JP2891920B2 - Output buffer circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output buffer circuit, and more particularly to an output buffer circuit having a CMOS structure in a semiconductor integrated circuit.

[0002]

2. Description of the Related Art In semiconductor integrated circuits, in recent years, there has been an increasing demand for an output buffer circuit having a large current driving capability and low noise. One such output buffer circuit is disclosed in JP-A-4-145717. FIG. 3 is a circuit diagram of the output buffer circuit described in the above publication. Referring to FIG.
Is an internal input terminal for receiving an internal signal A sent from a circuit inside the semiconductor integrated circuit having the output buffer circuit shown in FIG. The output terminal 21 is an external output terminal for extracting an output signal O corresponding to the internal signal to the outside of the semiconductor integrated circuit. Internal input terminal 20
Are connected to the input points of the inverters 1 and 3. The output signals B and F of the inverters 1 and 3 become the input signals of the inverters 2 and 4, respectively.

The output signal C of the inverter 2 is supplied to a delay circuit 5
Of the p-channel MOS field effect transistors (pMOS transistors) P1, P2 and P3 whose gate widths are divided into three
Gate input to 1 pMOS transistors P1,
The source electrodes of P2 and P3 are connected to the power supply line 22, and the drain electrodes are connected to the output terminal 21. On the other hand, the output signal G of the inverter 4 is divided into an input point of the delay circuit 7 and n-channel MOS field-effect transistors (nMOS transistors) N1, N2, N3 each having a gate width divided into three.
Of the nMOS transistors N1. The source electrodes of the nMOS transistors N1, N2, N3 are grounded to the ground line 23, and the drain electrodes are connected to the output terminal 21.

The output signal D of the delay circuit 5 becomes an input signal to the delay circuit 6 in the next stage and a gate input to the pMOS transistor P2, and further, a pMOS for pull-up.
This is supplied to the drain electrode of the transistor P4. The output signal H of the delay circuit 7 becomes an input signal to the delay circuit 8 in the next stage and a gate input to the nMOS transistor N2, and is further provided to the drain electrode of the pull-down nMOS transistor N4.

The output signal E of the delay circuit 6 becomes a gate input to the pMOS transistor P3 and, at the same time, is further applied to a drain electrode of a pull-up pMOS transistor P5. The output signal I of the delay circuit 8 becomes the gate input to the nMOS transistor N3, and is further supplied to the drain electrode of the pull-down nMOS transistor N5.

A pull-up pMOS transistor P
4 and P5, the source electrode is connected to the power supply line 22, and the output signal B of the inverter 1 is directly input to the gate electrode. On the other hand, the source electrodes of the pull-down nMOS transistors N4 and N5 are grounded to the ground line 23, and the output signal F of the inverter 3 is directly input to the gate electrode.

The above-described conventional output buffer circuit operates as follows. When the internal input signal A changes from low (L) level to high (H) level, the transistor N1
Is turned on, and the transistor P1 is turned off. Then, the transistor N2 is turned on by the signal H obtained by delaying the signal G input to the transistor N1 by the delay circuit 7. Further, the input signal H to the transistor N2
Is a signal I that has passed through the delay circuit 8 and is a transistor N3
Is made conductive. On the other hand, the pull-up transistors P4 and P4
Since P5 is turned on by the signal B, the transistor P5
2 and P3 are cut off without waiting for the gate inputs D and E transmitted through the delay circuits 5 and 6.

On the other hand, when the internal input signal A changes from the H level to the L level, the transistor P1 is turned on and the transistor N1 is turned off. The transistor P2 is turned on by the signal D delayed by the delay circuit 5 from the signal C input to the transistor P1. Further, the input signal D to the transistor P2 becomes the signal E through the delay circuit 6, and the transistor P3 is turned on. On the other hand, since the pull-down transistors N4 and N5 are turned on by the signal F, the transistors N2 and N3 receive the gate inputs H and I input through the delay circuits 7 and 8, respectively.
It will be cut off without waiting.

By the above operation, the output buffer circuit shown in FIG. 3 divides the gate widths of the pMOS transistor and the nMOS transistor into three, and inputs the delayed signals that have passed through the delay circuit sequentially to the gate electrodes of each of the divided transistors. This prevents the transistors from conducting at the same time and prevents the peaks of the currents flowing through the transistors from shifting, thereby suppressing fluctuations in the power supply potential and the ground potential due to the charging current and the discharging current when the transistors are conducting.

[0010]

The output buffer circuit shown in FIG. 3 has the following two problems. First,
In recent years, in response to the drive of large currents and diversification of needs of output buffer circuits, application to the use of connecting a large load such as connecting a coil to the outside, or multiple output buffer circuits by increasing the number of pins The situation where multiple simultaneous operations occur frequently is expanding. Under these circumstances, if the customer places strict demands on power supply noise and ground noise, a delay circuit and resistor for adjusting the conduction timing of the transistor are further delayed in order to enhance the noise reduction effect. Obtaining the desired timing, such as redesigning the transistor with a larger size or increasing the number of transistor divisions, involves a great deal of technical difficulty and an increase in the number of design steps. In addition, the use of delay circuits and resistors for adjusting the transistor conduction timing has a process dependence on the conduction timing. Therefore, if there is a change in the manufacturing process, the delay circuit and resistance etc. The timing adjustment section of the transistor must be redesigned.

Second, in the conventional output buffer circuit, a certain area is required because so-called analog means such as a resistor and a delay circuit are used for adjusting the transistor conduction timing. In addition, the area of other digital circuit blocks has been remarkably reduced in accordance with the recent progress in the miniaturization technology of semiconductor integrated circuits.
The area of the resistor and the delay circuit hardly decreases. Further, considering the case of a gate array, a standard cell, or the like, since the base of the cell is determined as a master, a considerable area is required if a resistor or a delay circuit is formed.

Both of the above two problems are based on the use of a delay circuit, a resistor or the like for adjusting the conduction timing of the divided transistors, that is, analogy.

Accordingly, the present invention relates to an output buffer circuit having a CMOS structure, in which the area is not increased, the transistor conduction timing does not depend on the manufacturing process, and the noise reduction effect is higher. And to provide an effective output buffer circuit.

[0014]

An output buffer circuit according to the present invention comprises a p-channel MOS field effect transistor and an n-channel MOS transistor.
Channel type MOS field effect transistor connected in series
A circuit of CMOS configuration using the series connection point as a signal output terminal.
N (n is an integer of 2 or more) paths, each signal output
Output buffers connected in parallel with common terminals
And a signal to be output via the output buffer unit.
Input signal to the data input terminal,
To the 2n data output terminals in synchronization with the
2n-bit parallel-out shift
Register and an inverted signal of the signal to be output to the outside.
Depending on the state, the first input terminal and the second input terminal respectively
Select one input data from two input data
2n output multiplexer with 2n sets of selection mechanisms for selecting and outputting
A multiplexer, wherein 2n bits of the shift register
Output data of each of the first input
Input to any of the 2nd input terminals
The shift register
To the first input terminal of the multiplexer.
At the input, the output data of the shift register is
Input in ascending order, and in the input to the second input terminal,
In addition to the configuration in which bits are input in descending order,
The 2n output signals of the multiplexer are output to the output buffer unit.
1n MOS field-effect transistors
Allocated one by one and given as gate input
It is characterized by having done.

According to the present invention, by dividing the gate width of the output transistor into a plurality of parts and sequentially delaying a common input signal to the gate electrode of each divided transistor, conduction and conduction of each divided transistor can be improved. In an output buffer circuit configured to shift the timing of non-conduction,
The means for adjusting the conduction and non-conduction of each of the transistors described above is constituted by a digital circuit to which a clock is input. For this reason, when changing the timing of the change of the conduction state of each transistor to, for example, a larger one, it is only necessary to increase the clock cycle, and unlike the timing adjusting means using a resistor or a delay circuit, there is no need to change the design. The occupied area of the circuit is unchanged. Further, even when the manufacturing process is changed, it is only necessary to adjust the clock cycle.

[0016]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram of an output buffer circuit according to one embodiment of the present invention. Referring to FIG. 1, the present embodiment includes an output buffer unit 30 having a CMOS configuration, and a timing adjustment unit 40 for adjusting the conduction / non-conduction timing of each transistor in output buffer unit 30. The input terminal 20 is an internal input terminal that receives an internal signal A sent from a circuit inside the semiconductor integrated circuit including the output buffer circuit.
The output terminal 21 is an external output terminal for extracting an output signal O corresponding to the internal signal A to the outside of the semiconductor integrated circuit.

In the output buffer unit 30, pMOS transistors P1 and n are connected between the power supply line 22 and the ground line 23.
A series connection circuit of the MOS transistor N1 and a series connection circuit of the pMOS transistor P2 and the nMOS transistor N2 are connected in parallel. The point of series connection of the transistor P1 and the transistor N1 and the transistor P1
2 and the transistor N2 are connected to the output terminal 21 in series. That is, this embodiment shows an example in which the gate width of each of the output pMOS transistor and the nMOS transistor is divided into two.

In the timing adjustment section 40, the internal input terminal 20 is connected to the input point of the inverter 11. The output signal J of the inverter 11 is input to the data terminal of the 4-bit shift register 41. The four-bit shift register 41 receives the clock CL input to the clock terminal.
When K rises, that is, when the signal changes from the L level to the H level, data input to the data terminal is output to the bit 1 output terminal. Data is shifted to the bit 2 output terminal. Similarly, the data at the bit 2 output terminal is shifted to the bit 3 output terminal, and the data at the bit 3 output terminal is shifted to the bit 4 output terminal. A clock CLK for dimming adjustment is input to a clock input terminal of the 4-bit shift register 41.

The output data B1 of the bit 1 output terminal among the four output data from the shift register 41 is input to the input terminals a1 and b4 of the multiplexer 42. The output data B2 of the bit 2 output terminal is
Are input to the input terminals a2 and b3. Output data B3 from the bit 3 output terminal is input to the input terminals a3 and b2 of the multiplexer 42. The output data B4 from the bit 4 output terminal is input to the input terminals a4 and a4 of the multiplexer 42.
Input to b1. When the input signal to the select input terminal SEL is at the H level, the multiplexer 42 outputs the input terminal a to the output terminals o1, o2, o3, and o4, respectively.
1, a2, a3, a4 output the input data, while
When the input signal to the select terminal SEL is at the L level, the output terminals o1, o2, o3, and o4 are connected to the input terminal b, respectively.
1, b2, b3, and b4 are output. The output signal J of the inverter 11 is input to the select terminal SEL of the multiplexer 42.

The output signal O1 of the output terminal o1 of the four output signals from the multiplexer 42 is input to the gate electrode of the pMOS transistor P1. Output terminal o2
Is input to the gate electrode of the pMOS transistor P2. The output signal O3 of the output terminal o3 is n
Input to the gate electrode of MOS transistor N2. The output signal O4 of the output terminal o4 is the nMOS transistor N
1 gate electrode.

Here, considering the above configuration as a functional block, a series connection circuit of a pMOS transistor P1 and an nMOS transistor N1 between a power supply line 22 and a ground line 23 and a series connection circuit of a pMOS transistor P2 and an nMOS transistor N2 The circuit can be viewed as an output buffer unit 30 having a series connection point of each transistor as an output point and each gate electrode as an input point.
In the present embodiment, this output buffer unit 30 is
In particular, it is considered as a buffer circuit having a large current driving capability.
On the other hand, a portion including the 4-bit shift register 41, the multiplexer 42, and the clock CLK is referred to as a timing adjustment unit 40 for shifting the change timing of the gate input of each transistor included in the output buffer unit 30. As is clear from the above description, a digital circuit is used as the timing adjustment unit 40.

FIG. 2 is a timing chart showing the waveform of each signal during the operation of the present embodiment shown in FIG. Referring to FIG. 2, the voltage waveform shown in FIG. 2 is applied to each node of the circuit shown in FIG. That is, the multiplexer 42 supplies the gate electrodes of the pMOS transistors P1 and P2 and the nMOS transistors N2 and N1 from the multiplexer 42, respectively.
Are supplied with signals O1 to O4 indicating voltage waveforms. As can be seen from this waveform, when the internal signal A to the internal input terminal 20 changes from L level to H level, the output signal J of the inverter 11 changes from H level to L level. At this time, first, the gate input O4 of the nMOS transistor N1 changes from H level to L level, and then the gate input O3 of the nMOS transistor N2 changes from H level to L level. Further thereafter, the pMOS transistor P2
Changes from the H level to the L level, and then the gate input O1 of the pMOS transistor P1 changes from the H level to the L level. That is, at this time, first, n
MOS transistors N1 and N2 are sequentially turned off, and then pMOS transistors P2 and P1 are sequentially turned on.

On the other hand, the same applies when the internal signal A to the internal input terminal 20 changes from H level to L level.
The gate inputs O1 and O2 of the S transistors P1 and P2 sequentially change from the L level to the H level to sequentially turn off the respective transistors, and then the gate inputs O3 and O4 of the nMOS transistors N2 and N1 sequentially change to the L level. To H level, and the respective transistors are sequentially turned on. The timing at which each transistor is sequentially turned on or turned off is determined by the cycle of the timing adjustment clock CLK to the 4-bit shift register 41.

As described above, in this embodiment mode, the transistors are first turned off sequentially, and then the transistors paired with them are turned on sequentially. Therefore,
A through current can be suppressed from flowing through each transistor for signal output, and a sudden large current can be reduced from flowing through the output buffer unit 30.

The case where the gate width division number of the output MOS transistor is two for the pMOS transistor and the nMOS transistor has been described above, but the same effect can be obtained even if the division number is two or more. Further, in the present embodiment, the digital circuit of the timing adjustment unit 40 is configured using basic blocks such as a 4-bit shift register and a multiplexer for convenience, but it should be a dedicated macro that performs such an operation. There will be.

[0026]

As described above, according to the present invention, the gate widths of the pMOS transistor and the nMOS transistor of the output buffer section are divided so that the divided transistors do not simultaneously transition to the conductive state or the non-conductive state. The timing adjustment unit that adjusts the timing is configured by a digital circuit that receives a timing adjustment clock without using a delay circuit or a resistor.

Thus, according to the present invention, even when the load is changed such that a large load such as a coil is connected to the outside, or when the customer requests noise reduction, the circuit constant can be reduced. No need to change the layout or
It is only necessary to adjust the cycle of the timing adjustment clock to an appropriate size. This has the effect of expanding the specifications of the output load value and the allowable range of noise in general-purpose products, particularly in ASICs such as gate arrays and standard cells, and further improving the versatility. or,
Since a digital circuit is used for the timing adjustment unit,
There is also an effect that the adjustment timing has no process dependency and the circuit correction and the layout correction due to the manufacturing process change become unnecessary.

In addition, since a resistor and a delay circuit are used in the timing adjustment section, noise reduction by driving with a large current can be reduced as compared with the conventional output buffer circuit in which the circuit area must be increased in order to increase the noise reduction effect. The higher the effect is, the smaller the area ratio is. This effect is particularly effective when applied to a semiconductor integrated circuit of a gate array or a standard cell whose base is determined as a master.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an output buffer circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart showing voltage waveforms of respective signals during operation of the output buffer circuit shown in FIG.

FIG. 3 is a circuit diagram of an example of a conventional output buffer circuit.

[Explanation of symbols]

 1, 2, 3, 4 Inverter 5, 6, 7, 8 Delay circuit 11 Inverter 20 Internal input terminal 21 External output terminal 22 Power supply line 23 Ground line 30 Output buffer unit 40 Timing adjustment unit 41 Shift register 42 Multiplexer

Continuation of the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H03K 17/16 H03K 17/687 H03K 19/0175 H03K 19/0948

Claims (1)

(57) [Claims] 1. A CMOS in which a p-channel type MOS field effect transistor and an n-channel type MOS field effect transistor are connected in series and a connection point of the serial connection is used as a signal output terminal.
An output buffer unit composed of n (n is an integer of 2 or more) configured circuits connected in parallel with common signal output terminals, and an inverted signal of a signal to be output via the output buffer unit A 2n-bit parallel-out shift register that sequentially shifts and outputs 2n data output terminals in synchronization with a clock input from the outside, and an inverted signal of the signal to be output to the outside A 2n output multiplexer comprising 2n sets of selection mechanisms for selecting and outputting one input data from two input data respectively input to the first input terminal and the second input terminal according to the state of Each of the 2n-bit output data of the register is divided and inputted to any one of the first input terminals and simultaneously inputted to any of the second input terminals. A multiplexer, wherein the output data of the shift register is input to a first input terminal of the multiplexer, the output data of the shift register is input in ascending bit order, and the input data is input to a second input terminal. Is configured to input in descending bit order, and outputs 2n output signals of the multiplexer,
An output buffer circuit, wherein each of the 2n MOS field-effect transistors constituting the output buffer section is assigned to a corresponding one of the MOS field-effect transistors and supplied as a gate input.