JPH09232930A - Output buffer circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent divided transistors(TRs) whose gate width is divided from being transited simultaneously to a conductive or nonconductive state by dividing the gate width of pMOS TRs and nMOS TRs of an output buffer section and using a timing adjustment section so as to adjust the state transmission timing. SOLUTION: When an internal signal A leading to an internal input terminal 20 changes from an L level to an H level, an output signal J of an inverter 11 changes from an H level to an L level. In this case, a gate input O4 of an nMOS TR N1 changes from an H level to an L level and then a gate input O3 of an nMOS TR N2 changes from an H level to an L level. Furthermore, a gate input O2 of a pMOS TR P2 changes from an H level to an L level and then a gate input O1 of a pMOS TR P1 changes from an H level to an L level. That is, at first the nMOS TRs N1, N2 are sequentially conductive and then the pMOS TRs P1, P2 are sequentially conductive.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output buffer circuit, and more particularly to an output buffer circuit having a CMOS structure in a semiconductor integrated circuit.

[0002]

2. Description of the Related Art In semiconductor integrated circuits, in recent years, there has been an increasing demand for an output buffer circuit having a large current driving capability and a small noise. One of such output buffer circuits is disclosed in Japanese Patent Application Laid-Open No. 4-145717. FIG. 3 is a circuit diagram of the output buffer circuit described in the above publication. Referring to FIG. 3, the input terminal 20
Is an internal input terminal that receives an internal signal A sent from a circuit inside the semiconductor integrated circuit including the output buffer circuit shown in FIG. The output terminal 21 is an external output terminal for taking out the output signal O corresponding to the above internal signal to the outside of the semiconductor integrated circuit. Internal input terminal 20
Is connected to the input points of the inverters 1 and 3. The output signals B and F of the inverters 1 and 3 become the input signals of the inverters 2 and 4, respectively.

The output signal C of the inverter 2 is supplied to the delay circuit 5
Of the p-channel type MOS field effect transistors (pMOS transistors) P1, P2, P3 whose gate width is divided into three.
It becomes the gate input to 1. pMOS transistor P1,
Source electrodes of P2 and P3 are connected to the power supply line 22, and drain electrodes thereof are connected to the output terminal 21. On the other hand, the output signal G of the inverter 4 is an input point of the delay circuit 7 and an n-channel MOS field effect transistor (nMOS transistor) N1, N2, N3 whose gate width is divided into three.
Of these, it becomes a gate input to the nMOS transistor N1. The source electrodes of the nMOS transistors N1, N2, N3 are grounded to the ground line 23, and the drain electrodes are connected to the output terminal 21.

The output signal D of the delay circuit 5 becomes an input signal to the delay circuit 6 of the next stage and a gate input to the pMOS transistor P2, and at the same time, further pull-up pMOS.
It is applied to the drain electrode of the transistor P4. The output signal H of the delay circuit 7 serves as an input signal to the delay circuit 8 of the next stage and a gate input to the nMOS transistor N2, and at the same time, is further given to the drain electrode of the pull-down nMOS transistor N4.

The output signal E of the delay circuit 6 serves as a gate input to the pMOS transistor P3 and, at the same time, is applied to the drain electrode of the pull-up pMOS transistor P5. The output signal I of the delay circuit 8 serves as a gate input to the nMOS transistor N3 and, at the same time, is applied to the drain electrode of the pull-down nMOS transistor N5.

PMOS transistor P for pull-up
The source electrode of each of P4 and P5 is connected to the power supply line 22, and the output signal B of the inverter 1 is directly input to the gate electrode. On the other hand, in each of the pull-down nMOS transistors N4 and N5, the source electrode is grounded to the ground line 23, and the output signal F of the inverter 3 is directly input to the gate electrode.

The conventional output buffer circuit described above operates as follows. When the internal input signal A changes from the low (L) level to the high (H) level, the transistor N1
Are turned on, and the transistor P1 is turned off. Then, the transistor N2 becomes conductive by the signal H input to the transistor N1 delayed by the delay circuit 7. Further, the input signal H to the transistor N2
Becomes the signal I that has passed through the delay circuit 8 and is the transistor N3.
Is made conductive. On the other hand, the pull-up transistor P4
Since P5 is conducted by the signal B, the transistor P
2, 2 and 3 are cut off without waiting for the gate inputs D and E transmitted through the delay circuits 5 and 6.

On the other hand, when the internal input signal A changes from H level to L level, the transistor P1 is turned on and the transistor N1 is turned off. Then, the transistor P2 is rendered conductive by the signal D input to the transistor P1 and delayed by the delay circuit 5. Further, the input signal D to the transistor P2 becomes the signal E which has passed through the delay circuit 6 and makes the transistor P3 conductive. On the other hand, since the pull-down transistors N4 and N5 are rendered conductive by the signal F, the transistors N2 and N3 are supplied to the gate inputs H and I through the delay circuits 7 and 8, respectively.
It will be cut off without waiting for.

With the above operation, the output buffer circuit shown in FIG. 3 divides the gate widths of the pMOS transistor and the nMOS transistor into three, and inputs the delay signal sequentially passed through the delay circuit to the gate electrode of each transistor after the division. By doing so, it is possible to prevent simultaneous conduction of the transistors and to make the peaks of the currents flowing through the transistors deviate, thereby suppressing fluctuations of the power supply potential and the ground potential due to the charging current and the discharging current when the transistors are conducting.

[0010]

The above-mentioned output buffer circuit shown in FIG. 3 has the following two problems. First,
2. Description of the Related Art In recent years, in response to a large current drive of output buffer circuits and diversification of needs, application to a large load connection such as connecting a coil to the outside, or multiple output buffer circuits by increasing the number of pins The situation in which multiple simultaneous operations occur frequently is expanding. Under such circumstances, when the customer makes strict requirements for power supply noise and ground noise, delay circuits such as delay circuits and resistors for adjusting the conduction timing of transistors should be delayed in order to enhance the noise reduction effect. In order to obtain a desired timing, such as redesigning into a large size or increasing the number of divided transistors, a great deal of technical difficulty and an increase in design man-hours are involved. In addition, since the conduction timing is process-dependent due to the use of a delay circuit and a resistor for adjusting the conduction timing of the transistor, whenever the manufacturing process is changed, the delay circuit, the resistance, or the like is changed. The transistor timing adjuster must be redesigned.

Secondly, in the conventional output buffer circuit, since the so-called analog means such as a resistor and a delay circuit is used for adjusting the conduction timing of the transistor, a certain area is required. Moreover, the area of other digital circuit blocks is remarkably reduced with the progress of miniaturization technology of semiconductor integrated circuits in recent years,
The resistance and the area of the delay circuit do not become small. Further, considering the case of a gate array or a standard cell, since the base of the cell is determined as a master, it takes a considerable area to build a resistor and a delay circuit.

Both of the above two problems are based on what is called an analog means of using a delay circuit or a resistor for adjusting the conduction timing of the divided transistors.

Therefore, the present invention is an output buffer circuit having a CMOS structure, in which the area is not increased, the conduction timing of the transistor does not depend on the manufacturing process, and the noise reduction effect is higher. It is an object of the present invention to provide an effective output buffer circuit for use in.

[0014]

In the output buffer circuit of the present invention, the gate width of each of the p-channel MOS field effect transistor and the n-channel MOS field effect transistor for outputting a signal to the outside is made plural. The output buffer section of the divided CMOS structure and the common input signal to the gate electrodes of the respective transistors after the division are sequentially delayed so as to change the conduction state to the non-conduction state or non-conduction state of the respective transistors after the division. It is characterized by comprising at least a digital circuit having a clock as an input, which adjusts the timing of the state transition from the conductive state to the conductive state so as to shift between the transistors.

According to the present invention, the gate width of the output transistor is divided into a plurality of lines, and a common input signal to the gate electrode of each transistor after the division is sequentially delayed, so that each of the divided transistors becomes conductive. In the output buffer circuit configured to shift the timing of non-conduction,
The means for adjusting conduction / non-conduction of each of the above transistors is configured by a digital circuit to which a clock is input. For this reason, when changing the timing of the change in the conduction state of each transistor to, for example, the larger one, it is only necessary to increase the clock cycle, and unlike the timing adjusting means using a resistor or a delay circuit, there is no need to change the design. The occupied area of the circuit is unchanged. Further, even if the manufacturing process is changed, it is only necessary to adjust the clock cycle.

[0016]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram of an output buffer circuit according to an embodiment of the present invention. With reference to FIG. 1, the present embodiment includes an output buffer section 30 having a CMOS structure, and a timing adjusting section 40 for adjusting the conduction / non-conduction timing of each transistor in the output buffer section 30. The input terminal 20 is an internal input terminal that receives an internal signal A sent from a circuit inside the semiconductor integrated circuit including the output buffer circuit.
The output terminal 21 is an external output terminal for taking out the output signal O corresponding to the internal signal A to the outside of the semiconductor integrated circuit.

In the output buffer section 30, the pMOS transistors P1 and n are provided between the power supply line 22 and the ground line 23.
A series connection circuit of the MOS transistor N1 and a series connection circuit of the pMOS transistor P2 and the nMOS transistor N2 are connected in parallel. A series connection point between the transistor P1 and the transistor N1 and the transistor P
The series connection points of 2 and the transistor N2 are connected to the output terminal 21, respectively. That is, the present embodiment shows an example in which the gate width of each of the pMOS transistor and the nMOS transistor for output is divided into two.

In the timing adjusting section 40, the internal input terminal 20 is connected to the input point of the inverter 11. The output signal J of the inverter 11 is input to the data terminal of the 4-bit shift register 41. The 4-bit shift register 41 has a clock CL input to a clock terminal.
When K rises, that is, changes from the L level to the H level, the data input to the data terminal is output to the bit 1 output terminal, and further, the bit 1 output terminal at the clock rising immediately before the clock rising is Shift data to bit 2 output. Similarly, the data of the bit 2 output terminal is shifted to the bit 3 output terminal, and the data of the bit 3 output terminal is shifted to the bit 4 output terminal. A clock CLK for dimming adjustment is input to the clock input terminal of the 4-bit shift register 41.

Of the four output data from the shift register 41, the output data B1 at the bit 1 output terminal is input to the input terminals a1 and b4 of the multiplexer 42. The output data B2 from the bit 2 output terminal is sent to the multiplexer 42.
Is input to the input terminals a2 and b3. The output data B3 from the bit 3 output terminal is input to the input terminals a3 and b2 of the multiplexer 42. The output data B4 from the bit 4 output terminal is input to the input terminal a4 of the multiplexer 42.
Input to b1. When the input signal to the select input terminal SEL is at H level, the multiplexer 42 described above outputs to the output terminals o1, o2, o3 and o4 respectively.
Output the input data to 1, a2, a3, a4, while
When the input signal to the select terminal SEL is at L level, the output terminals o1, o2, o3, and o4 respectively receive the input terminal b
The input data to 1, b2, b3, b4 is output. The output signal J of the inverter 11 is input to the select terminal SEL of the multiplexer 42.

Of the four output signals from the multiplexer 42, the output signal O1 at the output terminal o1 is input to the gate electrode of the pMOS transistor P1. Output terminal o2
Output signal O2 is input to the gate electrode of the pMOS transistor P2. The output signal O3 from the output terminal o3 is n
It is input to the gate electrode of the MOS transistor N2. The output signal O4 from the output terminal o4 is the nMOS transistor N
1 gate electrode.

Here, considering the above-mentioned configuration as a functional block, a series connection circuit of the pMOS transistor P1 and the nMOS transistor N1 between the power supply line 22 and the ground line 23, and a series connection of the pMOS transistor P2 and the nMOS transistor N2. The circuit can be regarded as an output buffer section 30 in which each transistor has a series connection point as an output point and each gate electrode as an input point.
In the present embodiment, this output buffer unit 30 is
Especially, it is considered as a buffer circuit having a large current driving capability.
On the other hand, the portion including the 4-bit shift register 41, the multiplexer 42, and the clock CLK is regarded as the timing adjusting unit 40 for shifting the change timing of the gate input of each transistor forming the output buffer unit 30. As is clear from the above description, it is understood that a digital circuit is used as the timing adjusting section 40.

FIG. 2 is a timing chart showing the waveform of each signal during the operation of the present embodiment shown in FIG. Referring to FIG. 2, the voltage waveform shown in this figure is applied to each node of the circuit shown in FIG. That is, the gate electrodes of the pMOS transistors P1 and P2 and the nMOS transistors N2 and N1 are input from the multiplexer 42 to the gate electrodes of FIG.
Signals O1 to O4 indicating voltage waveforms are input to the. As can be seen from this waveform, when the internal signal A to the internal input terminal 20 changes from the L level to the H level, the output signal J of the inverter 11 changes from the H level to the L level. At this time, first, the gate input O4 of the nMOS transistor N1 changes from H level to L level, and then the gate input O3 of the nMOS transistor N2 changes from H level to L level. After that, the pMOS transistor P2
The gate input O2 of the pMOS transistor P1 changes from the H level to the L level, and then the gate input O1 of the pMOS transistor P1 changes from the H level to the L level. That is, at this time, first, n
The MOS transistors N1 and N2 are sequentially turned off, and then the pMOS transistors P2 and P1 are sequentially turned on.

The same applies when the internal signal A to the internal input terminal 20 changes from H level to L level.
The gate inputs O1 and O2 of the S transistors P1 and P2 are sequentially changed from the L level to the H level, and the respective transistors are sequentially turned off. Then, the gate inputs O3 and O4 of the nMOS transistors N2 and N1 are sequentially set to the L level. Changes from H level to H level, and each transistor is sequentially turned on. The timing of sequentially turning on or off each transistor is determined by the cycle of the timing adjustment clock CLK to the 4-bit shift register 41.

As described above, in this embodiment, the transistors are sequentially made non-conductive first, and then the transistors paired with them are sequentially made conductive. Therefore,
A through current can be suppressed from flowing in each signal output transistor, and a sudden large current can be alleviated from flowing into the output buffer section 30.

The case where the gate width of the output MOS transistor is divided into two parts, the pMOS transistor and the nMOS transistor, has been described above, but the same effect can be obtained even if the number of divided parts is two or more. Further, in the present embodiment, the digital circuit of the timing adjusting unit 40 is constructed by using the basic blocks of the 4-bit shift register and the multiplexer for the sake of convenience, but it should normally be in the form of a dedicated macro that performs such an operation. Ah

[0026]

As described above, according to the present invention, the gate widths of the pMOS transistor and the nMOS transistor of the output buffer section are divided so that the divided transistors do not transit to the conductive state or the non-conductive state at the same time. The timing adjusting unit for adjusting the timing is configured by a digital circuit that receives the timing adjusting clock as an input, without using a delay circuit or a resistor.

Thus, according to the present invention, even when the load is changed such as connecting a large load such as a coil to the outside, or when the customer requests noise reduction, the circuit constants are reduced. No need to change the layout
It is sufficient to adjust the cycle of the timing adjustment clock to an appropriate size. This has the effect of expanding the specifications of the output load value and the allowable range of noise in a general-purpose product, particularly in an ASIC such as a gate array or a standard cell, and further increasing versatility. or,
Since a digital circuit is used for the timing adjustment unit,
The adjustment timing does not depend on the process, and the circuit modification and layout modification due to the manufacturing process change are not required.

Moreover, noise is reduced by driving a large amount of current as compared with a conventional output buffer circuit which requires a large circuit area in order to improve the noise reduction effect by using a resistor and a delay circuit in the timing adjustment section. The higher the effect, the smaller the area ratio. This effect is particularly effective when applied to a gate array whose base is determined as a master or a semiconductor integrated circuit of a standard cell.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an output buffer circuit according to an embodiment of the present invention.

FIG. 2 is a timing diagram showing voltage waveforms of respective signals during operation in the output buffer circuit shown in FIG.

FIG. 3 is a circuit diagram of an example of a conventional output buffer circuit.

[Explanation of symbols]

 1, 2, 3, 4 Inverter 5, 6, 7, 8 Delay circuit 11 Inverter 20 Internal input terminal 21 External output terminal 22 Power supply line 23 Ground line 30 Output buffer section 40 Timing adjustment section 41 Shift register 42 Multiplexer

Claims (3)

[Claims] 1. A p-channel MO for outputting a signal to the outside.
An output buffer unit having a CMOS structure in which the gate width of each of the S-type field effect transistor and the n-channel type MOS field effect transistor is divided into a plurality, and a common gate electrode for each transistor after the division. An input signal is sequentially delayed, and adjustment is performed so that the timing of the state transition from the conducting state to the non-conducting state or from the non-conducting state to the conducting state in each transistor after the division is shifted between the transistors, and the clock is input. An output buffer circuit comprising at least a digital circuit. 2. A CM in which a p-channel type MOS field effect transistor and an n-channel type MOS field effect transistor are connected in series, and the series connection point is used as a signal output terminal.
A plurality of circuits having an OS configuration are connected in parallel with their respective signal output terminals being connected in parallel, and a signal and a clock to be output to the outside via the output buffer unit are input, and the external From the signal that should be output to
Generating a digital signal in synchronization with the clock, which shifts the state of each transistor of the output buffer unit from a conducting state to a non-conducting state or from a non-conducting state to a conducting state at different timings between the transistors. An output buffer circuit comprising at least a digital circuit. 3. A CMOS in which a p-channel type MOS field effect transistor and an n-channel type MOS field effect transistor are connected in series, and the series connection point serves as a signal output terminal.
An output buffer unit in which n (n is an integer of 2 or more) circuit configurations are connected in parallel with their respective signal output terminals in common, and an inverted signal of a signal to be output via the output buffer unit. 2n-bit parallel-out shift register that outputs the data to the data input terminal, sequentially shifts to 2n data output terminals in synchronization with a clock input from the outside, and an inverted signal of the signal to be output to the outside. A 2n-output multiplexer having 2n sets of selection mechanisms for selecting and outputting one input data from the two input data respectively input to the first input terminal and the second input terminal according to the state of Each of the 2n-bit output data of the register is divided and input to one of the first input terminals and simultaneously input to one of the second input terminals. A multiplexer, wherein the output data of the shift register is input to the first input terminal of the multiplexer, the output data of the shift register is input in bit increasing order, and the input data is input to the second input terminal. Is configured to be input in the descending order of bits, and the 2n output signals of the multiplexer are assigned to the 2n MOS field effect transistors forming the output buffer section one by one and supplied as gate inputs. An output buffer circuit having the above-mentioned configuration.