JP3183494B2 - Timing signal generation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a timing signal generating circuit for use in an electronic device such as an IC test system, which generates a high-resolution timing signal by preventing a decrease in accuracy caused by temperature fluctuations and power supply fluctuations. It is about.

[0002]

2. Description of the Related Art With the speeding up of electronic circuits, higher resolution and higher accuracy of timing signals used in electronic equipment have been required. FIG. 7 shows an example of a timing signal generation circuit using the synchronous down counter 10.
In this case, the delay data is set in the synchronous down counter 10 by the LOAD signal, and then the set data is decremented by one in synchronization with the CLK signal, and the synchronous down counter 10 becomes "0". In AllZero
A signal is output, and a timing signal indicating a delay time that is an integral multiple of the CLK signal period can be generated.

In this case, a highly accurate timing signal can be obtained by using a CLK signal using a highly accurate crystal oscillator. However, there is a limit to the operation speed of the synchronous down counter 10, and high resolution, for example, C
It is not possible to easily generate a timing signal of 10 ns or less by setting the period of the LK signal to 10 ns or less.

FIG. 8 shows an example of a circuit for generating a timing signal by setting delayed data of a CLK cycle or less. The output signal AllZero signal of the synchronous down counter 10 is
The buffer 3 is input simultaneously to the terminal A of the selector A21.
Input to terminal B via 1 By selecting the A terminal or the B terminal of the selector A21, the buffer 31
The timing signal can be generated by switching the delay time of one stage.

[0005] The output signal of the selector A21 is
At the same time as input to the A terminal 22, the signal is input to the B terminal via the buffer 31 in two stages. By selecting the terminal A or the terminal B of the selector B22, a delay signal for two stages of the buffer 31 can be switched to generate a timing signal.

Similarly, the output signal of the selector B22 is
The buffer 3 is input simultaneously to the terminal A of the selector C23.
1 is input to the B terminal via four stages. This selector C2
By selecting the A terminal or the B terminal of No. 3, a delay signal for four stages of the buffer 31 can be switched to generate a timing signal.

Further, similarly, by connecting and selecting buffers 31 for eight stages and sixteen stages, a timing signal is generated with a delay time obtained by dividing a delay time for one cycle of a CLK signal into a plurality of stages. Can be.

This method has the following disadvantages because the unit of the delay time is the delay time Tpd of one stage of the buffer 31. The delay time Tpd fluctuates due to changes in the ambient temperature of the IC and the power supply voltage applied to the IC, causing an error in the timing signal. Due to manufacturing variations of IC, the delay time Tpd
Therefore, a timing signal error occurs. The cycle of the signal passing through the buffer 31 changes according to the value of the delay data set in the synchronous down counter 10, whereby the self-heating amount of the buffer 31 fluctuates, and the delay time Tpd fluctuates due to the temperature fluctuation resulting from the change. Generates signal errors. This is particularly noticeable in a CMOS circuit that consumes less power at rest.

The fluctuation of the delay time Tpd as described above generates a discontinuous point every 1 CLK period as shown in FIG. In the circuit of FIG. 8, when 1CLK is divided by m buffers 31, when the delay time Tpd is larger than the value of 1CLK time / m, a discontinuous point as shown by a solid line in FIG. 9 occurs.
When the delay time Tpd is smaller than the value of 1 CLK time / m, a discontinuous point as shown by a dotted line in FIG. 9 occurs.

In the circuit of FIG. 8, there is a delay of a timing signal by a plurality of selectors, apart from the delay time by the buffer 31. This delay does not affect the variable delay time due to the buffer 31, but has an effect on the timing signal, and the delay amounts of the plurality of selectors fluctuate for the same reason as described above, causing an error in the timing signal.

[0011]

When a timing signal is generated by setting delay data equal to or less than a CLK cycle by a conventional method, a change in temperature and power supply voltage applied to the IC, manufacturing variations of the IC, and a buffer for delaying the IC. The temperature fluctuation due to the fluctuation of the self-heating amount of 31, the delay due to the plurality of selector circuits and the delay fluctuation cause the error of the timing signal,
Its accuracy was not good. SUMMARY OF THE INVENTION It is an object of the present invention to generate a high-resolution and high-precision timing signal by preventing disturbance such as temperature fluctuation and power supply fluctuation applied to an IC, fluctuation of self-heating and deterioration of timing accuracy caused by a circuit configuration.

[0012]

In order to achieve the above object, a timing signal generating circuit according to the present invention is configured as follows. In other words, m for inputting the CLK signal
Variable delay circuit 120 in which two variable delay elements are cascaded
A phase comparator 140 that compares the phase of the output signal e1 of the variable delay circuit 120 with the phase of the CLK signal e2, and a feedback circuit 150 that feeds back the output of the phase comparator 140 to the m variable delay elements. A phase-locked loop circuit unit 100 is provided. A synchronous delay circuit for generating an output signal of a delay time at an integer multiple of the CLK period based on the upper digit of the delay data; a decoder for decoding a lower digit of the delay data; 110 and the decoder 160
And a selector signal that selects one of the outputs of the m variable delay elements and generates a timing signal that is an integral multiple of 1 / m of the CLK cycle. The signal selection circuit unit 200 is provided.

Here, the variable delay element of the variable delay circuit 120 is an inverter constituted by a dual gate MOSFET, and becomes positive logic and negative logic for each output of the variable delay element. Is also good.
Further, the output of the feedback circuit 150 of the phase-locked loop circuit section 100 may convert the delay control signal into a binary signal to control the delay time of the variable delay element. Furthermore, one phase-locked loop circuit unit 100 and the phase-locked loop circuit unit 100
, A plurality of timing signal selection circuit units 200 that generate timing signals by using outputs of the m variable delay elements, respectively.

[0014]

In the timing signal generating circuit configured as described above, the m-stage variable delay circuit always has a high precision C signal.
It operates in synchronization with LK, and the self-heating amount is stable. For this reason, the phase locked loop circuit section only has to respond to disturbance such as temperature fluctuation and power supply fluctuation applied to the IC. Further, since the variable delay circuit is composed of m stages of variable delay elements for minute delay, a high-precision signal having a period of 1 / m of the CLK period can be obtained, and a high-resolution timing signal can be generated. it can.

[0015]

【Example】

(Embodiment 1) FIG. 1 shows an embodiment of a timing signal generating circuit according to the present invention. The circuit can be broken down into the following blocks: Variable delay circuit 120 Variable delay elements of m stages are connected in cascade. At this time
Is the number of timings for dividing 1 CLK. And
The feedback circuit 150 controls the variable delay time, which is the sum of the delay times of the m-stage variable delay elements, to be 1 CLK. Phase comparator 140 is a circuit that outputs a voltage or a current proportional to the phase difference between two input signals e1 and e2. The charge pump is included in this block. Here, e1 represents the CLK signal as 1CLK.
The final output of the variable delay circuit 120 delayed by
Is the CLK signal itself. Feedback circuit 150 Variable delay circuit 120, phase comparator 140, and feedback circuit 1
50 is a circuit for determining the frequency characteristic of the phase locked loop circuit unit 100 including a filter for determining the frequency characteristic. Note that the variable delay circuit 120 always operates in synchronization with a fixed clock, and self-heating is constant. That is, the negative feedback loop only needs to respond to disturbances caused by temperature and voltage fluctuations, and does not need high-speed response characteristics. The selector circuit 130 is a circuit that selects one of the m output signals from the variable delay elements of the variable delay circuit 120 based on the lower order digit of the delay data and extracts it as a timing signal. Synchronous delay circuit 110 Generates an output signal of a delay time at a resolution of an integral multiple of the CLK cycle based on the upper digits of the delay data. One of m outputs from the variable delay elements of the variable delay circuit 120 is selected based on the output of this circuit and the selection signal, and is output as a timing signal. The decoder 160 generates a selection signal for selecting one of the m outputs from the variable delay elements of the variable delay circuit 120 based on the lower digits of the delay data.

The method of generating a delay time that is an integral multiple of the CLK period is performed by the synchronous delay circuit 110 as in the conventional case. In order to generate a minute delay of 1 / m of the CLK cycle, the delay time of one stage of the variable delay element constituting the variable delay circuit 120 is adjusted by the feedback circuit 150 so that the delay time becomes 1 / m of the CLK cycle. Controlling. That is, the entire delay time of the m-stage variable delay element is equal to the cycle of CLK. The output of each variable delay element of the variable delay circuit 120 composed of m stages of variable delay elements is obtained by equally dividing CLK into m phases. One of the m-phase CLKs is selected by the selector circuit 130. The selector circuit 130 is also controlled by the output of the synchronous delay circuit 110.

FIG. 2 shows the timing when m = 4. The synchronous delay circuit 110 counts CLKs for the number of times n, which is the upper digit of the set delay data, and generates an output signal at the n-th CLK. During the period of this output signal, the selector circuit 130 operates, and the m-phase CL
One of K is selected by a selection signal, and a timing signal is output. At this time, the signal at the subsequent stage of the m-phase CLK occurs in the latter half of the period of the output signal of the synchronous delay circuit 110, and the pulse width of the timing signal becomes narrow. Delay circuit 13
The output of No. 1 is a period of the output signal. This delay circuit 131
Is appropriately inserted according to the division number m and the pulse width of the output signal of the synchronous delay circuit 110. Also, the decoder 160
The selection signal from to the selector circuit 130 is supplied unchanged during the generation of the timing signal.

FIG. 3 shows an example of a variable delay element capable of voltage control in the variable delay circuit 120. FIG. 3 (a)
This is a general CMOS inverter. This power supply voltage V _CP
And it is possible to control the delay time Tpd by changing the V _CN. FIG. 3B shows that the ON resistances of Q3 and Q4 are not controlled by the power supply voltage but V _CP and V _CN.
Is a circuit that changes the delay time Tpd by controlling the delay time Tpd. FIG. 3 (c) uses a dual-gate MOSFET instead of a single-gate MOSFET.
In this case, Pch and Nch dual gate MOSF
Connect one G (gate) of ET as an input terminal and D
(Drains) are connected to each other and used as output terminals. Here, G1, G1,
Since the static characteristic between D and S (source) can be variably controlled by G2, for example, when the voltage of IN is V _DD , the Nch dual gate MOSFET is turned on,
The ON resistance at this time can be continuously varied by controlling the voltage applied to V _CN . Then, the output transition time determined by the product of the ON resistance, the wiring capacitance, and the input capacitance Cs of the next stage can be controlled by V _CN . This means that the Pch dual gate MO
The same applies to the SFET, and the ON resistance of the Pch dual-gate MOSFET can be controlled by V _CP .

The term “ON resistance” is used for the inverters shown in FIGS. 3B and 3C to simplify the description, but these ON resistances have a non-linear characteristic with respect to the input gate voltage. Therefore, for example, correctly in FIG. 3C, it can be said that the transition time of the output waveform is controlled by controlling the drain current _ID determined by the voltage between G1, D, and S by G2. The higher the V _CN and the lower the V _CP , the higher the _{ID, and} thus the shorter the transition time and the shorter the delay time. FIG. 3 (a)
In both FIGS. 3 (b) and 3 (c), the delay time is controlled by changing the two values of V _CP and V _CN , but one is fixed and the voltage change of only the other is performed. May control the delay time.

FIG. 4 shows an example of the delay control signal generator in the case where the delay control signal of the feedback circuit 150 is converted into a binary value to control the delay time of the variable delay element.

Incidentally, the variable delay element shown in FIG.
It is an inverter. Therefore, the variable delay circuit 12 shown in FIG.
In order to make the same logic as the variable delay element shown in FIG.
One inverter may be connected to the output of the variable delay element as shown in FIG. Also, as shown in FIG. 5A, variable delay elements may be connected in cascade, positive logic and negative logic signals may be output for each element, and the selector circuit 130 may match the logic.

(Embodiment 2) FIG. 6 shows a circuit when a plurality of timing signals are required. In this case, the variable delay circuit 1
20 forms a phase locked loop circuit unit 100 configured with a phase comparator 140 and a feedback circuit 150;
Regardless of the synchronous delay circuit 110 and the selector circuit 130, a stable delay circuit is formed in synchronization with CLK. Therefore, the output from the variable delay element of the variable delay circuit 120 can be shared by the plurality of timing signal selection circuit units 200. At this time, the delay time in the selector circuit 130 can be stabilized by supplying the delay control signal generated from the feedback circuit 150 to the selector circuit 130 as well.

[0023]

Since the present invention is configured as described above, it has the following effects. In other words, a timing signal can be generated with high precision at a resolution smaller than the CLK cycle, and the timing signal fluctuates due to changes in temperature and power supply voltage, fluctuations in IC manufacturing, and fluctuations in self-heating. There is no. Therefore, the circuit according to the present invention is useful because it can generate a high-resolution timing signal with high accuracy.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a timing signal generation circuit of the present invention.

FIG. 2 is a timing chart when m = 4 in one embodiment of the timing signal generation circuit of the present invention.

FIG. 3 is a circuit diagram showing one example of a variable delay element capable of voltage control according to the present invention.

FIG. 4 is an explanatory diagram showing one example of a driver of the variable delay element of the present invention.

FIG. 5 is a circuit diagram showing an example of a variable delay circuit according to the present invention.

FIG. 6 is a block diagram showing one embodiment of a multiple timing signal generation circuit of the present invention.

FIG. 7 is a block diagram of a timing signal generation circuit using a conventional synchronous down counter.

FIG. 8 is a circuit block diagram for generating a timing signal by setting delay data equal to or less than a CLK cycle in the related art.

FIG. 9 is an explanatory diagram showing a relationship between a set value of a timing signal and a delay time in a conventional circuit that sets a delay data equal to or less than a CLK cycle and generates a timing signal.

[Explanation of symbols]

 Reference Signs List 10 synchronous down counter 21 selector A 22 selector B 23 selector C 31 buffer 100 phase locked loop circuit unit 110 synchronous delay circuit 120 variable delay circuit 130 selector 131 delay circuit 140 phase comparator 150 feedback circuit 160 decoder 200 timing signal selection circuit Department

Claims (5)

(57) [Claims] 1. A variable delay circuit (120) in which m variable delay elements for inputting a CLK signal are connected in cascade, an output signal e1 of the variable delay circuit (120) and a CLK signal e2.
And a feedback circuit (150) that feeds back the output of the phase comparator (140) to the m variable delay elements, respectively. 100), and a synchronous delay circuit (110) for generating an output signal having a delay time at an integral multiple of the CLK cycle based on the upper digits of the delay data.
A decoder (160) for decoding the lower-order digit of the delay data; an output signal of the synchronous delay circuit (110) and a selection signal output from the decoder (160); And a selector circuit (200) comprising a selector circuit (130) for selecting one of the outputs of the above (1) and (2) and generating a timing signal of an integral multiple of 1 / m of the CLK cycle. Timing signal generating circuit. 2. A delay control signal of an output of a feedback circuit (150).
Is also supplied to a selector circuit (130).
The delay time of the circuit (130) is stabilized.
On-board timing signal generation circuit. 3. A phase locked loop circuit section (100).
Using the outputs of the m variable delay elements
Timing signal selection circuit section for generating a timing signal
The timing of claim 1, comprising (200).
Signal generation circuit. 4. A variable delay element of a variable delay circuit (120).
Is an inverter composed of dual-gate MOSFETs.
And positive logic and negative logic for each output of the variable delay element.
That is, matching the logic by the selector circuit (130)
4. A timing signal generator according to claim 1, 2 or 3.
Raw circuit. 5. The feedback of the phase locked loop circuit section (100).
The output of the circuit (150) outputs the delay control signal to binary (V _DD −
ΔV, V _SS + ΔV), and converts the gate voltage (V _CP ,
V _CN ) to control the delay time of the variable delay element.
The method according to claim 1, 2, 3, or 4, wherein
Timing signal generation circuit.