JP5850975B2 - Pulse generation circuit, sample hold circuit, solid-state imaging device - Google Patents

Description

The present invention relates to a pulse generation circuit, a sample hold circuit, and a solid-state imaging device.

  Semiconductor devices such as solid-state imaging devices are steadily increasing in speed, and it is necessary to finely adjust the phase relationship of the drive pulses. Patent Document 1 discloses a pulse edge selection circuit that adjusts the edge timing of a pulse by register setting. In this patent document 1, a clock is selected by a selector in a tournament system using a transfer gate from a multiphase clock.

JP 2009-045579 A

  However, the clock selection method using a tournament type selector as in Patent Document 1 is driven by inputting a clock to a logic gate such as a buffer that is not selected, so that power consumption increases. For example, when one clock is selected from N clocks, N / 2 clocks are selected by the first-stage logic gate. Next, an operation is performed in which N / 4 clocks are selected by the second-stage logic gate and narrowed down to one clock by the output-stage logic gate. For this reason, at least N−1 (= N / 2 + N / 4 +... +1) logic gates are moved by the clock. When a clock is input to the logic gate, power consumption increases due to a through current, and thus the tournament clock selection circuit consumes a large amount of power. Note that the logic gate here is a NAND gate, a NOR gate, an inverter, a buffer, a tristate inverter, a tristate buffer, a transfer gate, or the like.

The present invention provides a pulse generation circuit in which the number of logic gates being driven is reduced to reduce power consumption, and the number of logic gates through which a clock passes is reduced to shorten the clock delay.

One aspect of the present invention is a pulse generation circuit that generates a pulse, a rising edge position selection circuit including a first NOR gate, a plurality of first NAND gates, a second NOR gate, A falling edge position selection circuit having a plurality of second NAND gates, and an edge detection circuit, wherein the output of each of the plurality of first NAND gates is output from the rising edge position selection circuit. Connected to a first NOR gate, each of the plurality of first NAND gates is connected to at least a wiring for supplying any one of a plurality of clocks having different phases, and the plurality of first NAND gates In order to determine the position of the rising edge of the pulse among the plurality of clocks with respect to one first NAND gate of the NAND gates The selected first clock is supplied, and the one first NAND gate supplies a signal having a rising edge synchronized with the first clock to the first NOR gate, and the first NOR gate. The gate outputs a first signal having a falling edge synchronized with the first clock. In the falling edge position selection circuit, each output of the plurality of second NAND gates is the second signal. Connected to a NOR gate, each of the plurality of second NAND gates is connected to at least a wiring for supplying any of the plurality of clocks, and one of the plurality of second NAND gates is connected. A second clock selected to determine a position of a falling edge of the pulse among the plurality of clocks for one second NAND gate; The one second NAND gate is supplied with a signal having a rising edge synchronized with the second clock to the second NOR gate, and the second NOR gate is supplied with the second clock. A second signal having a falling edge synchronized with the second signal, and the edge detection circuit rises in synchronization with the falling edge of the first signal as the pulse, and the rising edge of the second signal A pulse that falls in synchronization with the falling edge is generated.

  According to the present invention, there is provided a pulse generation circuit in which the number of logic gates being driven is reduced to reduce power consumption, and the number of logic gates through which a clock passes is reduced to shorten the clock delay.

It is a block diagram which shows the structural example of the pulse generation circuit of a present Example. (A) is a circuit diagram showing a configuration example of the pulse edge selection circuit of the first embodiment, (b) is a circuit diagram of a falling edge detection type flip-flop. (A) is a timing chart showing an example of driving of a master clock and a multi-phase clock in the DLL of FIG. 1, and (b) is a timing chart showing an example of driving in the pulse edge selection circuit of FIG. 2 (a). FIG. 6 is a circuit diagram illustrating a configuration example of a pulse edge selection circuit according to a second embodiment. 10 is a timing chart illustrating an example of driving in the pulse edge selection circuit according to the second exemplary embodiment. FIG. 10 is a circuit diagram illustrating a configuration example of a pulse edge selection circuit according to a third embodiment. (A) is a circuit diagram of a sample and hold circuit to which the pulse generation circuit of the present embodiment is applied, and (b) is a timing chart showing a driving example thereof. It is a block diagram which shows the structural example of the solid-state imaging device to which the pulse generation circuit of a present Example is applied.

  <Configuration Example of Pulse Generation Circuit of This Embodiment> FIG. 1 illustrates a plurality of delay locked loop circuits (hereinafter abbreviated as DLL) 11 for generating a multiphase clock and a plurality of pulse edge selection circuits of this embodiment. 1 is a block diagram of a pulse generation circuit 10 including the same. In the figure, the pulse generation circuit 10 includes a DLL 11 that is a clock generation circuit and four pulse edge selection circuits 100, 200, 300, and 400.

  The DLL 11 includes a voltage control delay line (Voltage Controlled Delay Line; hereinafter referred to as VCDL) 12 including a plurality of voltage control delay elements 20, a phase comparison circuit 13, and a charge pump 14. Further, 15 is a master clock line, 16 is a rising signal line, 17 is a falling signal line, 18 is a control voltage line, and 19 is a feedback clock line. In this embodiment, it is assumed that the master clock line 15 receives a 100 MHz clock. The DLL 11 supplies the four pulse edge selection circuits 100, 200, 300, and 400 with multiphase clocks whose phases are shifted at equal intervals to the clock lines (P0, P1, P2,..., P63). In this embodiment, the number of clock lines into which multi-phase clocks enter is 64 from P0 to P63, but the present invention is not limited to this number. The master clock through the master clock line 15 is supplied to the phase comparator 13 and the VCDL 12. The VCDL 12 includes 64 voltage control delay elements 20 that can change the delay amount of the clock according to the control voltage line 18. Each voltage control delay element 20 is connected to a clock line (P0, P1, P2,..., P63) as an output terminal.

  The output clock of the last voltage controlled delay element 20 of the VCDL 12 is supplied to the phase comparator 13 through the feedback clock line 19. The phase comparator 13 is connected to a master clock line 15 and a feedback clock line 19 as input terminals. The phase comparator 13 outputs, to the ascending signal line 16 and the descending signal line 17, a pulse in which the phase of the master clock delayed by one cycle of the master clock line 15 and the feedback clock of the feedback clock line 19 are exactly the same. For example, if the clock rise of the feedback clock line 19 is earlier than the clock rise delayed by one cycle of the master clock line 15, the fall signal pulse is output to the fall signal line 17. If the rising edge of the feedback clock is delayed with respect to the rising edge of the master clock delayed by one cycle, the rising signal pulse is output to the charge pump 14 on the rising signal line 16. If the clock rise time of the master clock delayed by one cycle and the clock rise of the feedback clock line 19 become simultaneous, the synchronization state is established. At this time, no pulse is output to the rising signal line 16 and the falling signal line 17, or the rising signal pulse and the falling signal pulse are the same pulse. The charge pump 14 increases the voltage value of the control voltage line 18 when a rising signal pulse is input to the rising signal line 16 and decreases the voltage value of the control voltage line 18 when a falling signal pulse is input to the falling signal line 17. .

  The four pulse edge selection circuits 100, 200, 300, and 400 are the same circuit, and are connected with clock lines (P0, P1, P2,..., P63) as input terminals, respectively. Also, rising position data for specifying the position of the rising position determination circuit and falling position data for specifying the position of the falling position determination circuit are input to each pulse edge selection circuit. Each pulse edge selection circuit includes rising position determination circuits 101, 201, 301, 401, falling position determination circuits 102, 202, 302, 402, and falling edge detection flip-flops 104, 204, 304, 404, respectively. Have. The rising position determination circuits 101, 201, 301, 401 include registers PU1 [5: 0] to PU4 [5: 0] (101a, 201a, 301a, 401a) that hold rising position data. On the other hand, the falling position determination circuits 102, 202, 302, and 402 include registers PD1 [5: 0] to PD4 [5: 0] (102a, 202a, 302a, and 402a) that hold falling position data. The rising position determination circuit is a first clock selection circuit, and its output is a first clock. The falling position determination circuit is a second clock selection circuit, and its output is a second clock. Details of embodiments relating to the pulse edge selection circuit are given below.

[Example 1]
<Configuration Example of Pulse Edge Selection Circuit of First Embodiment> FIG. 2A shows a circuit diagram of the first embodiment applied to the pulse edge selection circuit 100 of FIG. In the figure, 101 is a rising position determining circuit, 102 is a falling position determining circuit, 103 and 109 are NOR gate / decoder groups, 104 is a falling edge detection type flip-flop, and 105 is a multiphase clock line group. Reference numeral 106 denotes an NOR gate at the output stage of the rising position determination circuit 101, and 107 denotes an NOR gate at the output stage of the falling position determination circuit 102. Reference numerals 108 and 109 are selected NOR gate decoders, 110 and 120 are first-stage NAND switch groups, and 111 and 121 are second-stage NAND gate groups. The first embodiment is also applied to other pulse edge selection circuits 200, 300, and 400.

  In the pulse edge selection circuit according to the first embodiment, only one rising / falling clock is selected by the NAND switch groups 110 and 120 in the first stage. The clock sets / resets the falling edge detection flip-flop 104 via the second-stage NAND gate groups 111 and 121 and the NOR gates 106 and 107 as output gates to generate a desired pulse. Therefore, the logic gates being driven are eight logic gates of both position determination circuits and the falling edge detection type flip-flop, and the number of logic gates being driven is reduced to reduce power consumption. In addition, the number of logic gates through which the clock passes is three stages in the position determining circuit, and the falling edge detection type flip-flop changes the output Q without a prohibited state at the falling edge of the input terminal, so the number of logic gates through which the clock passes is reduced. To shorten the clock delay. Note that the input stage that passes the selected clock through the NAND switch groups 110 and 120 in the first stage and the output to the subsequent falling edge detection type flip-flop are the output stages.

  (Circuit Example of Falling Edge Detection Flip-Flop) FIG. 2B is a circuit diagram of the falling edge detection flip-flop 104 shown in FIG. As shown in the figure, the falling edge detection type flip-flop 104 includes a plurality of inverter gates 141 and a NAND gate 142. The falling edge detection type flip-flop 104 has no prohibited state in which the output Q voltage rises when the voltage at the input terminal SB falls and the output Q voltage falls when the voltage at the input terminal RB falls. (Unconditionally) is a circuit to be realized. As shown in FIG. 2A, the output wiring UN of the rising position determination circuit 101 is connected to the input terminal SB of the falling edge detection type flip-flop 104, and the falling position determination circuit 102 is connected to the input terminal RB. The output wiring DN is connected. The output wiring OUT of the pulse edge selection circuit 100 is connected to the output terminal Q of the falling edge detection type flip-flop 104. The falling edge detection type flip-flop is an edge detection circuit, the input terminal SB is a first input terminal, and the input terminal RB is a second input terminal.

  <Driving Timing Chart of DLL 11> FIG. 3A is a driving timing chart of clocks on the master clock line 15 and the clock lines (P0, P1, P2,..., P63) in the DLL 11 of FIG. The drive timing in the synchronous state of DLL11 is represented. 3A, the horizontal axis represents time, and the vertical axis represents the voltage values of the master clock line 15 and the clock lines (P0, P1, P2,..., P63). In this embodiment, since the frequency of the master clock is 100 MHz, the time difference from one voltage rise time t0 to the next voltage rise time t64 is 10 ns. Since the drive timing chart of FIG. 3A represents a synchronous state, the difference between the voltage rise time t0 of the master clock and the voltage rise time t1 of the clock line P0 via the voltage control delay element 20 is 0. 156 (= 10/64) ns. This time difference corresponds to the delay time of the voltage control delay element 20. Similarly, the difference between the voltage rise time t1 of the clock line P0 and the voltage rise time t2 of the clock line P1 is also 0.156 ns. Thus, the time difference between the voltage rise times of adjacent clock lines is 0.156 ns. That is, the phase shift between adjacent clock lines is 1/64 period. In the synchronized state, the time difference between the voltage rise time t0 of the master clock and the voltage rise time t64 of the clock line P63 is 10 ns. The time t64 is also the voltage rise time next to the voltage rise time t0 of the master clock line 15. A multi-phase clock having an equal interval formed as described above is transmitted from the DLL 11 in FIG. 1 through the clock lines (P0, P1, P2,..., P63) in FIG. Are output to the pulse edge selection circuits 100, 200, 300, 400.

  <Driving Timing Chart of Pulse Edge Selection Circuit 100> In the example of FIG. 2A of the first embodiment, the clock input to the clock line P0 is used to determine the rising position, and the clock input to the clock line P32 is decreased. Used for position determination. Therefore, the NOR gate / decoder 108 in the NOR gate / decoder group 103 is selected for determining the rising position. Similarly, the NOR gate / decoder 109 in the NOR gate / decoder group 113 is selected for determining the falling position. FIG. 3B shows a drive timing chart of each node in the pulse edge selection circuit 100 of FIG. In the figure, the horizontal axis represents time (seconds), and the vertical axis represents the voltage value of each wiring.

  (Rise Position Determination) First, the rise position determination circuit 101 selects a clock line P0 from 64 multiphase clock lines (P0, P1, P2,..., P63). For this purpose, the register value PU [5: 0] 101a in the pulse edge selection circuit 100 is set to “000000” in binary (= 0 in decimal notation) based on the input rising position data. Then, the NOR gate / decoder 108 is selected from the NOR gate / decoder group 103. That is, only the wiring NU0 among the 64 output wirings NU0, NU1, NU2,... NU63 of the NOR decoder group 103 is always high. Further, only the wiring NU7 is shown in the timing chart of FIG. 3B, but the 63 wirings NU1, NU2,... NU63 other than the wiring NU0 are always low. As a result, the clock is output only to the wiring SU0 among the 64 output wirings SU0, SU1, SU2,..., SU63 of the first-stage NAND gate group 110, and the other 63 wirings SU1, SU2,. .., SU63 are always high. That is, 64 types of clocks entered from the multiphase clock lines (P0, P1, P2,..., P63) are selected as one type by the first-stage NAND gate group 110 of the rising position determination circuit 101. Next, among the eight output wirings TU0, TU1, TU2,..., TU7 of the second-stage NAND gate group 111, the clock is output only to the wiring TU0, and the other seven wirings TU1, TU2,. ..., TU7 is always low. This is because the inputs of the second stage NAND gate group other than the NAND113 gate are always high. Eight wirings TU0, TU1, TU2,... TU7 are connected to the input terminal of the NOR gate 106 at the output stage of the rising position determination circuit 101. As a result, as shown in FIG. 3B, a signal obtained by inverting the clock of the wiring TU0 is output to the output wiring UN of the NOR gate 106. That is, a clock that falls simultaneously with the rise time of the clock line P0 (time t0 or t4 in FIG. 3B) is output to the output wiring UN of the rise position determination circuit 101.

  (Falling Position Determination) In the falling position determination circuit 102, the clock line P32 is selected from the multiphase clock lines (P0, P1, P2,..., P63). For this purpose, the register value PD [5: 0] 102a in the pulse edge selection circuit 100 is set to "100000" in binary (= 32 in decimal notation) based on the input falling position data. Then, the NOR gate / decoder 109 is selected from the NOR gate / decoder group 113. As a result, the rise time of the clock line P32 (time t1 in FIG. 3B) is connected to the output wiring DN of the fall position determination circuit 102 with the same number of stages and the same number of logic gates by the same movement as the rise position determination circuit 101. And a clock falling at the same time as t5).

  In general, the output clock of the NAND gate is delayed with a slow voltage fall, and the voltage rise of the output clock of the NOR gate is slow with a delay. For this reason, in the first embodiment, the dull falling side of the output clocks of the second-stage NAND gate groups 111 and 121 (time t2 in FIG. 4) is not used. Further, the dull rising side of the output clock of the NOR gates 106 and 107 in the output stage is not used. Further, the dull falling of the NAND gate and the dull rising of the NOR gate are worsened as the number of input terminals is increased. For this reason, generally, a NAND gate or a NOR gate that handles a clock uses three inputs or less. However, in the first embodiment, as shown in FIG. 5, since the falling of the NAND gate and the rising of the NOR gate are not used, a clock can be used with a NAND gate or NOR gate having four or more inputs. Actually, in the first embodiment, the 8-input NAND gate 112 and the 8-input NOR gates 106 and 107 are used as clocks. NAND gates and NOR gates are alternately connected. It is also possible to have more than 8 inputs.

  The drive timing chart of FIG. 3B will be described in time series. At time t0, the multiphase clock P0 rises from low to high, and the voltage of the wiring SU0 changes from high to low. Due to the low input of SU0 to the NAND gate 112, the potential of the wiring TU0 is changed from low to high. Due to the high input of TU0 to the NOR gate 106, the potential of the wiring UN falls from high to low. Then, the output OUT (Q) is changed from low to high by the operation of the falling edge detection type flip-flop 104. At time t1, NU0 is high, the multiphase clock P32 rises from low to high, and the voltage of the wiring SD32 changes from high to low. With the SD32 low input to the NAND gate 122, the potential of the wiring TD4 changes from low to high. The high input of TD4 to the NOR gate 107 causes the potential of the wiring DN to fall from high to low. Then, the output OUT (Q) changes from high to low by the operation of the falling edge detection type flip-flop 104. At time t2, the multiphase clock P0 falls from high to low, and the voltage of the wiring SU0 changes from low to high. At this time, the wiring TU0 changes from high to low, but since the wiring TU0 is an output of the 8-input NAND gate 112, the voltage becomes low as shown in FIG. For this reason, at the time t3 delayed from the time t2, the voltage of the wiring UN becomes high while being dull. This is because the wiring UN is the output of the 8-input NOR gate 106. As shown in these times t2 and t3, there is a time during which the voltage transition is slow, but this slowdown does not appear in the output OUT as shown in FIG. Further, time t4 performs the same operation as time t0, and time t5 performs the same operation as time t1.

  As shown in the timing chart of FIG. 3B, a pulse that rises at the falling time (t0 or t4) of the wiring UN and falls at the falling time (t1 or t5) of the wiring DN is applied to the wiring OUT. Is output. In the first embodiment, since the falling edge detection type flip-flop 104 is used, the rising edge of the voltage with a dull wiring UN or DN is not used. For this reason, even if the NOR gates 106 and 107 are used at the output stage of the clock, the dull rise does not matter. Further, a clock buffer may be connected to the outputs of the NOR gates 106 and 107 as necessary. However, this clock buffer must not invert the phase. In the first embodiment, it is assumed that 64 types of clocks having different phases are used at 100 MHz, so that a pulse having a time resolution of 0.156 (= 10/64) ns can be freely generated. And it does not vary with temperature, process, power supply voltage fluctuation, and power consumption is low. Actually, the pulse edge selection circuit of the first embodiment has a power consumption of 1/10 or less compared with the conventional one under the conditions of a power supply voltage of 1.8 V, a driving frequency of 100 MHz, and room temperature. Further, the pulse edge selection circuit according to the first embodiment reduces the number of gates passing from the clock input to the output, and can shorten the clock delay.

[Example 2]
<Configuration Example of Pulse Edge Selection Circuit According to Second Embodiment> FIG. 4 is a circuit diagram illustrating a pulse edge selection circuit according to a second embodiment. In the figure, 500 is a pulse edge selection circuit, 501 is a rising position determination circuit, 502 is a falling position determination circuit, 504 is a falling edge detection type flip-flop, and 505 is a multiphase clock line group. 510 and 520 are first-stage NAND gate groups, 515 and 525 are second-stage inverter groups, 516 and 526 are third-stage NOR gate groups, 517 and 527 are fourth-stage NAND gate groups, and 506. , 507 represent NOR gates in the output stage. As the falling edge detection type flip-flop 504, the same circuit as that described with reference to FIG. In the second embodiment, in order to generate a pulse of the output OUT of the pulse edge selection circuit 500, P6 is used as a clock for determining the rising time and P25 is used as a clock for determining the falling time from the multiphase clock line group 505.

  In the pulse edge selection circuit according to the second embodiment, only one rising / falling clock is selected by the NAND switch groups 510 and 520 in the first stage. The clock passes through the second-stage inverter groups 515 and 525, the third-stage NOR gate groups 516 and 526, the fourth-stage NAND gate groups 517 and 527, and the output-stage NOR gates 506 and 507. Then, the falling edge detection type flip-flop 104 is set / reset to generate a desired pulse. Therefore, the logic gates being driven are 10 logic gates (including inverters) and falling edge detection flip-flops of both position determination circuits, and the number of logic gates being driven is reduced to reduce power consumption. In addition, the number of logic gates through which the clock passes is five in the position determining circuit (including the inverter), and the falling edge detection type flip-flop changes the output Q without a prohibited state at the falling edge of the input terminal, so the clock passes through. The clock delay is shortened by reducing the number of logic gates.

  Since the DLL 11 is the same as that of the first embodiment, the description thereof is omitted. The pulse edge selection circuit 500 of the second embodiment can be used in the pulse edge selection circuits 100, 200, 300, and 400 of FIG.

  <Driving Timing Chart of Pulse Edge Selection Circuit 500> FIG. 5 is a timing chart in the pulse edge selection circuit of the second embodiment. In the figure, the horizontal axis represents time (seconds), and the vertical axis represents the voltage value of each wiring.

  (Rising Position Determination) First, the falling position determination circuit 101 selects a clock line P6 from 64 multiphase clock lines (P0, P1, P2,..., P63). For this purpose, the register value PU [5: 0] (not shown) in the pulse edge selection circuit 500 is set to “000110” in binary (= 6 in decimal notation) based on the input rising position data. Then, only the selected NAND gate 512 in the first-stage NAND gate group 510 passes the clock. The remaining NAND gates always output a high signal. That is, 64 types of clocks entered from the multiphase clock lines (P0, P1, P2,..., P63) are selected as one type in the first stage of the rising position determination circuit 501. Next, among the 64 output wirings SU1, SU2,..., SU63 of the second stage inverter group 515, a clock is output only to the wiring SU6, and a low signal is always output to the remaining wirings. . As a result, the clock is output only to the wiring TU1 among the 16 output wirings TU0, TU1,... TU15 of the third-stage NOR gate group 516, and the high signal is always output to the remaining wirings. . Next, among the four output wirings GU0, GU1,..., GU3 of the fourth-stage NAND gate group 517, a clock is output only to the wiring GU0, and a low signal is always output to the remaining three wirings. Is done. Four wirings GU0, GU1, GU2, and GU3 are connected to the input terminal of the NOR gate 506 in the output stage of the rising position determination circuit 501. As a result, as shown in FIG. 5, a signal obtained by inverting the clock of the wiring GU0 is output to the output wiring UN of the NOR gate 506. That is, a clock that falls simultaneously with the rise time of the clock line P0 (time t0, t3 in FIG. 5) is output to the output wiring UN of the rise position determination circuit 501.

  (Falling Position Determination) In the falling position determination circuit 502, the clock line P24 is selected from 64 multiphase clock lines (P0, P1, P2,..., P63). For this purpose, the register value PD [5: 0] (not shown) in the pulse edge selection circuit 500 is set to "011001" (= 24 in decimal number display) in the pulse edge selection circuit 500 based on the input falling position data. Then, the NAND gate 522 is selected from the first-stage NAND gate group 520. As a result, a clock that falls at the same time as the rising time of the clock line P24 (time t1, t4 in FIG. 5) is output to the output wiring DN of the falling position determining circuit 502 by the same movement as the rising position determining circuit 501.

  As shown in FIG. 4, the output wiring UN of the rising position determination circuit 501 is connected to the input SB of the falling edge detection type flip-flop 504, and the output wiring DN of the falling position determination circuit 502 is connected to the input RB. To do. Further, the output wiring OUT of the pulse edge selection circuit 500 is connected to the output Q of the falling edge detection type flip-flop 504. For this reason, as shown in the drive timing chart of FIG. 5, a pulse rising at the voltage falling time (t0, t3) of the wiring UN and falling at the voltage falling time (t1, t4) of the wiring DN is applied to the wiring OUT. Is output. Also in the second embodiment, since the falling edge detection type flip-flop 504 is used, the voltage rising in which the wiring UN or DN is dull is not used. Therefore, even if the NOR gates 506 and 507 are used in the output stage of the clock output, the dull rise does not matter. Further, a clock buffer may be connected to the outputs of the NOR gates 506 and 507 in the output stage as necessary. However, this clock buffer must not invert the phase.

  The drive timing chart of FIG. 5 will be described according to time series. At time t0, the multiphase clock P6 rises from low to high, the output of the selected NAND 512 is changed from high to low, and the voltage of the wiring SU6 is changed from low to high by the inverter. When the wiring SU6 changes from low to high, the potential of the wiring TU1 changes from high to low. The wiring TU1 changes from high to low, the potential of the wiring GU0 changes from low to high, and the potential of the wiring UN falls from high to low. Then, the output OUT (Q) is changed from low to high by the operation of the falling edge detection type flip-flop 504. At time t1, the multiphase clock P25 rises from low to high, the voltage of the wiring SD25 changes from low to high, the potential of the wiring TD6 changes from high to low, the potential of the wiring GD1 changes from low to high, and the wiring DN The potential falls from high to low. Then, the output OUT (Q) is changed from high to low by the operation of the falling edge detection type flip-flop 504. At time t2, the multiphase clock P6 falls from high to low, and the voltage of the wiring SU6 changes from high to low. At this time, the wiring TU1 changes from low to high, but the wiring TU1 is the output of the 4-input NOR gate, so that the voltage becomes high as shown in the drawing. Further, although the wiring GU0 changes from high to low, the voltage goes low while being dull because of the output of the 4-input NAND gate. Further, since the wiring UN is the output of the four-input NOR gate 506, the potential goes from low to high while dull. At time t2, there is a time when the voltage transition is slow, but as shown in FIG. 5, no bluntness appears at the output OUT. Further, time t3 performs the same operation as time t0, and time t4 performs the same operation as time t1. In the second embodiment, the number of gates passing from the clock input to the output of the pulse edge selection circuit 500 is reduced, the clock delay can be shortened, and the number of logic gates to be driven is reduced, so that the power consumption is also small.

[Example 3]
<Configuration Example of Pulse Edge Selection Circuit According to Third Embodiment> FIG. 6 is a circuit diagram illustrating a pulse edge selection circuit 600 according to a third embodiment. In the figure, 601 is a rising position determining circuit, 602 is a falling position determining circuit, 604 is a rising edge detection type flip-flop, and 606 and 607 are NAND gates in the output stage. The output wiring UN of the NAND gate 506 is connected to the S input terminal of the rising edge detection type flip-flop 604, and the output wiring DN of the NAND gate 507 is connected to the R input terminal. Further, the OUT output wiring of the pulse edge selection circuit 600 is connected to the Q output terminal. In the third embodiment, NAND gates 506 and 507 are used as output stage outputs of the rising position determining circuit 601 and the falling position determining circuit 602 to output clocks to the output wirings UN and DN. Although not shown, the phase of this clock is determined by the same method as in the first and second embodiments. Since the clocks of the wirings UN and DN are output from the NAND gates 506 and 507, the voltage falls slowly. For this reason, the falling edge using the rising edge detection type flip-flop 604 is not used. The circuit configuration of the rising edge detection type flip-flop 604 can be conceived from the configuration of the falling edge detection type flip-flop 104 shown in FIG.

  <Example of Sample and Hold Circuit Using Pulse Generation Circuit to which Pulse Edge Selection Circuit of This Embodiment is Applied> FIG. 7 shows a sample and hold circuit using a pulse generation circuit to which the pulse edge selection circuit of this embodiment is applied as a pulse generation circuit. Is applied. 7A is a circuit diagram of a sample hold circuit used in the analog / digital conversion circuit, and FIG. 7B is a drive timing chart. In the circuit diagram of FIG. 7A, 701 represents an operational amplifier, Vin represents an analog input voltage, Vout represents an operational amplifier output voltage, Cs represents a sampling capacitor, and S1, S2 and S3 represent switches. A represents a wiring connecting the switches S1 and S2 and the capacitor Cs, and B represents a wiring connecting the capacitor Cs, the inverting input terminal (− terminal) of the operational amplifier 701, and the switch S1. This circuit is an integrated sample hold and comparator. On / off of the switches S1, S2, and S3 of this circuit is controlled by a pulse with a rising / falling accurate generated by the pulse generation circuit 10 to which the pulse edge selection circuit of this embodiment is applied.

  The operation of the circuit diagram of FIG. 7A will be described using the drive timing chart of FIG. First, at time t0, the switches S1 and S2 are turned on. At this time, since the switch S1 is on, the operational amplifier 701 is in a virtual short state, so that the non-inverting input terminal (+ terminal) and the inverting input terminal (−terminal = wiring B) of the operational amplifier 701 have the same potential. On the other hand, since S2 is turned on, the voltage of the wiring A is the analog input voltage Vin. Next, at time t1, the switch S1 is turned off, and the connection between the output terminal of the operational amplifier 701 and the inverting input terminal (−terminal = wiring B) is disconnected. At time t2, the switch S2 is turned off and the switch S3 is turned on. Then, since the input voltage applied to the capacitor Cs is held, a potential difference of −Vin is generated between the − terminal and the + terminal of the operational amplifier 701. At this time, the operational amplifier 701 functions as a comparator, and outputs a logic value of high or low according to the sign of Vin. In the timing chart of FIG. 7B, the times t0 to t2 are referred to as sample times, and the times after time t2 are referred to as hold times. In this sample time, the switch S1 is turned off slightly earlier than the switch S2. This is because the impedance of the wiring B when the switch S2 is turned off is increased by turning off the switch S1 early. As a result, the charge under the gate of the switch S2 does not flow out to the capacitor Cs, and a sample hold circuit with a small offset can be formed. As in time, the pulse generation circuit 10 provided with the pulse edge selection circuit of this embodiment is used to form the timings of the switches S1, S2, and S3. In particular, it is effective to turn off the switch S1 slightly earlier than the switch S2. This sample and hold circuit has no variation due to temperature, process, and power supply voltage fluctuations, and consumes less power.

  <Example of Solid-State Imaging Device Using Pulse Generation Circuit to which Pulse Edge Selection Circuit of This Embodiment is Applied> The pulse edge selection circuit of this embodiment can also be applied to a solid-state imaging device. FIG. 8 is a block diagram when a pulse generation circuit to which the pulse edge selection circuit of this embodiment is applied is used in a solid-state imaging device. In the figure, reference numeral 800 denotes a solid-state imaging device that captures an image and generates pixel data. Reference numeral 850 denotes a pixel unit that stores pixel data in units of pixels. Reference numeral 851 denotes a readout circuit for reading out pixel data from the pixel portion 850 in parallel. Reference numeral 852 denotes a horizontal shift register that scans parallel pixel data read by the readout circuit 851 and performs parallel / serial conversion to output the data in series. Reference numeral 853 denotes a read signal, and reference numerals 854 and 855 denote non-overlap pulses output from the pulse edge selection circuit. The same reference numerals as those described above represent the same reference numerals as before. In the solid-state imaging device 800, the pixel unit 850 includes many pixels in a two-dimensional manner. For example, the pixel unit 850 includes 5000 pixels in the column direction and 3000 rows in the row direction, and includes a total of 15 million pixels. A signal photoelectrically converted by the pixel portion 850 is read by the reading circuit 851. Then, the signals are read out from the solid-state imaging device 800 by the horizontal shift register 852 as read signals 853 in order from the right. The read signal 853 may be either an analog signal or a digital signal. The horizontal shift register 852 is required to be driven at a large frequency due to the recent increase in the number of pixels. In order to generate 5000 columns of shift pulses, two non-overlapping pulses having mutually inverted phases are input to the horizontal shift register 852. A pulse generation circuit 10 to which the pulse edge selection circuit of this embodiment is applied is used to generate this non-overlap pulse. Then, the non-overlap pulse does not vary due to temperature, process, and power supply voltage fluctuations, and the solid-state imaging device 800 itself consumes less power. As a result, a highly reliable individual imaging device can be provided.

  In the pulse edge selection circuits according to the first to third embodiments, an example in which a gate element having 8 input terminals or a gate element having 4 input terminals is used in the output stage is shown. However, the examples of the first to third embodiments are merely examples, and the present invention can be achieved by appropriately combining a NAND gate having a plurality of input terminals and a NOR gate having a plurality of input terminals regardless of the number of input terminals. As shown, the rising edge and falling edge can be freely selected. That is, a pulse with a duty ratio of 20% can be easily produced. In addition, since the number of logic gates that are driven by a clock during driving can be reduced, power consumption can be reduced.

Claims (10)

A pulse generation circuit for generating a pulse,
A rising edge position selection circuit having a first NOR gate and a plurality of first NAND gates;
A falling edge position selection circuit having a second NOR gate and a plurality of second NAND gates;
An edge detection circuit,
In the rising edge position selection circuit,
Each output of the plurality of first NAND gates is connected to the first NOR gate;
Each of the plurality of first NAND gates is connected to at least a wiring for supplying any of a plurality of clocks having different phases.
A first clock selected to determine the position of the rising edge of the pulse from the plurality of clocks is supplied to one first NAND gate of the plurality of first NAND gates;
The one first NAND gate supplies a signal having a rising edge synchronized with the first clock to the first NOR gate,
The first NOR gate outputs a first signal having a falling edge synchronized with the first clock;
In the falling edge position selection circuit,
Each output of the plurality of second NAND gates is connected to the second NOR gate;
Each of the plurality of second NAND gates is connected to at least a wiring for supplying any of the plurality of clocks,
A second clock selected from the plurality of clocks to determine a position of a falling edge of the pulse is supplied to one second NAND gate among the plurality of second NAND gates. ,
The one second NAND gate supplies a signal having a rising edge synchronized with the second clock to the second NOR gate,
The second NOR gate outputs a second signal having a falling edge synchronized with the second clock;
Said edge detection circuit, as the pulse, to generate the first rising in synchronism with the falling edge of the signal, the second of said falling falling pulse in synchronization with the edge of the signal,
A pulse generation circuit characterized by the above. The edge detection circuit includes a falling edge detection type flip-flop having a first input terminal and a second input terminal, and an output of the first NOR gate of the rising position selection circuit is the first signal. As an input to the first input terminal, and an output of the second NOR gate of the falling position selection circuit is input to the second input terminal as the second signal.
The pulse generation circuit according to claim 1.   Each of the rising position selection circuit and the falling position selection circuit selects the first clock and the second clock from the plurality of clocks according to values set in the respective registers. The pulse generation circuit according to claim 1 or 2.   The first and second NOR gates are NOR gates having four or more inputs, and each of the first and second NAND gates is a NAND gate having four or more inputs. The pulse generation circuit according to any one of claims 1 to 3.   The first and second NOR gates are NOR gates having an input end of 8 inputs or more, and each of the first and second NAND gates is a NAND gate having an input end of 8 inputs or more. The pulse generation circuit according to any one of claims 1 to 3. The rising position selection circuit further includes a buffer circuit that buffers the output of the first NOR gate, and the falling position selection circuit further includes a buffer circuit that buffers the output of the second NOR gate,
The pulse generation circuit according to claim 1, wherein the pulse generation circuit is configured as described above.   The pulse generation circuit according to claim 1, further comprising a clock generation circuit that generates the plurality of clocks based on a master clock. A capacitor,
An operational amplifier circuit connected to the capacitor and outputting a voltage held in the capacitor;
A first switch for supplying and charging an input voltage to the capacitor;
A second switch provided in a feedback circuit of the operational amplifier circuit;
A third switch for grounding the input side of the capacitor;
A plurality of pulse generation circuits for generating a plurality of pulses for switching the first to third switches,
Each of the plurality of pulse generation circuits includes the pulse generation circuit according to any one of claims 1 to 7.
A sample-and-hold circuit. A pulse generation circuit for generating a pulse,
A rising edge position selection circuit having a first NAND gate and a plurality of first NOR gates;
A falling edge position selection circuit having a second NAND gate and a plurality of second NOR gates;
An edge detection circuit,
In the rising edge position selection circuit,
Each output of the plurality of first NOR gates is connected to the first NAND gate;
Each of the plurality of first NOR gates is connected to at least a wiring for supplying any one of a plurality of clocks having different phases.
A first clock selected to determine the position of the rising edge of the pulse from the plurality of clocks is supplied to one first NOR gate of the plurality of first NOR gates,
The one first NOR gate supplies a signal having a falling edge synchronized with the first clock to the first NAND gate,
The first NAND gate outputs a first signal having a rising edge synchronized with the first clock;
In the falling edge position selection circuit,
Each output of the plurality of second NOR gates is connected to the second NAND gate;
Each of the plurality of second NOR gates is connected to at least a wiring for supplying any of the plurality of clocks,
A second clock selected from the plurality of clocks to determine the position of the falling edge of the pulse is supplied to one second NOR gate of the plurality of second NOR gates. ,
The one second NOR gate supplies a signal having a falling edge synchronized with the second clock to the second NAND gate,
The second NAND gate outputs a second signal having a rising edge synchronized with the second clock,
Said edge detection circuit, as the pulse rises in synchronization with the rising edge of the first signal to generate said second of said synchronism with falling pulse to the rising edge of the signal,
A pulse generation circuit characterized by the above. A pixel unit for storing pixel data of the captured image;
A readout circuit for reading out pixel data from the pixel unit in parallel;
A shift register for parallel / serial conversion and outputting serially the pixel data read in parallel to the readout circuit;
A pulse generating circuit according to any one or claims 9 to claims 1 to 7 which is configured to provide a pulse for driving the shift register,
A solid-state imaging device comprising:

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