KR102022645B1 - Semiconductor integrated circuit and clock synchronization method - Google Patents

Semiconductor integrated circuit and clock synchronization method Download PDF

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KR102022645B1
KR102022645B1 KR1020130083322A KR20130083322A KR102022645B1 KR 102022645 B1 KR102022645 B1 KR 102022645B1 KR 1020130083322 A KR1020130083322 A KR 1020130083322A KR 20130083322 A KR20130083322 A KR 20130083322A KR 102022645 B1 KR102022645 B1 KR 102022645B1
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clock
output
signal
phase
delay
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KR20150009181A (en
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김수원
정찬희
이범수
권대한
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에스케이하이닉스 주식회사
고려대학교 산학협력단
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • G—PHYSICS
    • G04—HOROLOGY
    • G04F—TIME-INTERVAL MEASURING
    • G04F10/00—Apparatus for measuring unknown time intervals by electric means
    • G04F10/005—Time-to-digital converters [TDC]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/03—Astable circuits
    • H03K3/0315—Ring oscillators
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0818—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter comprising coarse and fine delay or phase-shifting means

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  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Nonlinear Science (AREA)
  • Pulse Circuits (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

According to the present invention, a semiconductor integrated circuit capable of reducing skew between a plurality of clocks having heterogeneous power supply voltages applied to a plurality of semiconductor chips, and minimizing an area of a clock synchronization circuit by implementing coarse synchronization using an oscillation signal. And a clock synchronization method.
A semiconductor system according to the present invention comprises: a first semiconductor chip driven according to a first output clock that transitions from a voltage of a first level to a voltage of a second level; A second semiconductor chip driven according to a second output clock that transitions from the third level voltage to the fourth level voltage; And a clock synchronizer which receives the first output clock and the second output clock, and outputs the phase of the first output clock in synchronization with the phase of the second output clock, wherein the clock synchronizer uses an oscillation signal. Synchronization can be implemented.

Figure R1020130083322

Description

Semiconductor Integrated Circuits and Clock Synchronization Methods {SEMICONDUCTOR INTEGRATED CIRCUIT AND CLOCK SYNCHRONIZATION METHOD}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock synchronization technique for semiconductor integrated circuits, and more particularly, to a technique useful for applying to DVFS control in a system LSI, a microprocessor, and even a data processing system for portable devices.

In order to reduce the power consumption of the semiconductor integrated circuit, it is effective to lower the power supply voltage. This is because the power consumption of the transistors constituting the semiconductor decreases in proportion to the square of the power supply voltage. In addition, the switching operating frequency of this transistor has a relation that is approximately proportional to the power supply voltage. Therefore, when the operating frequency of the logic circuit does not have to be high, it is effective to lower the power supply voltage and at the same time to reduce the operating frequency for lowering the power of the semiconductor integrated circuit. This is known as Dynamic Voltage Frequency Scaling.

As such, DVFS control technology is a valid concept for lowering power, but various challenges must be solved in order to mount this technology on a chip. Among them, the first clock applied to the first semiconductor chip transitions from the voltage of the first level to the voltage of the second level, and the second clock applied to the second semiconductor chip is the fourth level at the voltage of the third level. In the case of the transition to the voltage of, since the voltage level of the clock applied to each semiconductor chip is different from each other, the time when the first clock transitions from the first level to the second level, and the second clock is the fourth level from the third level Since the transition time to each other is different, the time required for detecting data in the first clock transitioning to the second level and the second clock transitioning to the fourth level is shortened.

That is, the data of the first clock and the second clock should be read while the level transition of the first clock and the second clock is completed, but the first clock and the second clock are shifted to different levels. When the level transition is completed, the timing shifts are different. Therefore, data must be read in accordance with the clock at which the level transition is completed later. However, when the phase of the first clock and the phase of the second clock are not synchronized, the time for reading data becomes shorter.

Thus, by synchronizing the phase of the first clock and the phase of the second clock to eliminate clock skew between the first and second clocks applied to the first and second chips, sufficient data can be read from each clock. It is necessary to secure time.

Japanese Patent Laid-Open No. 2010-118746 (published May 27, 2010)

According to the present invention, a semiconductor integrated circuit and a clock synchronization method capable of reducing skew between a plurality of clocks having different power supply voltages applied to a plurality of semiconductor chips are provided.

In addition, the present invention provides a semiconductor integrated circuit and a clock synchronization method capable of minimizing the area of a clock synchronization circuit by implementing coarse synchronization using an oscillation signal.

A semiconductor system according to the present invention comprises: a first semiconductor chip driven according to a first output clock that transitions from a voltage of a first level to a voltage of a second level; A second semiconductor chip driven according to a second output clock that transitions from the third level voltage to the fourth level voltage; And a clock synchronizer which receives the first output clock and the second output clock, and outputs the phase of the first output clock in synchronization with the phase of the second output clock, wherein the clock synchronizer uses an oscillation signal. Synchronization can be implemented.

According to an aspect of the present invention, a clock synchronizer may include: a replicator delay unit configured to output a replica clock by delaying a second input clock corresponding to the second output clock by one unit delay time than one clock time; Receiving a first input clock corresponding to the first output clock and the replica clock, and using a logical combination of a rising edge or a falling edge of the first input clock and the replica clock, a first coarse clock corresponding to the replica clock; A first coarse delay unit for generating a delay signal; A second coarse delay corresponding to the second input clock by receiving the first input clock and the second input clock and using a logical combination of a rising edge or a falling edge of the first input clock and the second input clock; A second coarse delay unit for outputting a signal; An interpolation control signal generator configured to generate an interpolation control signal by comparing one of the first coarse delay signal and the second coarse delay signal with a phase of the first input clock; And a linear interpolation unit configured to output an internal output signal linearly interpolating the first coarse delay signal and the second coarse delay signal using the interpolation control signal.

In addition, according to an aspect of the present invention, an interpolation control signal generation unit includes two stages for outputting a phase difference signal by comparing one of the first coarse delay signal and the second coarse delay signal with a phase of the first input clock. A time-digital converter; And an interpolation controller configured to convert the phase difference signal into an interpolation control signal of a thermometer code and output the converted signal.

In addition, the semiconductor system according to another aspect of the present invention, the first between the terminal of the first input clock input to the coarse delay unit and the terminal of the first coarse delay signal output from the first coarse delay unit; A first switch connected in parallel with the coarse delay unit; A second switch connected in parallel with the second coarse delay unit between a terminal of the second input clock input to the second coarse delay unit and a terminal of the second coarse delay signal output from the second coarse delay unit; And comparing the phases of the first input clock and the second input clock and switching the first switch and the second switch when the phase difference between the first input clock and the second input clock is within a predetermined setting value. A phase comparator may be further included.

According to another aspect of the present invention, the second coarse delay unit includes: a control clock generator for outputting a control clock for oscillation according to a level transition between the first input clock and the second input clock; A controllable oscillator for intermittently generating an oscillation signal having a predetermined oscillation frequency in response to an oscillation control clock output from the control clock generator; An edge detector which receives the first input clock and the second input clock and detects an edge of a clock that is out of phase among the first input clock and the second input clock and outputs an oscillation output control signal; A third switch controlled by the oscillation output control signal to pass an oscillation signal output from the controllable oscillator; And a second coarse delay signal transitioning to a first level in response to a first rising edge of the oscillation signal passing through the third switch, and transitioning to a second level in response to a reset signal corresponding to the second input clock. It may include an edge coupling portion for outputting.

In addition, the linear interpolation unit according to another aspect of the present invention, the first inverter group connected in parallel to the interpolation control signal is switched, and receives the first coarse delay signal and inverts the power supply voltage level; A second inverter group connected in parallel to the interpolation control signal and receiving a second coarse delay signal and inverting and outputting a ground voltage level; And an inverter configured to invert the output of the first inverter group and the output of the second inverter group in parallel.

Further, according to another aspect of the present invention, a clock synchronizer, during one operation, uses a phase detection signal corresponding to a phase difference between the first output clock and the second output clock to supply the first output clock. A coarse delay block for correcting a phase of a corresponding first input clock within a predetermined first set value; And a fine delay block comparing the phase of the first output clock with the phase of the second output clock to correct the phase of the coarse delay signal output from the coarse delay block within a second predetermined value.

Further, according to another aspect of the present invention, the coarse delay block detects a phase difference between the phase of the first output clock and the second output clock and periodically outputs a phase detection signal corresponding to the phase difference. A rough phase detector; A single actuating unit configured to generate a single enable signal using the phase detection signal; A ring oscillator for outputting an oscillation signal in response to the one-time enable signal; A counter for counting and outputting a length of the oscillation signal; And a coarse delay line delaying the first input clock in response to an output of the counter and outputting a coarse delay signal.

Further, according to another aspect of the present invention, the one-time actuating unit may include a logic circuit for outputting a one-time enable signal by logically combining the phase detection signal and the power supply voltage.

Further, according to another aspect of the present invention, the one-time enable signal means a phase difference between the first output clock and the second output clock.

Further, according to another aspect of the present invention, the ring oscillator can be implemented using a bias voltage.

Further, according to another aspect of the present invention, the counter counts the number of rising edges from the rising edge of the oscillation signal output from the ring oscillator to the moment when the one-time enable signal is disabled and outputs the digital clock as a digital clock. Can be.

Further, according to another aspect of the present invention, a coarse delay line includes: a decoder for decoding a digital clock output from the counter; A plurality of unit delay cells connected in series for delaying the first input clock corresponding to the decoding value output from the decoder; And a multiplexer controlled by the digital clock output from the counter to select any one of outputs of the plurality of unit delay cells.

Further, according to another aspect of the present invention, the delay time of the unit delay cell is equal to one period of the clock frequency generated by the ring oscillator.

According to still another aspect of the present invention, a fine delay block may include: a variable divider which increases the frequency divided by a higher frequency of the second input clock; A fine phase detector for comparing a phase of the first output clock and the second output clock to output a phase difference detection signal; A fine phase controller for varying an operating frequency corresponding to the frequency division and outputting a phase control signal in response to the phase difference detection signal; And a fine delay line controlled by the phase control signal to compensate for the phase of the coarse delay signal.

Further, according to another aspect of the present invention, the fine delay line includes a serially connected delay cell having different delay magnitudes and delays the input coarse delay signal to different delay magnitudes according to the phase control signal. Real delay line; And a dummy delay line arranged in parallel with the same structure as the real delay line and passing the second input clock as it is.

According to the present invention, skew between a plurality of clocks having heterogeneous power supply voltages applied to a plurality of semiconductor chips can be reduced, and the area of the clock synchronization circuit can be minimized by implementing coarse synchronization using the oscillation signal.

1 is an overall block diagram of a semiconductor integrated circuit according to an embodiment of the present invention;
2 is an open loop clock synchronization circuit diagram according to an embodiment of the present invention;
3 is an open loop clock synchronization timing diagram according to an embodiment of the present invention;
4 is a rough delay circuit diagram of an open loop type clock synchronization circuit according to an embodiment of the present invention;
5 is a rough delay timing diagram in an open loop clock synchronization circuit according to an embodiment of the present invention;
6 is a circuit diagram of a linear interpolator in an open loop type clock synchronization circuit according to an embodiment of the present invention;
7 is a hybrid clock synchronization circuit according to another embodiment of the present invention;
8A is an operational waveform diagram of a coarse block according to another embodiment of the present invention;
8B is an operation waveform diagram of a fine block according to another embodiment of the present invention;
9 is a detailed circuit diagram of the phase detection unit 710 and the one-time operation unit 720 according to another embodiment of the present invention;
10 is a detailed circuit diagram of a ring oscillator 730 according to another embodiment of the present invention;
11 is a detailed circuit diagram of a coarse delay line 750 according to another embodiment of the present invention;
12A is a detailed circuit diagram of a phase difference controller 780 according to another embodiment of the present invention;
12B is a detailed circuit diagram of a SAR controller according to another embodiment of the present invention, and
13 is a detailed circuit diagram of a fine delay line according to another exemplary embodiment of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Prior to this, terms or words used in the specification and claims should not be construed as having a conventional or dictionary meaning, and the inventors should properly explain the concept of terms in order to best explain their own invention. Based on the principle that can be defined, it should be interpreted as meaning and concept corresponding to the technical idea of the present invention. Therefore, the embodiments described in the specification and the configuration shown in the drawings are only the most preferred embodiments of the present invention and do not represent all of the technical idea of the present invention, various modifications that can be replaced at the time of the present application It should be understood that there may be equivalents and variations.

FIG. 1 is a block diagram of a semiconductor integrated circuit according to an embodiment of the present invention, and includes a clock synchronizer 110, a first semiconductor chip 120, and a second semiconductor chip 130.

The clock synchronizer 110 receives the first output clock CKout1 and the second output clock CKout2 and sets the phase of the first output clock CKout1 applied to the first semiconductor chip 120 to the second semiconductor chip. The output is performed in synchronization with the phase of the second output clock CKout2 applied to the 130.

The first semiconductor chip 120 is driven according to the first output clock CKout1 that transitions from the voltage of the first level to the voltage of the second level.

The second semiconductor chip 130 is driven according to the second output clock CKout2 that transitions from the third level voltage to the fourth level voltage.

2 is an open loop clock synchronization circuit diagram according to an embodiment of the present invention, and FIG. 3 is an open loop clock synchronization timing diagram according to an embodiment of the present invention.

The open loop type clock synchronization circuit according to an exemplary embodiment of the present invention may include a replicator delay unit 210, a first rough delay unit 220, a second rough delay unit 230, a first switch 240, and a first switch unit 240. And a second switch 250, a two-stage time-to-digital converter 260, an interpolation controller 270, and a linear interpolator 280.

The replicator delay unit 210 outputs the duplicated clock CKrpl by delaying the input second input clock CKin2 by a time smaller than one clock time Tck by one unit delay time.

The first coarse delay unit 220 receives the first input clock CKin1 and the replica clock CKrpl, and uses a logical combination of a rising edge or a falling edge of the two clocks to replicate the clock. The first coarse delay signal OCDU1 corresponding to CKrpl is output.

The second coarse delay unit 230 has the same structure as the first coarse delay unit 220, and receives the first input clock CKin1 and the second input clock CKin2, so that the rising edge or the falling edge of the two clocks is input. The second coarse delay signal OCDU2 corresponding to the second input clock CKin2 is output using the logical combination.

The first switch 240 and the second switch 250 are turned on when the phase difference between the first input clock CKin1 and the second input clock CKin2 is within a predetermined set value. That is, when the phase difference between the first input clock CKin1 and the second input clock CKin2 is within a predetermined setting value, the first input clock CKin1 and the second input clock CKin2 are respectively provided with a first coarse delay unit ( 220 and the second coarse delay unit 230 are bypassed.

Here, the set value may be determined according to the size of the linear interpolator 280 to correct the phase between the two clocks. For example, although not shown, the apparatus may further include a phase comparator configured to compare phases of the first input clock CKin1 and the second input clock CKin2, and the phase comparator may further include a first input clock CKin1 and a second input. When the phase difference of the clock CKin2 is within 1 ns (= TCKin1-TCKin2 or TCKin2-TCKin1), a switching signal is output to turn on the first switch 240 and the second switch 250.

The two-stage time-to-digital converter 260 compares the phase of any one of the first coarse delay signal OCDU1 and the second coarse delay signal OCDU2 with the first input clock CKin1 and bins the phase difference. Output as a phase difference signal in binary code.

The interpolation controller 270 converts a phase difference signal of a binary code into an interpolation control signal of a thermometer code and outputs the converted signal.

The linear interpolator 280 outputs an internal output signal OUTint of linearly interpolating the first coarse delay signal OCDU1 and the second coarse delay signal OCDU2 using the interpolation control signal.

4 is a rough delay circuit diagram of an open loop type clock synchronization circuit according to an exemplary embodiment of the present invention, and FIG. 5 is a rough delay timing diagram of an open loop type clock synchronization circuit according to an exemplary embodiment of the present invention.

The coarse delay in the open loop clock synchronization circuit according to an embodiment of the present invention may include a control clock generator 410, a controllable oscillator 420, an edge detector 430, a third switch 440, and an edge combiner ( 450).

The control clock generator 410 transitions from the "L" state to the "H" state when the first input clock CKin1 transitions to the "H" level and the second input clock CKin2 transitions to the "L" level. When the first input clock CKin1 transitions to the "L" level and the second input clock CKin2 transitions to the "H" level, an oscillation control clock that generates a transition from the "H" state to the "L" state is generated and output. The control clock generator 410 according to an embodiment of the present invention may be any one or a combination of RS F / F, D F / F, T F / F, and JK F / F.

The controllable oscillator 420 intermittently generates the oscillation signal OUTosc having a predetermined oscillation frequency in response to the oscillation control clock output from the control clock generator 410. Specifically, the oscillation signal is generated in response to the oscillation control clock transitioning to the "H" state, and the last rising edge of the oscillation signal OUTosc is generated in response to the oscillation control clock transitioning to the "L" state.

The edge detector 430 receives the first input clock CKin1 and the second input clock CKin2 and detects an edge of a clock that is out of phase among the first input clock CKin1 and the second input clock CKin2. Output the steady state oscillation output control signal CTRL. That is, the edge detector 430 outputs the oscillation output control signal CTRL in the monostable state to the rising edge and the falling edge of the clock out of phase among the first input clock CKin1 and the second input clock CKin2, respectively. Capture the pulse. The edge detector 430 resets the edge combiner 450 using a reset signal Reset generated in response to a falling edge of the second input clock CKin2.

The third switch 440 is switched to the oscillation output control signal CTRL output from the edge detector 430 and is output from the controllable oscillator 420 while the oscillation output control signal CTRL is in the "H" state. Pass the oscillation signal OUTosc.

The edge combiner 450 transitions to the "H" state in response to the first rising edge of the oscillation signal INcpt passing through the third switch 440, and "L" in response to the falling edge of the second input clock CKin2. Output a second coarse delay signal OCDU2 that transitions to " state. &Quot;

FIG. 6 is a circuit diagram of a linear interpolator in an open loop type clock synchronization circuit according to an exemplary embodiment of the present invention, wherein the linear interpolator 280 uses a first coarse delay signal OCDU1 and a second coarse delay using an interpolation control signal. The internal output signal OUTint from which the signal OCDU2 is linearly interpolated is output.

The linear interpolator 280 is switched to the interpolation control signals T0, T1,..., And T15, and receives a first coarse delay signal OCDU1 to invert and output the power voltage level. (611, 612, ..., 626), the interpolation control signal (T0, T1, ..., T15) is switched, and receives the second rough delay signal (OCDU2) in parallel to invert the ground voltage level and output Connected second inverter groups 631, 632, ..., 646, outputs of the first inverter groups 611, 612, ..., 626 and second inverter groups 631, 632, ..., 646 Inverter 650 for inverting the output of the parallel connection.

For example, as shown in FIG. 3, when interpolating the first coarse delay signal OCDU1 and the second coarse delay signal OCDU2, 16 inverters are connected in parallel to each inverter group, and the first inverter group When six of the sixteen inverters in the turn-on, ten of the sixteen inverters in the second inverter group are turned on. Accordingly, since the current of the second coarse delay signal OCDU2 flows more, the phase of the interpolated signal approaches the phase of the second coarse delay signal OCDU2.

Here, the switching operation of the inverter in each inverter group will be omitted because it is obvious to those skilled in the art (see Korean Patent Application No. 1993-21729).

7 is a hybrid clock synchronization circuit diagram according to another embodiment of the present invention, FIG. 8A is an operation waveform diagram of a coarse delay block according to another embodiment of the present invention, and FIG. 8B is a fine diagram according to another embodiment of the present invention. Operation waveform diagram of a delay block.

The hybrid clock synchronization circuit according to another embodiment of the present invention includes a coarse delay block and a fine delay block. The coarse delay block includes a coarse phase detector 710, a single acting unit 720, a ring oscillator 730, a counter 740, and a coarse delay line 750, and the fine delay block includes a variable divider 760. , A fine phase detector 770, a fine phase controller 780, and a fine delay line 790.

A rough delay block according to another embodiment of the present invention will be briefly described as follows. When the coarse phase detector 710 periodically outputs the phase detection signal, the one-time actuator 720 generates the one-time enable signal EN, and the ring oscillator 730 starts to operate to generate the oscillation signal CKosc. When the counter 740 counts the rising edge of the oscillation signal CKosc. And outputs the number of cycles of the oscillation signal CKosc., The coarse delay line 750 delays the first input clock CKin1. And output as a coarse delay signal (CKcoarse). As a result, the coarse block operates only for one cycle to reduce the phase difference of the first input clock CKin1 within the time 600ps corresponding to one period of the ring oscillator 730.

9 is a detailed circuit diagram of the coarse phase detection unit 710 and the one-time operation unit 720 according to another embodiment of the present invention.

The rough phase detector 710 detects a phase difference between the phase of the first output clock CKout1 and the second output clock CKout2 and periodically outputs the phase detection signal S1. The short acting unit 720 prevents the rough fixing operation from being repeated during the fine fixing after the rough fixing. To this end, the one-time operation unit 720 receives the output of the first inverter 721 for inverting the phase detection signal and the output of the first inverter 721 as a clock signal, and receives and outputs the power supply voltage as a data signal. 722), the second inverter 723 for inverting the output of the DF / F 722, and outputs a single enable signal EN that is only enabled once by multiplying the output of the phase detection signal and the second inverter 723 by one. And an end gate 724.

Specifically, when the rising edge of the first output clock CKout1 and the phase detection signal (S1) and the one-time enable signal (EN) transitions to the "H" state, after the rising edge of the second output clock (CKout2) 1 When the DF / F 711 outputs the reset signal Reset, the phase detection signal S1 and the one-time enable signal EN transition to the "L" state. When the phase detection signal S1 transitions from the "H" state to the "L" state, the output S2 of the second inverter 723 in the single-acting unit 720 transitions from the "H" state to the "L" state. do. Thereafter, even when the first output clock CKout1 and the second output clock CKout2 generate a rising edge, the output S2 of the inverter 723 in the single-acting operation 720 is still maintained in the "L" state, and thus the AND gate. 724 maintains a single enable signal EN in the " L " state. That is, the single-time enable signal EN in the "H" state means a phase difference between the first output clock CKout1 and the second output clock CKout2.

10 is a detailed circuit diagram of a ring oscillator 730 according to another embodiment of the present invention, wherein the ring oscillator 730 is a NAND gate that negatively multiplies a single enable signal EN and an output signal of the ring oscillator 730. 1010 and a plurality of serially connected inverters 1020,..., 10N0 for inverting the output of the NAND gate 1010 and outputting the oscillation clock signal CKosc.

The ring oscillator 730 implements a delay cell using a bias voltage so that even if the power supply voltage changes, the current Id flowing inside the inverter is constant so that the delay time Td of the individual delay cells does not change.

The counter 740 counts the number of rising edges from the rising edge of the oscillation signal CKosc. Output from the ring oscillator 730 to the moment when the single enable signal EN is disabled and outputs the digital clock. .

FIG. 11 is a detailed circuit diagram of a coarse delay line 750 according to another embodiment of the present invention, wherein the coarse delay line 750 is a first input clock CKin1 input corresponding to the number of clocks output from the counter 740. Delay to output as a coarse delay signal (CKcoarse). The coarse delay line 750 is a decoder 1110 for decoding the digital clock output from the counter and the input clock CKin input as much as the decoding value I [3: 0] output from the decoder 1110. A plurality of serially coupled unit delay cells 1111, 1112, ..., 111g for delaying, and a multiplexer 1130 controlled by a digital clock output from a counter to select any one of the outputs of the plurality of unit delay cells. . In addition, the individual unit delay cells include a plurality of serially connected inverters that invert and output the outputs of the NAND gate 1141 and the NAND gate 1141 that inversely logically multiplies the value inverting the decoding value and the clock CKdi input thereto. (1142, ..., 114N), and the AND gate 1150 for ANDing the decoding value and the clock CKdi input thereto. Here, the delay time of the unit delay cell is equal to one period of the frequency of the clock generated by the ring oscillator 730.

A fine delay block according to another embodiment of the present invention will be briefly described as follows.

The fine delay block uses the fine phase control unit 780 to change the phase difference for 600 cycles and then sequentially change the size of the fine delay line 790 to 320ps, 160ps, 80ps, 40ps, 20ps, and 10ps in the fine delay line 790. It can be reduced to less than 10ps.

For example, when the phase of the first output clock CKout1 advances by 340 ps before the phase of the second output clock CKout2 after the coarse delay block is operated, the fine phase controller 780 controls the fine delay line 790 to control the fine delay line 790. The phase of the first output clock CKout1 is delayed by 320ps to reduce the phase difference between the first output clock CKout1 and the second output clock CKout2 to 20ps. In this case, since the phase of the first output clock CKout1 is 20ps ahead of the phase of the second output clock CKout2, the fine phase detection unit 770 generates an "H" state signal, and the fine phase control unit 780 The fine delay line 790 is controlled to delay the phase of the first output clock CKout1 by 160 ps again. At this time, since the phase of the first output clock CKout1 is 140ps behind the phase of the second output clock CKout2, the fine phase detector 770 generates an "L" state signal. Then, in the next cycle, the above process is repeated by changing the 80ps delay size instead of the 160ps delay size. In this way, the 40ps, 20ps, and 10ps sizes can all be controlled, and the phase difference can be reduced to within 10ps.

The variable divider 760 changes the operating frequency of the fine phase controller 780 according to the frequency of the input clock. For example, if the frequency of the input clock exceeds 2.0 GHz, the input clock is divided into three, and if the frequency is 1 to 2 GHz, the input clock is divided into two. This is to prevent the occurrence of an error in which the fine clock control unit does not determine the phase control signal by the phase difference detection signal because the next clock is generated before the fine phase controller outputs the phase control signal when the frequency of the input clock is high.

The fine phase detector 770 compares the phase of the second output clock CKout2 with the phase of the first output clock CKout1 and outputs a phase difference detection signal of the "H" state signal or the "L" state signal.

12A is a detailed circuit diagram of the phase controller 780 according to another embodiment of the present invention, in which the fine phase controller 780 is a fine delay in the fine delay line 790 according to a sign output from the fine phase detector 770. Control the size of the. That is, the fine phase detector 770 shifts the phase of the first output clock CKout1 and the second output clock CKout2 to the "H" state at the rising edge of the output clock, and at the rising edge of the backward output clock. A phase detection signal that transitions to the L "state is periodically output.

The overall operation is as follows.

When the initial reset signal reset is applied, the plurality of serially connected SAR controllers 1210 and 1211 to 1216 output SAR control signals B [5: 0] of '000000'. When the reset signal resets to the "L" state, the first SAR control unit 1211 resets the enable signal to the initial value because the enable terminal is in the "L" state and the bit terminal is in the "L" state. When reset is applied to the shift terminal, the first SAR control signal B [5] output from the bit terminal transitions to the "H" state.

On the next consecutive rising edge of the second output clock CKout2, the value of the phase detection signal comp_out input to the comp terminal comp of the first SAR controller 1211 is transferred to the bit terminal bit. The phase detection signal comp_out at that time is a "H" state or "L" state signal determined by the phase difference between the first output clock CKout1 and the second output clock CKout2 that have passed through the fine delay line 790. .

When the first SAR control signal B [5] is determined by the phase detection signal comp_out, the second SAR control signal B [4] transitions to the " H " state.

Thereafter, by enabling the enable terminal of the first SAR control unit 1211 to the "H" state, the first SAR control signal B [5] becomes the comp terminal of the first SAR control unit 1211. The phase detection signal comp_out input to the signal is maintained, and the phase detection signal comp_out for acquiring the second SAR control signal B [4] is detected.

12B is a detailed circuit diagram of the SAR controller, and each SAR controller 1211,..., And 1216 includes a 3: 1 multiplexer 1240 and a D F / F 1250.

In addition, the 3: 1 multiplexer 1240 operates as shown in Table 1 below. When the enable terminal value is “H”, the value stored in the bit terminal is output. When the enable terminal value is "L" and the value stored in the bit terminal is "H", the comp terminal value is output and the comp terminal value is bit terminal. Are stored in. Finally, when the enable terminal value is in the "L" state and the value stored in the bit terminal is in the "L" state, a shift terminal value is output.

enable bit selection operation One X bit memorization 0 One comp data load 0 0 shift shift right

FIG. 13 is a detailed circuit diagram of a fine delay line according to another exemplary embodiment of the present invention. The fine delay line 790 includes a real delay line 1320 and a dummy delay line 1310.

The real delay line 1320 includes a plurality of delayed cells connected in series of 320 ps, 160 ps, 80 ps, 40 ps, 20 ps, 10 ps, and receives a coarse delay signal CKcoarse according to the phase control signal of the fine phase controller 780. Phases can be delayed in sizes of 320ps, 160ps, 80ps, 40ps, 20ps, and 10ps.

The dummy delay line 1310 is disposed in parallel with the same structure as the real delay line 1320, and passes the input second input clock CKin2 as it is.

Here, since the delay size of one inverter is 20 to 30 ps, the relative delay size is used by adding a dummy delay line 1310 to implement a delay of 10 ps. In addition, since the real delay line 1320 and the dummy delay line 1310 experience a change in the supply voltage at the same time, the fine delay line 790 using the dummy delay line 1310 has an advantage of being insensitive to the change in the supply voltage.

As described above, although the present invention has been described by way of limited embodiments and drawings, the present invention is not limited thereto and is intended by those skilled in the art to which the present invention pertains. Of course, various modifications and variations are possible within the scope of equivalents of the claims to be described.

210: replicator delay unit 220: first rough delay unit
230: second rough delay unit 240: first switch
250: second switch 260: two-stage time-to-digital converter
270: interpolation control unit 280: linear interpolation unit
710: coarse phase detector 720: ring oscillator
730: ring oscillator 740: counter
750: coarse delay line 760: variable dispensing part
770: fine phase detector 780: fine phase controller
790: fine delay line

Claims (16)

A first semiconductor chip driven according to a first output clock that transitions from the voltage of the first level to the voltage of the second level;
A second semiconductor chip driven according to a second output clock that transitions from the third level voltage to the fourth level voltage; And
A clock synchronizer which receives the first output clock and the second output clock and synchronizes a phase of the first output clock with a phase of the second output clock,
The clock synchronizer implements synchronization using an oscillation signal.
The method of claim 1, wherein the clock synchronizer,
A replicator delay unit configured to output a replica clock in which a second input clock corresponding to the second output clock is delayed by one unit delay time than one clock time;
Receiving a first input clock corresponding to the first output clock and the replica clock, and using a logical combination of a rising edge or a falling edge of the first input clock and the replica clock, a first coarse clock corresponding to the replica clock; A first coarse delay unit for generating a delay signal;
A second coarse delay corresponding to the second input clock by receiving the first input clock and the second input clock and using a logical combination of a rising edge or a falling edge of the first input clock and the second input clock; A second coarse delay unit for outputting a signal;
An interpolation control signal generator configured to generate an interpolation control signal by comparing one of the first coarse delay signal and the second coarse delay signal with a phase of the first input clock; And
A linear interpolator for outputting an internal output signal linearly interpolating the first coarse delay signal and the second coarse delay signal using the interpolation control signal
Semiconductor system comprising a.
The method of claim 2, wherein the interpolation control signal generation unit,
A two-time time-digital converter configured to output a phase difference signal by comparing one of the first rough delay signal and the second rough delay signal with a phase of the first input clock; And
An interpolation control unit for converting the phase difference signal into an interpolation control signal of a thermometer code and outputting
Semiconductor system comprising a.
The method of claim 2,
A first switch connected in parallel with the first coarse delay unit between a terminal of the first input clock input to the first coarse delay unit and a terminal of the first coarse delay signal output from the first coarse delay unit;
A second switch connected in parallel with the second coarse delay unit between a terminal of the second input clock input to the second coarse delay unit and a terminal of the second coarse delay signal output from the second coarse delay unit; And
Compares a phase of the first input clock and the second input clock and controls to switch the first switch and the second switch when a phase difference between the first input clock and the second input clock is within a predetermined setting value. Phase comparator
A semiconductor system further comprising.
The method of claim 2, wherein the second rough delay unit,
A control clock generator for outputting an oscillation control clock in response to a level transition between the first input clock and the second input clock;
A controllable oscillator for intermittently generating an oscillation signal having a predetermined oscillation frequency in response to the oscillation control clock output from the control clock generator;
An edge detector which receives the first input clock and the second input clock and detects an edge of a clock that is out of phase among the first input clock and the second input clock and outputs an oscillation output control signal;
A third switch controlled by the oscillation output control signal to pass an oscillation signal output from the controllable oscillator; And
Outputs a second coarse delay signal that transitions to a first level in response to a first rising edge of the oscillation signal passing through the third switch and transitions to a second level in response to a reset signal corresponding to the second input clock Edge joint
Semiconductor system comprising a.
The linear interpolation unit of claim 2,
A first inverter group connected in parallel to the interpolation control signal and receiving the first coarse delay signal and inverting and outputting a power supply voltage level;
A second inverter group connected in parallel to the interpolation control signal and receiving a second coarse delay signal and inverting and outputting a ground voltage level; And
An inverter that inverts the output of the first inverter group and the output of the second inverter group in parallel;
Semiconductor system comprising a.
The method of claim 1, wherein the clock synchronizer,
During one operation, the phase detection signal corresponding to the phase difference between the first output clock and the second output clock is used to correct the phase of the first input clock corresponding to the first output clock within a predetermined first set value. Coarse delay block; And
A fine delay block for comparing the phase of the first output clock with the phase of the second output clock to correct the phase of the coarse delay signal output from the coarse delay block within a second predetermined value;
Semiconductor system comprising a.
The method of claim 7, wherein the coarse delay block,
A rough phase detector for detecting a phase difference between the phase of the first output clock and the second output clock and periodically outputting a phase detection signal corresponding to the phase difference;
A single actuating unit configured to generate a single enable signal using the phase detection signal;
A ring oscillator for outputting an oscillation signal in response to the one-time enable signal;
A counter for counting and outputting a length of the oscillation signal; And
A coarse delay line delaying the first input clock in response to an output of the counter and outputting the coarse delay signal
Semiconductor system comprising a.
The method of claim 8, wherein the single actuating part,
A logic circuit for logically combining the phase detection signal and a power supply voltage to output a single enable signal
Semiconductor system comprising a.
The method of claim 9,
The one-time enable signal means a phase difference between the first output clock and the second output clock.
The method of claim 8,
The ring oscillator is implemented using a bias voltage.
The method of claim 8,
And the counter counts the number of rising edges from the rising edge of the oscillation signal output from the ring oscillator to the moment when the single enable signal is disabled and outputs a digital clock.
The method of claim 8, wherein the coarse delay line,
A decoder for decoding the digital clock output from the counter;
A plurality of unit delay cells connected in series for delaying the first input clock corresponding to the decoding value output from the decoder; And
A multiplexer controlled by a digital clock output from the counter to select any one of the outputs of the plurality of unit delay cells
Semiconductor system comprising a.
The method of claim 13,
And a delay time of the unit delay cell is equal to one period of a clock frequency generated by the ring oscillator.
The method of claim 7, wherein the fine delay block,
A variable divider which increases the frequency dividing as the frequency of the second input clock corresponding to the second output clock increases;
A fine phase detector for comparing a phase of the first output clock and the second output clock to output a phase difference detection signal;
A fine phase controller for varying an operating frequency corresponding to the frequency division and outputting a phase control signal in response to the phase difference detection signal; And
A fine delay line controlled by the phase control signal to compensate for the phase of the coarse delay signal
Semiconductor system comprising a.
The method of claim 15, wherein the fine delay line,
A real delay line including a plurality of delay cells connected in series having different delay magnitudes, and delaying the input coarse delay signal to different delay magnitudes according to the phase control signal; And
A dummy delay line arranged in parallel with the same structure as the real delay line and passing the second input clock as it is.
Semiconductor system comprising a.
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JP2000307420A (en) 1999-04-16 2000-11-02 Hitachi Ltd Phase adjustment circuit and optical interconnector system
JP2011507358A (en) 2007-12-14 2011-03-03 モサイド・テクノロジーズ・インコーポレーテッド Clock recovery and timing method in a system having multiple devices and a memory controller with flexible data alignment

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JP2000307420A (en) 1999-04-16 2000-11-02 Hitachi Ltd Phase adjustment circuit and optical interconnector system
JP2011507358A (en) 2007-12-14 2011-03-03 モサイド・テクノロジーズ・インコーポレーテッド Clock recovery and timing method in a system having multiple devices and a memory controller with flexible data alignment

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