DE19680271T1 - Variable delay circuit and time signal generation circuit - Google Patents

Variable delay circuit and time signal generation circuit

Info

Publication number
DE19680271T1
DE19680271T1 DE19680271T DE19680271T DE19680271T1 DE 19680271 T1 DE19680271 T1 DE 19680271T1 DE 19680271 T DE19680271 T DE 19680271T DE 19680271 T DE19680271 T DE 19680271T DE 19680271 T1 DE19680271 T1 DE 19680271T1
Authority
DE
Germany
Prior art keywords
signal generation
time signal
variable delay
circuit
generation circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
DE19680271T
Other languages
German (de)
Inventor
Toshiyuki Okayasu
Hideo Sakai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advantest Corp
Original Assignee
Advantest Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP10295595A external-priority patent/JP3183494B2/en
Application filed by Advantest Corp filed Critical Advantest Corp
Publication of DE19680271T1 publication Critical patent/DE19680271T1/en
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H03K5/134—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices with field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
DE19680271T 1995-04-04 1996-03-11 Variable delay circuit and time signal generation circuit Ceased DE19680271T1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP10295595A JP3183494B2 (en) 1994-06-02 1995-04-04 Timing signal generation circuit
PCT/JP1996/000598 WO1996031949A1 (en) 1995-04-04 1996-03-11 Variable delay circuit and timing signal generating circuit

Publications (1)

Publication Number Publication Date
DE19680271T1 true DE19680271T1 (en) 1997-06-05

Family

ID=14341230

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19680271T Ceased DE19680271T1 (en) 1995-04-04 1996-03-11 Variable delay circuit and time signal generation circuit

Country Status (3)

Country Link
KR (1) KR100199219B1 (en)
DE (1) DE19680271T1 (en)
WO (1) WO1996031949A1 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3729926A1 (en) * 1987-09-07 1989-03-23 Siemens Ag CMOS output stage

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5018347B1 (en) * 1969-04-09 1975-06-27
JPH07112146B2 (en) * 1983-10-14 1995-11-29 ソニー株式会社 Variable delay circuit
JPS6297421A (en) * 1986-08-12 1987-05-06 Nippon Gakki Seizo Kk Pulse fm detection circuit
JPH05268017A (en) * 1992-03-17 1993-10-15 Sanyo Electric Co Ltd Clock generator

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3729926A1 (en) * 1987-09-07 1989-03-23 Siemens Ag CMOS output stage

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
JP 2-2 02 114 A, in: Patents Abstr. of Japan, Sect. E, Vol. 14 (1992), Nr. 489 (E-994) *
JP 4-13 305 A, in: Patents Abstr. of Japan, Sect. E, Vol. 16 (1992), Nr. 166 (E-1193) *
JP 4-2 77 921 A, in: Patents Abstr. of Japan, Sect. E, Vol. 17 (1992), Nr. 75 (E-1320) *
JP 63-1 77 610 A, in: Patents Abstr. of Japan, Sect. E, Vol. 12 (1992), Nr. 449 (E-686) *

Also Published As

Publication number Publication date
KR100199219B1 (en) 1999-06-15
KR970702618A (en) 1997-05-13
WO1996031949A1 (en) 1996-10-10

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
8131 Rejection