JP3335820B2 - DA converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DA for converting a digital input signal into an analog output signal having a predetermined resolution in response to a digital input signal having a predetermined number of bits.
More particularly, the present invention relates to an R-2R DA converter to which CMOS is applied.

[0002]

2. Description of the Related Art FIG. 7 shows an example of an R-2R DA converter.
It is a structural circuit diagram of an example. The DA converter 40 in the illustrated example is
A DA converter that uses the voltage addition method,
Element R _Ten, R₁₁, R₁₂And the resistance element R₂₀, R_{twenty one}, R_{twenty two},
R_{twenty three}, R_{twenty four}And the switch circuit S ₀, S₁, S_Two, S
_ThreeAnd an operational amplifier OP. In addition,
Anti-element R_Ten, R₁₁, R₁₂Each have a resistance value R,
Anti-element R₂₀, R_{twenty one}, R_{twenty two}, R _{twenty three}, R_{twenty four}Is the resistance value
Has 2R.

In the DA converter 40 shown in the figure, selection input terminals of switch circuits S ₀ , S ₁ , S ₂ , and S ₃ are provided with:
Digital input signals D ₀ , D ₁ , D ₂ , D ₃ are input, respectively, and their output terminals are respectively connected to resistance elements R ₂₀ , R _21,.
Is connected to one terminal of R _22, R _23, its first input is connected to all the reference voltage V _R, the second input terminal is connected to all the ground.

[0004] One terminal of the resistance element R ₂₄ is connected to the ground. The other terminals of the resistance elements R ₂₄ and R ₂₀ are connected to one terminal of the resistance element R _10. Similarly, the other terminals of the resistance elements R ₁₀ and R ₂₁ are connected to one terminal of the resistance element R _11. The other terminals of the elements R ₁₁ and R ₂₂ are connected to the resistance element R ₁₂
, The other terminals of the resistance elements R ₁₂ and R ₂₃ are input to the + input terminal of the operational amplifier OP, the output terminal is input to the − input terminal of the operational amplifier OP, and the analog output signal is output from the output terminal thereof. Is output.

FIG. 8 is a circuit diagram showing an example of a switch circuit used in the above-described R-2R type DA converter. The switch circuit 42 in the illustrated example is an example of a switch circuit to which CMOS is applied, and similarly to an inverter including a P-type MOS transistor (hereinafter, referred to as PMOS) 44 and an N-type MOS transistor (hereinafter, referred to as NMOS) 46, It is composed of a PMOS 48 and an NMOS 50.

In the illustrated switch circuit 42, PM
The sources of the OS 44 and the NMOS 46 are connected to the power supply voltage V _DD and the ground, respectively. The gate (selection input terminal of the switch circuit) receives the digital input signal D _n , and the drain is short-circuited to the gate of the PMOS 48 and the NMOS 50. Has been entered. Similarly, PM
(First and second input terminal of the switch circuit) source OS48 and NMOS50 is connected to a reference voltage V _R and ground, respectively, the drain is the output terminal OUT are short-circuited.

In the DA converter 40 shown in FIG.
Each switch circuit S₀, S₁, S_Two, S_ThreeCorresponds
Digital input signal D₀, D₁, D_Two, D_ThreeAccording to
And the resistance element R₂₀, R_{twenty one}, R_{twenty two}, R_{twenty three}One terminal of
Reference voltage V_ROr connect to one of the grounds.
In the illustrated example, the digital input signal D₀, D₁, D
_Two, D_ThreeIs high level, the corresponding resistance element
R₂₀, R_{twenty one}, R_{twenty two}, R _{twenty three}Is connected to the reference voltage V_RTo
Connected to ground when low level
It is.

Here, when only the digital input signal D ₀ is at a high level, the combined resistances on the left, lower and right sides of the point D are 2R, 2R and 43R / 21, respectively, and the voltage V _{D at the} point _D is a reference. the voltage V _R × 43/128. The voltage V _C at the point _C is the voltage V _{D at the} point _D × 22/4.
3, ie, the reference voltage V _R × 11/64, and the voltage V _B at the point _B is the voltage V _C × 6/11 at the point _C , ie, the reference voltage V
_R × 3/32, and the voltage V _A at the point _A is the voltage V _{B at the} point _B
× 2/3, that is, the reference voltage V _R / 16.

Similarly, the voltage V A at the point _A is equal to the reference voltage V _R when only the digital input signal D ₁ is at a high level.
/ 8, and becomes the reference voltage V _R / 4 when only the digital input signal D ₂ is at the high level, and becomes the reference voltage V _R / 2 when only the digital input signal D ₃ is at the high level. Also, the digital input signals D ₀ , D ₁ , D ₂ , D ₃
Are simultaneously at the high level, the voltage VA at point _A is the sum of these output voltages.

In this manner, the voltage VA at the point _A is input to the + input terminal of the operational amplifier OP, and the digital input signals D ₃ , D ₂ , D ₁ and D ₀ are output from the output terminal of the operational amplifier OP.
, An analog output signal converted to a predetermined voltage level is output.

By the way, the above-mentioned R to which the CMOS is applied is used.
In the -2R type DA converter 40, the switch circuit 4
The PMOS 48 and the NMOS 50 constituting the second 2 have an on-resistance. The PMOS 48 and NMOS 50
Is connected in series with the resistance element R _2n , and its resistance value and fluctuations in the resistance value are one of the major factors that adversely affect the conversion accuracy of the DA converter 40.

Therefore, the resistance value of the on-resistance of the switch circuit needs to be sufficiently small so that it can be regarded as almost zero with respect to the resistance values of the resistance elements R _1n and R _2n , and the resistance of each switch circuit is required. It is necessary to minimize the fluctuation of the resistance value of the on-resistance. For this reason, the PMOS 48 and the NMOS 50 forming the switch circuit 42 have conventionally been used.
By increasing the transistor width W, the resistance value of the on-resistance and the fluctuation of the resistance value are suppressed to be small.

[0013] However, in the CMOS, both PMOS48 and NMOS50 in the vicinity logic threshold is turned on, thereby transiently through current flows toward the ground from the reference voltage V _R. In the R-2R DA converter 40 to which CMOS is applied, a PMOS 48 and an NMOS 50 constituting the switch circuit 42 are provided.
For transistor width W is large, not only the consumption current through current is increased (power consumption) increases, noise potential between the reference voltage V _R and ground varies occurs, the DA converter 40 There is a problem that conversion accuracy may be adversely affected.

Next, FIG. 9 shows a layout of an example of a conventional R-2R DA converter. The layout of the illustrated example is such that the operational amplifier OP and the switch circuit 4 in the configuration circuit of the DA converter 40 shown in FIGS.
2 corresponding to a portion excluding the PMOS 44 and the NMOS 46, and constituting the switch circuit 42.
8 and NMOS 50 corresponding to PMOS 52 and N
It comprises a MOS 54 and resistance elements 56 and 58 corresponding to the resistance elements R _1n and R _2n .

In the layout shown in FIG.
2 is configured by connecting five divided PMOSs in parallel, and similarly, the NMOS 54 is divided into five divided NMOSs.
Are connected in parallel. The resistance element 56 is constituted by a polysilicon resistance having a resistance value R. Similarly,
The resistance element 58 is configured by connecting two polysilicon resistors each having a resistance value R in series.

Here, FIG. 6A is a conceptual diagram showing an example of a transistor characteristic of a switch circuit used in a DA converter having the above-described layout. Transistor characteristics of the illustrated example, for example, and so the switching circuit on-resistance of the S _0> ON resistance of the switch circuits S _1> ON resistance of the switch circuit S _2> on-resistance of the switching circuit S _3, the on-resistance of the switch circuit 42 7 conceptually illustrates an example of a case where the resistance value has a slope.

In the layout of the illustrated example, since the transistor width W of the PMOS 52 and the NMOS 54 constituting the switch circuit is large, most of the DA converter 40 is occupied by the switch circuit. Therefore, for example, the transistor characteristics of the switch circuit S ₀ and the switch circuit S ₃ , for example, the resistance values of the on-resistances of the PMOS 48 and the NMOS 50 are significantly different due to manufacturing variations and the like. There is a problem that the conversion accuracy may be adversely affected and the yield of products is reduced.

[0018]

SUMMARY OF THE INVENTION It is an object of the present invention to reduce or completely prevent a through current in the vicinity of a threshold value when a state of a switch circuit changes, in view of the problems based on the prior art. It is another object of the present invention to provide a DA converter capable of reducing current consumption and improving the yield of products.

[0019]

In order to achieve the above object, according to the present invention, one end of the resistance element is connected to one of a reference voltage and a ground in accordance with a resistance element and an input digital input signal. An R-2R DA converter for outputting an analog output signal having a voltage level corresponding to the digital input signal, wherein the switch circuit comprises a first P-type MOS transistor.
A transistor, a first N-type MOS transistor, the
Two P-type MOS transistors and a second N-type MOS transistor.
And Njisuta than said first timing to be the OFF state of the N-type MOS transistor, the Ru delays the timings of turning on the first P-type MOS transistor
1 delay element and the timing at which the first P-type MOS transistor is turned off.
A second delay element for delaying the timing at which the S transistor is turned on, wherein the sources of the first P-type MOS transistor and the first N-type MOS transistor are connected to the reference voltage and the ground, respectively. Each of these drains is short-circuited and connected to one end of the resistance element, and the second P-type MOS transistor and
And the source of the second N-type MOS transistor is
These are connected to the power supply voltage and ground, respectively.
The digital input signal is input to both ports,
The drain of the second P-type MOS transistor is
The gate of the first P-type MOS transistor and the second
The second N-type MOS transistor is connected to the input terminal of the delay element.
The drain of the transistor is connected to the first N-type MOS transistor.
Connected to the gate of the transistor and the input terminal of the first delay element.
Output terminals of the first and second delay elements
The first P-type MOS transistor and the first
Input to the gate of the N-type MOS transistor of
The first and second P-type MOS transistors,
The first and second N-type MOS transistors and
The first and second delay elements are each divided into a predetermined number.
Of the divided first P-type MOS transistor
The source and the drain are connected in parallel,
Over DOO via the first delay element corresponding divided
The first N-type MOS transistors sequentially connected in series and divided
The source and drain of the transistor are connected in parallel
And the gate is divided by the corresponding second delay
The second device, which is sequentially connected in series via an element and divided
Source and gate of P-type MOS transistor
Connected in parallel, with their drains divided
Connected to the gate of the first P-type MOS transistor;
Source of the divided second N-type MOS transistor
And the gate are connected in parallel, and the drain is
Divided corresponding first N-type MOS transistor
And a D / A converter characterized by being connected to a gate of the D / A converter.

Here, the DA converter described above is used.
Thus, n switch circuits are provided, and each of the
A first P-type MOS transistor included in a switch circuit;
And the first N-type MOS transistor
Each of the switches
The first P-type MOS transistor and the
The first N-type MOS transistors are taken out one by one.
And each of the n first P-type MOS transistors
And n first N-type MOS transistors.
Are divided into m groups.
It is preferable to have a split layout structure .

[0021]

[0022]

[0023]

[0024]

[0025]

In the DA converter of the present invention, basically, the delay means delays the N of the switch circuit from the timing of turning off the PMOS of the switch circuit.
Delay the timing of turning on the MOS, and
The timing of turning off the PMOS
Is delayed, that is, PM
It is configured to reduce the time during which the OS and the NMOS are simultaneously turned on, or to generate the time during which the OS and the NMOS are simultaneously turned off. Further, the DA converter of the present invention
In a DA converter having N switch circuits each including m PMOSs and NMOSs, one PMOS and one NMOS are taken out from each switch circuit and divided into m groups each including n PMOSs and NMOSs. In addition, it has a layout structure in which these groups are arranged as a unit. For this reason,
According to the DA converter of the present invention, the delay means
Through current in the vicinity of the logic threshold value of the switch circuit can be reduced or completely prevented, and the layout structure can make the transistor characteristics between the switch circuits, especially the transistor on-resistance uniform. Therefore, according to the DA converter of the present invention, not only the current consumption is reduced, but also the occurrence of noise due to the through current is reduced or completely prevented, the conversion accuracy of the DA converter is improved, and the production yield of the product is improved. Is done.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a DA converter according to the present invention will be described in detail based on a preferred embodiment shown in the accompanying drawings. The DA converter of the present invention is applicable to an R-2R type DA converter employing any system. Hereinafter, the DA adopting the voltage addition method shown in FIG.
A description will be given using a converter as an example.

FIG. 1 is a circuit diagram of a switch circuit used in a DA converter according to an embodiment of the present invention. In the illustrated example, the switch circuit 10 includes a PMOS 12a, 1
2b, 12c, NMOSs 14a, 14b, 14c,
PMOS 16a, 16b, 16c and NMOS 18a,
18b, 18c and resistance elements 20a, 20b, 20c
And resistance elements 22a, 22b, and 22c.

That is, the switch circuit 10 shown in FIG.
Is compared with the switch circuit 42 shown in FIG.
Is divided into three PMOSs 12a, 12b, and 12c,
These PMOSs are connected in parallel.
To the three NMOSs 14a, 14b, 14c, and the PMOS
48 to three PMOSs 16a, 16b, 16c, and NM
The OS 50 is divided into three NMOSs 18a, 18b, and 18c, respectively, and these PMOSs and NMOSs are connected in parallel.

In this switch circuit 10, a PMOS
12a, 12b, 12c and NMOS 14a, 14
b, 14c are connected to the power supply voltage V _DD and the ground, respectively, and the gate thereof is connected to the digital input signal D DD.
_n are commonly input, and their drains are
S16a, 16b, 16c and NMOSs 18a, 18
b, 18c are input to the gates.

The drain of the PMOS 12a is input to the gate of the NMOS 18a via the resistance element 22a, further input to the gate of the NMOS 18b via the resistance element 22b, and further connected to the NMO via the resistance element 22c.
It is input to the gate of S18c. Similarly, NMOS
The drain of 14a is connected to a PMOS through a resistance element 20a.
The signal is input to the gate of the PMOS 16b via the resistance element 20b, and further input to the gate of the PMOS 16c via the resistance element 20c.

On the other hand, PMOS16a, 16b, 16c and NMOS18a, 18b, 18c source connected to the reference voltage V _R and ground, respectively, the drain is the output terminal OUT are short-circuited. In the following description, PMOS16a, 16b, N ₁₁ an input signal input to the gate of 16c respectively, N _12, N
_13. Similarly, input signals input to the gates of the NMOSs 18a, 18b, 18c are N ₂₁ , N ₂₂ , N ₂₃ , respectively.
And

Here, FIG. 2 shows the structure of the present invention shown in FIG.
Represents the operation of the switch circuit used in the DA converter
4 shows a timing chart. First, the digital input signal
D_nIs low, the PMOSs 12a, 12b, 1
2c and NMOSs 14a, 14b, 14c are respectively
An on state and an off state. Therefore, the input signal
N ₁₁, N₁₂, N₁₃And the input signal N_{twenty one}, N_{twenty two}, N_{twenty three}Hato
Are at the high level, and the PMOSs 16a, 16b, 16
c and NMOSs 18a, 18b, 18c are
In the off state and the on state.
The output terminal OUT is at a low level.

[0033] Next, when the digital input signal D _n is changed from low level to high level, PMOS12a,
12b, 12c and NMOS 14a, 14b, 14c
Change to an off state and an on state, respectively. At this time, since the NMOSs 14a, 14b, and 14c are turned on, the input signals N ₂₁ , N ₂₂ , and N ₂₃ instantaneously go to a low level almost simultaneously, so that the NMOSs 18a, 18c
b and 18c are instantaneously turned off almost simultaneously.

On the other hand, the input signal N ₁₁ is equal to the input signals N ₂₁ , N
₂₂ and N _23, the resistance R and the resistance
It changes to a low level at a timing delayed by the time constant of the gate capacitance C of S16a. Similarly, the input signal N _12, only a constant amount when by further gate capacitance C of the resistance value R and PMOS16b resistive element 20b than the input signal N _11, the input signal N ₁₃ further resistive element than the input signal N ₁₂ It changes to a low level at a timing delayed by the time constant of the resistance value R of 20c and the gate constant C of the PMOS 16c. That is, the output terminal OUT of the switch circuit 10 is connected to the PMOS 16a, 16b, 1
6c sequentially changes to the high level in accordance with the timing of turning on.

[0035] Incidentally, when the digital input signal D _n is changed from a high level to a low level, PMOS12a,
12b, 12c, NMOS 14a, 14b, 14c, P
MOS 16a, 16b, 16c, NMOS 18a, 18
b, the state of 18c, the input signal _{N 11, N 12, N 13} , the input signal _{N 21, N 22, N 23} , the output terminal OU of the switch circuit 10
Except that T is the voltage level of the reversed operates in exactly the same manner as when the digital input signal D _n is changed from low level to high level.

As described above, in the DA converter of the present invention using the switch circuit 10 shown in FIG. 1, the PMOSs 16a, 16b, 16
c and NMOSs 18a, 18b, 18c reduce the time during which they are simultaneously turned on near the logic threshold value or generate the time during which they are simultaneously turned off, thereby reducing or completely preventing through current. In addition, current consumption can be reduced, noise can be prevented, the accuracy of the DA converter can be improved, and the product yield can be improved.

Although an embodiment of the switch circuit used in the DA converter of the present invention has been described, the present invention is not limited to this embodiment.

For example, a PMOS constituting a switch circuit
And the NMOS may be divided into a predetermined number,
It does not have to be divided. In the case of division, the number of divisions may be appropriately set so as to reduce or prevent the through current according to the error range allowed from the number of bits of the DA converter. Conversely, when the division is not performed, for example, the PMOSs 12a and 16a and the NMOSs 14a and 18a in FIG.
In addition, a switch circuit may be constituted by only the resistance elements 20a and 22a.

As the delay element, for example, a capacitance element may be connected in parallel instead of the resistance element, or a delay may be made by connecting a predetermined number of inverters and buffers in series. In the switch circuit 10 of the illustrated example, the resistance elements 20a, 20b, 20
c and the resistance elements 22a, 22b, 22c are composed of, for example, a polysilicon resistance, diffusion, or the like.

FIG. 3 is a circuit diagram of another embodiment of the switch circuit used in the DA converter of the present invention. The illustrated switch circuit 24 includes inverters 26a, 26b, 26c each having a different logical threshold value.
, PMOSs 28a and 28b and NMOSs 30a and 30
b. The inverters 26a, 26b,
26c have logical thresholds of 1.5V, 2.5V and 3.5V, respectively, and the following description is made on the assumption that the power supply voltage is 5V.

The switch circuit 24 of the illustrated example uses inverters 26a, 26b and 26c having different threshold values, respectively, in place of the inverter composed of the PMOS 44 and the NMOS 46 as compared with the switch circuit 42 shown in FIG. The PMOS 48 is divided into two PMOSs 28a, 2
8b, these PMOSs are connected in parallel, and similarly, the NMOS 50 is divided into two NMOSs 30a, 30b, and these NMOSs are connected in parallel.

[0042] In the switch circuit 24 of the illustrated embodiment, the inverters 26a, 26b, both the digital input signal D _n is input to an input terminal of 26c, the output terminal of the inverter 26a is input to the gate of NMOS30a, the output terminal of the inverter 26b Are PMOS 28b and NMOS 30b
, And the output terminal of the inverter 26c
The signal is input to the gate of the OS 28a.

The PMOSs 28a, 28b and NM
OS30a, 30b source connected to the reference voltage V _R and ground, respectively, the drain is the output terminal OUT are short-circuited. In the following description, the output signals of the inverters 26a, 26b, 26c, that is, the NMOS 30a, the PMOS 28b, and the NMOS 3
0b, the input signal input to the gate of PMOS28a and N _1, N _2, N _3, respectively.

FIG. 4 is a timing chart showing the operation of the switch circuit used in the DA converter of the present invention shown in FIG. First, when the digital input signal D _n is at a low level, the digital input signal D _n becomes
Inverted by inverters 26a, 26b, 26c,
The input signals N ₁ , N ₂ and N ₃ are all at a high level.
Therefore, the PMOSs 28a and 28b and the NMOS 30
Reference numerals a and 30b denote an off state and an on state, respectively, and the output terminal OUT of the switch circuit 24 is at a low level.

[0045] Next, when the digital input signal D _n is changed from low level to high level, the digital input signal D _n includes an inverter 26a having different logical threshold respectively, 26b, by 26c, the input signal N _1,
The signals are sequentially inverted in the order of N ₂ and N ₃ to become a low level. That is, the NMOS 30a is turned off, and then the NMO
S30b and PMOS 28b are turned off and on, respectively, and finally, PMOS 28a is turned on. Therefore, the output terminal OU of the switch circuit 24
T sequentially changes to the high level sequentially in accordance with the timing when the PMOSs 28a and 28b are sequentially turned on.

[0046] Incidentally, when the digital input signal D _n is changed from a high level to a low level, PMOS28a,
28b, the state of the NMOSs 30a and 30b, and the input signal N
₁ , N ₂ , N ₃ and the output terminal OUT of the switch circuit 24
And a voltage level except be reversed, operate exactly like as when the digital input signal D _n is changed from low level to high level.

As described above, in the DA converter using the switch circuit 24 in the illustrated example, the through current can be reduced in the same manner as in the DA converter using the switch circuit 10 shown in FIG. The current consumption can be reduced, the occurrence of noise can be prevented, the accuracy of the DA converter can be improved, and the production yield of products can be improved.

In the DA converter according to the present invention, the logical threshold value of the inverter driving the PMOS is made higher than the logical threshold value of the inverter driving the NMOS, so that the PMOS and NMOS constituting the switch circuit are formed. If it is possible to reduce the time for turning on simultaneously or to generate the time for turning off simultaneously, the PMOS and N
The number of divisions of the MOS is not particularly limited. That is, the PMOS and the NMOS constituting the switch circuit may have a configuration that is not divided, or may have a configuration that is divided into a predetermined number. In addition, PM that constitutes the switch circuit
When the OS and the NMOS are divided into a predetermined number, the PMOS and the NMOS may be individually driven by inverters having different thresholds.

Next, FIG. 5 shows a layout of an example of the DA converter of the present invention. The layout of the illustrated example is shown in FIG.
In the constituent circuit of the DA converter shown in FIG.
12a, 12b, 12c, NMOS 14a, 14b, 1
4c, corresponding to the constituent circuits except for the resistive elements 20a, 20b, 20c and the resistive elements 22a, 22b, 22c.
PMOS 32 corresponding to 16b, 16c, and N corresponding to NMOS 18a, 18b, 18c of the switch circuit 10.
MOS 34 and resistance element 36 corresponding to resistance element R _1n
And a resistance element 38 corresponding to the resistance element R _2n .

Here, the PMOS 32 and the NMOS 34
Is a PMOS divided into five and an N divided into five for each of the switch circuits S ₀ , S ₁ , S ₂ , and S _3.
MOS, ie, a total of 20 PMOSs and 20 N
It is configured by connecting MOS in parallel. These 20 PMOSs and 20 NMOSs are sequentially arranged one by one in the order of the switch circuits S ₀ , S ₁ , S ₂ , and S ₃ , respectively.
Five groups G ₀ , G ₁ ,
G ₂ , G ₃ , and G ₄ are arranged separately.

In the illustrated example, the resistance element 36 is constituted by a polysilicon resistance having a resistance value R. Similarly, the resistance element 38 is constituted by connecting two polysilicon resistances having a resistance value R in series. I have.

FIG. 6B is a conceptual diagram showing an example of the transistor characteristics of the switch circuit used in the DA converter having the above-described layout. Transistor characteristics of the illustrated example, and so for example the on-resistance of the group G _0> ON resistance of the groups G _1> ON resistance of the groups G _2> on-resistance of the group G _3> ON resistance of the groups G _4, on the inter-group 7 conceptually illustrates an example of a case where a resistance value of a resistor has a slope.

In the layout of the illustrated example, the group G
The resistance values of the on-resistances ₀ , G ₁ , G ₂ , G ₃ , and G ₄ have a slope like the resistance value of the on-resistance of the switch circuit shown in FIG. However, since the resistance values of the on-resistances between the PMOSs and the NMOSs constituting the respective groups G ₀ , G ₁ , G ₂ , G ₃ , G ₄ are formed substantially equal, the switch circuits S ₀ , S ₁ , S 4
_2, S ₃ between characteristics it is possible to equalize the, it is possible to improve the DA converter conversion accuracy, thereby improving the yield of the product.

In the layout of the illustrated example, PMs constituting the same switch circuits S ₀ , S ₁ , S ₂ , S ₃
The OS and the NMOS are, for example, the PMOS and the NMOS constituting the switch circuit S ₀ are arranged at a fixed interval, so that the gates of the PMOS and the NMOS constituting the respective switch circuits are provided for each switch circuit. For example, the resistance elements 20a, 20b, 20c and the resistance element 22 shown in the switch circuit 10 of FIG.
a, 22b, 22c can be easily configured.

In the illustrated example, the arrangement order of the PMOS and the NMOS in each group is all the same, but in the DA converter of the present invention,
The order of arranging the PMOS and the NMOS in one group is not particularly limited, and may be the same order, symmetrical or random.

[0056]

As described in detail above, the D of the present invention
The A-converter is provided with delay means for PMOS and NMOS constituting the switch circuit, thereby reducing the time during which the PMOS and NMOS constituting the switch circuit are simultaneously turned on, or generating the time during which the PMOS and NMOS are simultaneously turned off. The logic circuit is configured to reduce or completely prevent a through current near a logic threshold of the circuit. Further, the DA converter of the present invention is a DA converter having n switch circuits, wherein PMOS and NMOS constituting each switch circuit are replaced with m PMOS and m NMO, respectively.
S, a PMOS and an NMOS are taken out from each switch circuit one by one, divided into m groups of n PMOSs and NMOSs, and have a layout structure arranged for each of these groups. is there. Therefore, according to the DA converter of the present invention, the through current of the switch circuit can be reduced or completely prevented, and the on-resistance between the switch circuits can be made uniform, so that the current consumption can be reduced. Of course, the conversion accuracy of the DA converter can be improved, and the production yield can be improved.

[Brief description of the drawings]

FIG. 1 is a configuration circuit diagram of an embodiment of a switch circuit used in a DA converter of the present invention.

FIG. 2 is a timing chart of an embodiment showing an operation of the switch circuit shown in FIG.

FIG. 3 is a configuration circuit diagram of another embodiment of the switch circuit used in the DA converter of the present invention.

FIG. 4 is a timing chart of one embodiment showing an operation of the switch circuit shown in FIG. 3;

FIG. 5 is a layout of a DA converter according to an embodiment of the present invention.

6A is a conceptual diagram illustrating an example of a transistor characteristic of a switch circuit used in the conventional DA converter shown in FIG. 9, and FIG. 6B is a switch used in the DA converter of the present invention shown in FIG. FIG. 3 is a conceptual diagram of an example showing transistor characteristics of a circuit.

FIG. 7 is a configuration circuit diagram of an example of a conventional DA converter.

FIG. 8 is a circuit diagram illustrating an example of a switch circuit used in a conventional DA converter.

FIG. 9 is a layout of an example of a conventional DA converter.

[Explanation of symbols]

_{10,24,42, S 0, S 1,} S 2, S 3 switch circuits 26a, 26b, 26c inverters 12a, 12b, 12c, 16a, 16b, 16c, 2
8a, 28b, 32, 44, 48, 52 P-type MOS transistors (PMOS) 14a, 14b, 14c, 18a, 18b, 18c, 3
0a, 30b, 34, 46, 50, 54 N-type MOS transistors (NMOS) 20a, 20b, 20c, 22a, 22b, 22c, 3
_{6,38,56,58, R 10, R 11,} R 12, R 20,
R ₂₁ , R ₂₂ , R ₂₃ , R ₂₄ resistance elements D ₀ , D ₁ , D ₂ , D ₃ , D _n digital input signals N ₁₁ , N ₁₂ , N ₁₃ , N ₂₁ , N ₂₂ , N ₂₃ , N ₁ , N ₂ , N
₃ the input signal OUT output terminal V _DD supply voltage V _R the reference voltage OP operational amplifier _{G 0, G 1, G 2} , G 3, G 4 group

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) H03M 1/00-1/88 H03K 17/00-17/70

Claims (2)

(57) [Claims] A resistive element, and a switch circuit for connecting one end of the resistive element to one of a reference voltage and a ground in accordance with an input digital input signal;
An R-2R DA converter that outputs an analog output signal having a voltage level corresponding to the digital input signal, wherein the switch circuit includes a first P-type MOS transistor, a first N-type MOS transistor, Second P-type MO
An S transistor, a second N-type MOS transistor,
Said first N-type MOS than the timing of the OFF state of the transistor, the first P-type MOS transistor the first delay element timing which is turned Ru delaying the
And a second delay for delaying a timing at which the first N-type MOS transistor is turned on, more than a timing at which the first P-type MOS transistor is turned off.
And an element, the first P-type MOS transistor and the first N
Type source of the MOS transistor is connected to the reference voltage and the ground, respectively, each of these drains is connected to one end of the resistive element is shorted, the second
A P-type MOS transistor and the second N-type MOS transistor;
The sources of the transistors are the power supply voltage and ground, respectively.
And each of these gates together has the digital
Input signal is input to the second P-type MOS transistor.
The drain of the first P-type MOS transistor
And the input terminal of the second delay element
And the drain of the second N-type MOS transistor is:
A gate of the first N-type MOS transistor;
The output terminals of the first and second delay elements are connected to the input terminal of a first delay element, respectively.
A first P-type MOS transistor and the first N-type M
Input to the gate of the OS transistor, and further to the first and second P-type MOS transistors.
The first and second N-type MOS transistors
And the first and second delay elements each have a predetermined number.
And the source of the divided first P-type MOS transistor
And the drain are connected in parallel, and the gate is
Sequentially directly through the split corresponding first delay element
Column-connected and divided sources of the first N-type MOS transistor
And the drain are connected in parallel, and the gate is
Directly sequentially through the divided corresponding second delay elements
Column-connected and divided sources of the second P-type MOS transistor
And the gate are connected in parallel, and the drain is
Divided corresponding first P-type MOS transistor
Source of the divided second N-type MOS transistor connected to the gate of
And the gate are connected in parallel, and the drain is
Divided corresponding first N-type MOS transistor
A DA converter, which is connected to a gate of the D / A converter. 2. The DA converter according to claim 1, wherein
And n switch circuits, each of the switches
The first P-type MOS transistor and the
M each of the first N-type MOS transistors
And the first P-type MOS is provided from each of the switch circuits.
Transistor and first N-type MOS transistor
Are taken out one by one, and each of the n first P
MOS transistor and n first N-type MOs
Divided into m groups of S transistors
It has a layout structure divided and arranged for each of these groups.
A DA converter characterized in that: