JPS60105323A - Digital-analog converter - Google Patents

Abstract

PURPOSE:To improve the conversion accuracy and manufacture yield by constituting plural inverter circuits of an inverter circuit section with a series of parallel connection of MOS inverters to each bit and forming them in a small area of square semiconductor region. CONSTITUTION:An equivalent circuit where each inverter circuit is constituted by complementary MOS inverters is constituted with analog switches S1-Sn responding respectively to an n-bit signal of digital input, ON resistors RN1- RNn of N-channel insulation gate FET and a reference potential VR. A series of parallel connection of insulation gate FETs are provided to each bit and the total channel width of the FETs is formed to be a desired channel width. Furthermore, the ON resistance is decreased sufficiently by connecting the insulation gate FETs in parallel.

Description

Detailed Description of the Invention The present invention relates to a digital-to-analog converter in which an R-2R resistor ladder network is driven by an inverter circuit, and the inverter circuit section is integrated into an IC (integrated circuit) according to a unique layout pattern. This reduces conversion errors and improves production yield.

Conventionally, this type of digital-to-analog converter has not been integrated into an IC as a whole; instead, an R-2R resistor ladder network and an inverter circuit to drive it have been prepared separately, and these have been assembled in a hybrid manner. It was composed of

In digital-to-analog converters configured in this way, since the inverter circuit is not specially designed and manufactured for DA conversion, there are variations in characteristics such as resistance between inverters, and it is difficult to improve conversion accuracy. It was a hindrance.

An object of the present invention is to provide a novel digital-to-analog converter in which an R-2R type resistor ladder network and an inverter circuit are made into a monolithic IC to improve conversion accuracy and manufacturing yield.

The digital-to-analog converter according to the present invention includes a group of MOS inverters connected in parallel for each bit of a plurality of inverter circuits Y in the inverter circuit section, and can also include a large number of MOS inverters belonging to the inverter circuit section. It is characterized in that it is formed within a rectangular semiconductor region with a small area. In this specification, the term "MO8 type inverter" refers to an inverter having an insulated gate type FET (field effect transistor) as an active element.

The invention will now be described in detail with reference to embodiments shown in the accompanying drawings.

FIG. 1 shows the circuit configuration of a digital-to-analog converter to be integrated into an IC according to the present invention. It looks like this.

Input terminals Il to I corresponding to n bits of digital input
Input buffer sofas BF1 to BFn are connected to each input buffer sofa, and each input buffer sofa has a configuration in which two inverter circuits are connected in cascade.

Output terminals 0□~On of input capacitors BF1~BFn are R-
It is connected to the corresponding resistor 2R of the 2R type resistor ladder network LA, and the analog output voty'r can be taken out from the most significant bit (MSB) side of the resistor ladder network LA.

FIG. 2 shows an equivalent circuit when each inverter circuit in the circuit of FIG. 1 is configured with a complementary MO8 type inverter, and 81 to Sn are analog switches each responding to an n-bit signal of digital input; RPI to RPn are P-channel insulated gate FETs
, RNI to RNn are the on-resistances of the N-channel insulated gate FETs, and VR is a reference potential higher than the ground potential.

In the digital-to-analog converter described above, in order to reduce conversion errors, it is necessary not only to increase the resistance accuracy in the R-2R resistance ladder network LA, but also to increase the absolute values of the on-resistances RPI to RPn and RNI to RNn that lead to this. The on-resistance may be made small enough to be ignored, or the on-resistance may be doubled for each lower bit.

In reality, if the absolute values of RPI~RPn and RNI~RNn are made smaller, the inverter size will become larger, which will impede IC integration, and will also make latch-up more likely to occur, so the absolute value of the on-resistance should be made smaller. On the other hand, the on-resistance is made to double each time the bit becomes a lower bit.

In order to double the on-resistance in this way,
If the channel length of an insulated gate FET is the same, the channel width can be halved, but if this is done, the channel width will become wider as it approaches the MSB side, and at the MSB it will be 5.000 mm. ~10,000
(μm:l). Therefore, arranging the bits as they are is not a good idea because it not only results in poor pattern efficiency but also increases the variation in on-resistance between bits.

Therefore, in this invention, a group of parallel-connected insulated gate type FET'Y is provided for each bit, and these FETs
The sum of the channel widths is the desired channel width. Furthermore, by connecting it in parallel to the insulated gate FET', the on-resistance can be made sufficiently small.

FIG. 3 is a representative diagram of the configuration of the input buffer section in an IC-based digital-to-analog converter according to an embodiment of the present invention for the n-th bit (MSB) and the n-i-th bit. An equivalent circuit for the n-th bit input buffer is shown in FIG.

The n-th first inverter circuit 1o includes a plurality of complementary MO8-type inverters connected in parallel, and such a configuration includes the n-th second inverter circuit 12, the The same applies to the first and second inverter circuits and η.

In the n-th input buffer, the output terminal (drain D) of the first inverter circuit 10 is connected to the input terminal (gate G) of the second inverter circuit 12, and such a connection is n-1. The first bit input capacity
The same applies to the second inverter circuits and the fourth inverter circuits.

As mentioned above, a large number of complementary MO8 type inverters constituting a plurality of inverter circuits are formed in a rectangular semiconductor region, and each channel length direction of these inverters is parallel to one side of the rectangle, and each channel length direction is parallel to one side of the rectangle. so that the width direction is parallel to the other side perpendicular to the - side of the rectangle, and from MSB (nth bit) to LSB.
The inverter groups up to (the least significant bit) are arranged along the other side of the rectangle in the order described.

The channel lengths of the multiple complementary MO8 type inverter groups are defined to be the same for all bits. In addition, the numerous complementary MO8! The channel width of the inverter is defined so that it is halved for each lower bit. For example, in the n-th input buffer, a P-channel insulated gate FET
If channel width y<Wp and channel width YWN of an N-channel insulated gate FET, then n
In the -1st bit buffer, the channel width of the P-channel insulated gate FET is Wp/2,
The channel width of each N-channel insulated gate FET is set to WN/2.

In the n-th input buffer, the input terminal (gate G) of the first inverter circuit 100 is connected to the input terminal □ via the input resistor IRnY, and
The output terminal (drain D) of is connected to the output terminal on.

Similarly, in the n-1th bit input buffer, the input terminal of the first inverter circuit is connected to the input resistor lR.
The input terminal of the second inverter circuit n-1 is connected to the output terminal In-1. Note that the input resistors IRn and lRn-1 are formed to pass under the first power supply line VSS and the second power supply line VDD.

In the n-th input buffer, the wiring layer 14 for the source S of the P-channel insulated gate FET is connected to the second power supply line "DD via the cross resistor CRnY, and the wiring layer 14 for the source S of the P-channel insulated gate FET is connected to the second power supply line "DD" S
The wiring layer for is connected to the first power supply line VSS. Similarly, in the (n-1)th input buffer, the wiring layer for the source S of the P-channel insulated gate FET is connected to the second power supply line VDD via the cross resistor CRn-IY. , the wiring layer for the source S of the N-channel insulated gate FET is the first wiring layer.
is connected to the power supply line VSg. Note that the first power supply line VS8 provides a relatively low reference potential (corresponding to the ground potential in FIG. 2), and the second power supply line VDD provides a relatively high reference potential (for example, the ground potential in FIG. 2). (equivalent to VR).

As mentioned above, if an inverter group is arranged for each bit and two or more power lines are connected to them, as well as a human power line and an output line, a cross resistor must be connected to the output line. However, in this case, the potential of the output line changes depending on the inverter output, which increases the capacitance and delays the response speed of the inverter output. In addition, in a cross resistance whose capacitance is negligible, the resistance is large and
Affects conversion error.

In order to solve this longevity problem, in the above embodiment,
A cross resistor is attached to the power supply line without adding a cross resistor to the inverter output line.

In this case, in order to reduce the conversion error, the value of the cross resistance should be reduced to less than the allowable limit.
It is effective to double the cross resistance for each lower bit.

In order to double the cross resistance in this way,
In the above embodiment, the cross resistors CRn and CRn-0 are made to have the same length LCR, and the width YWCR of the cross resistor CRn is set to the width YWca/of the cross resistor CRn1.
I'm setting it to 2. Note that the cross resistances CRn and CRn
1 are arranged so that each width direction is parallel to the channel width direction and each length direction is perpendicular to the channel width direction, and in this way, the above-mentioned MO
Together with the S-type inverter arrangement, this is useful for reducing the input capacitor size.

FIG. 5 shows a cross section taken along the line ■-■ in FIG.

A diffused resistance layer 32 is formed on the surface of the semiconductor substrate (material), and a source wiring layer 14 and a first 2- power source are connected to one end and the other end of this diffused resistance layer 32, respectively. Line VDD is connected. A resistive layer made of polysilicon or the like is formed on the diffused resistive layer 32 via an insulating layer 34, and one end and the other end of this resistive layer I are connected to the source wiring layer 14 and the second resistive layer I, respectively. power line vDD
It is connected to the. A first power supply line V8B is formed on the resistance layer I via the insulating layer 38, and this first power supply line V8B is
The power supply line V88 extends between and parallel to the source wiring layer 14 and the second power supply line VDD.

The cross resistance CRn is constituted by two resistance layers 32 and 32 which are connected in parallel and arranged one on top of the other, and other cross resistances such as CRn are constituted in the same manner.

Configuring the cross resistance in this way: 1. This has the advantage of making it easier to reduce the cross resistance value to below a permissible limit and reducing the area occupied by the cross resistance.

As described above, according to the present invention, the inverter circuit is configured with a group of MO8 type inverters connected in parallel for each bit, and the channel width of the YKOS type inverter is halved each time the lower bit becomes l bit. As a result, the on-resistance is reduced for each bit, and the variation in on-resistance between bits is reduced, and conversion accuracy and manufacturing yield can be greatly improved. In addition, a large number of MOS inverters with channel lengths are arranged in a two-square semiconductor region, and each of these inverters has a channel length direction parallel to one side of the rectangle and a channel width direction of each inverter. Both are arranged parallel to the other side orthogonal to the - side of the rectangle, and the inverter groups from the most significant bit to the least significant bit are arranged along the other side of the rectangle in the order described. Therefore, there is an effect that the area occupied by the inverter circuit section on the semiconductor chip can be minimized.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a digital-to-analog converter to be integrated into an IC according to the present invention, and FIG.
An equivalent circuit diagram when each inverter circuit in the circuit shown in FIG. , FIG. 4 is an equivalent circuit diagram of the n-th input/sofa in FIG. 3, and FIG. 5 is a sectional view taken along the line ■-■ in FIG. 3. BF□～BFn...Input power, S1%Sn・
... Analog switch, LA... R-2R type resistance ladder network, 10, 12, 20, 22... Inverter circuit. Applicant Nippon Gakki Mfg. Co., Ltd. Agent Patent Attorney Toshiaki Izawa Figure 1, pFn Figure 2 Written amendment to professional procedures (spontaneous) December 1999 lJ Date Showa Kaku Patent Application No. 213023 2, Title of Invention Digital- Analog converter 3, relationship to the amended person case Patent applicant No. 1 Nakazawa-cho, Hamamatsu City, Shizuoka Prefecture (407) Nippon Gakki Mfg. Co., Ltd. Representative Hiroshi Kawakami 4, Agent 116 Nishi, Arakawa-ku, Tokyo Nippori 5-chome 11-7 YM Building 702 No. 5, Subject of amendment 6 - Contents of amendment (1) The "Claims" column of the specification is amended in accordance with the attached appendix 9. (2) On page 7, lines 2 to 4 of the specification, it says that [the inverter circuit 10 includes...]. , ] to be corrected. (3) On page 7, lines 2 to 4, and line 1 of the specification, the phrase ``In addition...in this order of description'' was replaced with ``In the order in which the inverters of multiple bits are connected. Correct to "in order". (4) On page 8, line 5 of the specification, the phrase "for all bits" is corrected to "for a group of inverters of multiple bits." (5) On page 13 of the specification, line 11, “The capacitance increases,
'' should be corrected to ``Because of capacitance.'' (6) On page 13 of the specification, lines 8 to 9, it says “Moreover...
...in the order of this description" should be corrected to "in addition, the inverter groups of multiple bits are arranged in bit order." (7) Figures 4 and 5 of the drawings shall be revised in the attached appendix. Claims (a) A plurality of inverter circuits each corresponding to a plurality of bits of digital input; (b) A plurality of input terminals each receiving a plurality of bits of the digital input signal via the plurality of inverter circuits. and the signal linear D from these input terminals
In a digital-to-analog converter equipped with an R-2R type resistor ladder network for A conversion, and an output means for extracting an analog output from the resistor ladder network, the plurality of inverter circuits are arranged in groups for each bit. It is formed in a substantially rectangular semiconductor region including a number of MOS type inverters connected in parallel, and a large number of MOS type inverters in this semiconductor region.
The type inverter is arranged such that the length direction of each channel is parallel to one side of the rectangle, and the width direction of each channel is almost parallel to the other side of the rectangle that is orthogonal to the - side. upper O inverter groups are arranged in bit order along the other side of the rectangle;
The channel length of the multiple MOS type inverters is the multiple bits 9Δ.For one color group, the channel length is 111□□
-Drop - Piece■-1-11. □1-□Sound is defined as the same,
The channel width of the plurality of MOS type inverters is specified to be halved for each lower bit. .

Claims (1)

[Scope of Claims] (a) A plurality of inverter circuit units each corresponding to a plurality of bits of digital input; (bl) a plurality of input terminals each receiving a plurality of bits of the digital input signal via the plurality of inverter circuits; and the signals 'Y IJ from these input terminals
In the R-2R resistor ladder network that performs near-DA conversion, and (c) the digital-to-analog converter that serves as an output means for extracting an analog output from this resistor ladder network, the plurality of inverter circuits A group of MOS inverters connected in parallel are formed in an approximately rectangular semiconductor region, and a large number of MOS inverters in this semiconductor region are
The type inverter is arranged such that the length direction of each channel is parallel to one side of the rectangle, and the width direction of each channel is almost parallel to the other side of the rectangle that is orthogonal to the - side. The inverter groups from to the least significant bit are arranged along the other side of the rectangle in the stated order, and the channel lengths of the large number of MOS inverters are defined to be almost the same for all bits. A digital-to-analog converter characterized in that the channel width of the MOS inverter is regulated to be halved for each lower bit.