JP4570946B2 - Digital / analog converter, ΔΣ modulation type analog / digital converter and mobile communication terminal - Google Patents

Description

  The present invention relates to a digital-to-analog converter.

  A digital-to-analog converter (hereinafter referred to as a D / A converter) that converts a digital input signal into an analog output signal is one of important circuit blocks that form the basis of various digital signal processing circuits. In particular, the performance of a DSP (Digital Signal Processor) used inside a communication device such as a mobile phone or an audio device depends on the accuracy and processing speed of the D / A converter.

  These D / A converters may be used alone or may be used in an analog-digital converter (hereinafter referred to as an A / D converter). There are several D / A converter variations such as R-2R type, segment R-2R type, and capacitor array type that have different circuit formats, and they are properly used according to required characteristics such as conversion accuracy and conversion speed. (Patent Document 1, Patent Document 2).

  As an example in which the D / A converter is built in the A / D converter, there is a ΔΣ modulation type A / D converter (hereinafter referred to as a ΔΣ A / D converter) frequently used in digital audio and communication DSPs. FIG. 7 is a diagram showing a configuration of a general ΔΣ A / D converter. The ΔΣ A / D converter 500 includes a ΔΣ modulation circuit 520 and a decimation filter 530. The ΔΣ modulation circuit 520 includes an integrator 600, a D / A converter 610, and an A / D converter 620.

  For digital audio applications, the ΔΣ A / D converter 500 is required to have a performance of about 12 bits, for example. The D / A converter 610 used in such a ΔΣ A / D converter 500 may have about 4 bits, but high conversion accuracy corresponding to about 12 bits is required. Therefore, it is suitable to use a capacitor array type D / A converter for the D / A converter 610 instead of the R-2R type or the segment R-2R type.

JP2001-345702 JP2003-258642A

  However, the capacity array type D / A converter has a drawback that a high-performance amplifier is required, and the circuit consumes a large amount of current due to the high-performance amplifier.

  If the accuracy of the R-2R type or segment R-2R type D / A converter can be improved, the ΔΣ A / D converter can be replaced with the above-described capacitance array type D / A converter. An amplifier is unnecessary, and the current consumption of the circuit can be reduced.

  The present invention has been made in view of such problems, and an object thereof is to provide an R-2R type and segment R-2R type D / A converter with improved conversion accuracy.

  One embodiment of the present invention relates to a digital-to-analog converter. This digital-analog converter is an R-2R type digital-analog converter, and includes a ladder network resistor network to which a plurality of resistors are connected, a reference voltage source that supplies a reference voltage to a connection node of the plurality of resistors, A plurality of switches provided between a connection node of the plurality of resistors and a reference voltage source and turned on / off in association with a digital input signal. Each of the plurality of switches has a resistance value that is approximately ½ times each time the bit of the digital input signal is increased by one digit, and a plurality of switches that connect the connection nodes of the plurality of resistors and the reference voltage source through the plurality of switches. The wiring is formed so that the resistance value becomes approximately ½ times each time the bit of the digital input signal increases by one digit.

  According to this aspect, in the R-2R type digital-analog converter, the resistance value of the ladder network resistor network including the resistance of the switch and the wiring can be matched, so that the conversion accuracy can be improved. Here, “substantially ½” is intended to allow the case where the resistance value is not halved due to a variation in the resistance value due to process variations and the restriction of the resistance value due to a design rule such as a wiring width. It suffices if it is close to ½ within a range in which the accuracy required for the converter can be obtained.

The plurality of wirings connecting the connection nodes of the plurality of resistors and the reference voltage source are formed so that the wiring length is substantially the same, and the wiring width is approximately doubled every time the bit of the digital input signal is increased by one digit. May be.
By adjusting the resistance value of the wiring according to the wiring width, the size of the switch is proportional to the wiring width, so that the layout efficiency on the semiconductor integrated circuit can be increased. “Substantially the same” has the same meaning as “substantially 1/2” described above.

The plurality of wirings may be formed with the upper limit value when the wiring width reaches a predetermined upper limit value.
As the wiring width increases, the resistance value of the wiring decreases, so the influence on the accuracy of the digital-analog converter decreases. Therefore, by setting the upper limit value of the wiring determined based on the accuracy required for the digital-analog converter, it is possible to prevent the wiring width from being increased more than necessary and to reduce the area. In particular, as the number of bits of the digital input signal of the digital-to-analog converter increases, the wiring width increases, so an efficient design can be achieved by setting an upper limit value according to the accuracy required for the digital-to-analog converter. It can be performed.

Another aspect of the present invention is also a digital-to-analog converter. This digital-analog converter is a segment R-2R type digital-analog converter, and includes a ladder network resistor network to which a plurality of resistors are connected, a reference voltage source that supplies a reference voltage to a connection node of the plurality of resistors, and And a plurality of switches provided between connection nodes of the plurality of resistors and the reference voltage source and turned on / off in association with the digital input signal. The m switches whose on / off is controlled by the lower m bits of the digital input signal are formed such that the resistance value is approximately ½ times each time the bit of the digital input signal is increased by one digit, and A plurality of wirings connecting a connection node of a plurality of resistors and a reference voltage source through m switches are formed so that the resistance value is approximately ½ times each time the bit of the digital input signal is increased by one digit. On the other hand, the 2 ^n-1 switches whose ON / OFF is controlled by the upper n bits of data are formed so that their resistance values are substantially the same, and a plurality of switches are provided via the 2 ^n-1 switches. The plurality of wirings connecting the connection node of the resistor and the reference voltage source are formed so that their resistance values are substantially the same.

  According to this aspect, the resistance values of the switches and wirings corresponding to the segment type upper bits are set equal, and the resistance values of the switches and wirings corresponding to the lower bits of the R-2R type are approximately ½ for each bit. By setting the value twice, the resistance value of the ladder network resistor network including the switch and the wiring can be matched, so that the conversion accuracy can be improved.

A plurality of wirings connecting a connection node of a plurality of resistors and a reference voltage source via m switches are set to have substantially the same wiring width, and the wiring width is reduced every time the bit of the digital input signal is increased by one digit. On the other hand, a plurality of wirings that connect a connection node of a plurality of resistors and a reference voltage source via 2 ^n-1 switches are formed so as to be twice as long as the wiring width and the wiring length are substantially the same. May be formed.

Yet another embodiment of the present invention is a ΔΣ modulation type analog-digital converter. This ΔΣ modulation analog-digital converter integrates an input analog signal, an analog-digital converter that converts the output of the integrator into a digital value, and converts the output of the analog-digital converter into an analog value for integration. And the above-described R-2R type or segment R-2R type digital-to-analog converter for outputting to the device.
The digital-to-analog converter used in the ΔΣ modulation type analog-to-digital converter does not require a large number of bits, but high conversion accuracy is required. Therefore, the above-described R-2R type or segment R- A 2R type digital-analog converter can be used. As a result, current consumption can be reduced and the circuit scale can be reduced as compared with the case where a capacitance array type digital-analog converter is used.

Yet another embodiment of the present invention is a mobile communication terminal. This mobile communication terminal includes the above-described ΔΣ modulation type analog-digital converter.
By using the R-2R type and segment R-2R type digital / analog converters with low current consumption in the ΔΣ modulation type analog-digital converter, the current consumption of the mobile communication terminal can be reduced.

  Note that any combination of the above-described constituent elements and the constituent elements and expressions of the present invention replaced with each other among methods, apparatuses, systems, etc. are also effective as an aspect of the present invention.

  The D / A converter according to the present invention can improve conversion accuracy.

(First embodiment)
FIG. 1 is a circuit diagram showing a configuration of a D / A converter 100 according to the first embodiment of the present invention. In the following drawings, the same constituent elements are denoted by the same reference numerals, and redundant description will be omitted as appropriate.
The D / A converter 100 is an R-2R type D / A converter, which converts a 4-bit digital input signal into an analog output signal and outputs it from an output terminal 104.

  The D / A converter 100 includes a network resistor network 10, a switch SW, and a reference voltage source 20.

The network resistance network 10 is configured by connecting a plurality of resistors in a ladder shape. Between the ground terminal GND and the output terminal 104, three resistors whose resistance value is set to R, one resistor whose resistance value is set to 2R, and a switch SW0 are connected in series. The connection nodes ND1 to ND4 of the three resistors whose resistance values are set to R are connected to the reference voltage source 20 via the resistors whose resistance values are set to 2R and the switches SW1 to SW4.
The switch SW0 is a switch provided for resistance value matching. This switch SW0 is always on when performing the digital-analog conversion operation.

  The reference voltage source 20 outputs a reference voltage Vref, and applies the reference voltage Vref to the connection nodes ND1 to ND4 via the switches SW1 to SW4.

  Each of the switches SW1 to SW4 is a switch for connecting either the reference voltage source 20 or the ground terminal GND to each of the connection nodes ND1 to ND4, and ON / OFF is controlled according to each bit of the 4-bit digital input signal. The The switch SW1 corresponds to the least significant bit LSB (Least Significant Bit), and the switch SW4 corresponds to the most significant bit MSB (Most Significant Bit). These switches SW1 to SW4 are turned on to the reference voltage source 20 side when the bit value of the corresponding digital input signal is 1, and are turned on to the ground terminal GND side when the bit value is 0.

  For example, if the 4-bit digital input signal is 1111, all the switches SW1 to SW4 are connected to the reference voltage source 20 side. If 1101, the switches SW1, SW2, and SW4 are turned on to the reference voltage source 20 side. Only the switch SW3 is turned on to the ground terminal GND side.

  In the network resistance network 10, a resistance of 2R is connected to the lower side (not including the left side) and the left side of the connection node ND1. Therefore, the impedance viewed from the lower side (including the left side) of the connection node ND1 is a combined resistance R obtained by combining these resistances.

The impedance viewed from the lower side of the connection node ND2 is R + R = 2R because the combined resistance R and the resistance R between the connection nodes N1 and ND2 are combined in series. That is, the 2R resistor is connected to the connection node ND2 both on the lower side (not including the left side) and the left side. Accordingly, the impedance of the lower side (including the left side) of the connection node ND2 is also R.
Similarly, the impedance of the lower side (not including the left side) viewed from the connection node ND3 or ND4 is 2R.

  In this way, the R-2R type network resistor network 10 has the resistance value 2R and the resistance value 2R combined in parallel to become the resistance value R, and the resistance value R is combined in series with the resistance value R to become 2R again. It is comprised so that it may become.

  The impedance when the left side is viewed from the connection node ND4 is 2R, and the impedance when the lower side is viewed is also 2R. Therefore, when the switch SW4 is turned on to the reference voltage source 20, the output terminal 104 outputs Vref × 1/2.

  Next, the connection node ND3 will be examined. The impedance when the upper side is viewed from the connection node ND3 is 2R + R = 3R. The impedance when the lower side (not including the left side) is viewed from the connection node ND3 is 2R. Therefore, when the switch SW3 is turned on to the reference voltage source 20 side, Vref × 3/8 appears at the connection node ND3, and Vref × 3/8 × (2R / 3R) = Vref × 1 / from the output terminal 104. 4 is output.

  From the same calculation, Vref × 1/8 is output from the output terminal 104 when the switch SW2 is turned on to the reference voltage source 20, and from the output terminal 104 when the switch SW1 is turned on to the reference voltage source 20 side. Vref × 1/16 is output.

  Therefore, when each bit of the digital input signal is represented by b1 to b4, the analog output voltage Vout output from the output terminal 104 is Vout = Vref × (b4 × 1/2 + b3 × 1/4 + b2 × 1/8 + b1 × 1 / 16), and operates as a digital-to-analog converter.

FIG. 2 is an equivalent circuit diagram of the D / A converter 100 of FIG. 1 and illustrates resistance components.
When the switches SW0 to SW4 in FIG. 1 are configured with MOSFETs (Metal Oxide Field Effect Effect Transistors), the switches SW0 to SW4 have on-resistances ron0 to ron4 as resistance components.
Further, the wiring connecting the resistors R, 2R and the reference voltage source 20 via the switch SW also has a resistance component rw.
FIG. 2 shows the on-resistances ron0-ron4 and the wiring resistances rw0-rw4 of these switches SW0-SW4 together with the resistors R, 2R constituting the ladder network resistance network.

In the D / A converter 100 according to the present embodiment, the on-resistances ron1 to ron4 of the switches SW0 to SW4 are represented by the relational expressions ron0 = ron1 = rx, ron2 = rx / 2, ron3 = rx / 4, ron4 = rx / 8. Designed to meet. That is, the switches SW1 to SW4 are designed so that the resistance value ron is approximately ½ times each time the bit of the digital input signal is increased by one digit.
When the switches SW0 to SW4 are configured by MOSFETs, the on-resistances ron1 to ron4 can be adjusted by the transistor size, that is, the gate length and the gate width.

  Further, in the D / A converter 100 according to the present embodiment, the wiring resistances rw0 to rw4 connecting the resistors R and 2R and the reference voltage source 20 are also expressed by the relational expressions rw0 = rw1 = ry, rw2 = ry / 2. , Rw3 = ry / 4, rw4 = ry / 8. That is, the resistance values of the plurality of wirings connecting the connection nodes ND1 to ND4 of the plurality of resistors and the ground terminal or the reference voltage source 20 through the switches SW0 to SW4 have their resistance values every time the bit of the digital input signal increases by one digit. It is formed so as to be approximately ½ times.

FIG. 3 is a diagram showing an example of the layout of the D / A converter 100 of FIG. 2 on the semiconductor integrated circuit.
As shown in FIG. 3, the transistor size ratio of the switches SW0 to SW4 is set to 1: 1: 2: 4: 8, and the ratio of the on resistances ron0 to ron4 is 8: 4: 2: 1: 1. It is set to be.

In FIG. 3, W0 to W4 indicate wirings connecting the connection nodes ND1 to ND4 of the resistors and the ground terminal or the reference voltage source 20 through the switches SW0 to SW4, respectively.
As shown in FIG. 3, the wirings W0 to W4 are set so that the wiring lengths are substantially the same and the wiring width is 1: 1: 2: 4: 8. Therefore, the resistance values rw0 to rw4 of the wirings W0 to W4 are 8: 4: 2: 1: 1.

  Returning to FIG. 2, the accuracy of the D / A converter 100 configured as described above will be examined. When the ON resistances of the switches SW0 to SW4 and the resistance values of the wirings W0 to W4 are set as described above, the impedance viewed from the lower side from the connection node ND1 and the impedance viewed from the left side are both Rz1 = 2R + rx + ry. equal.

Next, the impedance of the lower side viewed from the connection node ND2 is Rz2 = R + Rz1 / 2 = 2 × R + (rx + ry) / 2, which is equal to the impedance viewed from the left side of the connection node ND2. Therefore, impedance matching is also achieved for the connection node ND2.
Furthermore, the impedance of the connection node ND3 viewed from the lower side is Rz3 = R + Rz2 / 2 = 2 × R + (rx + ry) / 4, which is equal to the impedance viewed from the left side.
Further, the impedance of the connection node ND4 viewed from the lower side is R + Rz3 / 2 = 2 × R + (rx + ry) / 8, which is equal to the impedance viewed from the left side.

  As described above, in the D / A converter 100 according to the present embodiment, the impedance of the network resistor network 10 is adjusted to include the resistance values of the switches SW0 to SW4 and the wirings W0 to W4, thereby providing a highly accurate ladder network. An R-2R type digital-analog converter having a resistor network can be formed, and high-precision digital-analog conversion is possible.

  For example, let us consider a case in which the resistance values of the resistors constituting the network resistor network 10 are R = 10 kΩ, 2R = 20 kΩ, and the on-resistance ron0 = rx = 500Ω of the switch SW0. If it is assumed that the resistance values rw0 to rw4 of the wirings W0 to W4 are all equal and about 10Ω, compared to the case where the wiring is ideally formed as in the D / A converter 100 according to the present embodiment, R An error of several Ω is generated in the matching of the 2R resistance. A mismatch of several Ω with respect to 10 kΩ means that a conversion error of about ΔV = Vfsr / 1000 occurs as the voltage error ΔV. Here, Vfsr represents a voltage corresponding to the full scale range. Since the error of Vfsr / 1000 corresponds to an error of about 1 LSB in a 10-bit (1024) digital-analog converter, it becomes a problem when higher-precision digital-analog conversion is required.

  According to the D / A converter 100 according to the present embodiment, since the resistances of R and 2R are matched including the wiring resistance, the error can be suppressed to be small. That is, when the resistance values rw0 to rw4 of the wirings W0 to W4 are set to 8: 4: 2: 1: 1, the resistance mismatch between R and 2R can be 1Ω or less. As a result, the D / A converter 100 having an accuracy of about 12 bits can be realized.

(Second Embodiment)
FIG. 4 is a circuit diagram showing a configuration of a D / A converter 200 according to the second embodiment. This D / A converter 200 is a segment R-2R type 4-bit digital-analog converter, and the upper 2 bits are constituted by the segment type and the lower 2 bits are constituted by the R-2R type.

  The D / A converter 200 includes a network resistor network 10, a switch SW, and a reference voltage source 20.

Between the ground terminal GND and the output terminal 104, a resistor having a resistance value set to R, a resistor having a resistance value set to 2R, and a switch SW0 are connected in series.
The connection nodes ND1 to ND5 are connected to the reference voltage source 20 via the resistors whose resistance values are set to R or 2R and the switches SW1 to SW5.

  The reference voltage source 20 outputs a reference voltage Vref, and applies the reference voltage Vref to the connection nodes ND1 to ND5 via the switches SW1 to SW5.

  Similarly to the first embodiment, the switch SW1 and the switch SW2 constitute an R-2R type digital-analog converter, and are turned on / off corresponding to the lower 2 bits.

In the D / A converter 200 according to the second embodiment, the three switches SW3 to SW5 are controlled based on the upper two bits of the digital input signal.
As described in the first embodiment, the impedance of the lower side (including the left side) viewed from the connection node ND2 is set to R. When attention is paid to the connection node ND5, the impedance when the lower side is viewed is R / 3.
Therefore, when the switch SW5 is turned on, Vout = Vref × 1/4 is output from the output terminal 104 as the output voltage Vout. The same applies to the switch SW4 and the switch SW3, and Vref / 4 is output as the output voltage Vout in the ON state.

  As a result, the output voltage Vout output from the output terminal 104 becomes Vout = Vref × (b5 × 1/4 + b4 × 1/4 + b3 × 1/4 + b2 × 1/8 + b1 × 1/16), and operates as a digital analog converter. To do. Here, b3 to b5 are data obtained by decomposing the upper 2 bits, and b2 and b1 represent the lower 2 bits.

FIG. 5 is an equivalent circuit diagram of the D / A converter 200 of FIG. 4 and illustrates resistance components.
FIG. 5 shows the on resistances ron0 to ron5 and the wiring resistances rw0 to rw5 of the switches SW0 to SW5 together with the resistors R and 2R constituting the ladder network resistor network.

  In the D / A converter 200 according to the present embodiment, the on-resistances ron0 to ron5 of the switches SW0 to SW5 satisfy the relational expressions ron0 = ron1 = rx, ron2 = rx / 2, and ron3 = ron4 = ron5 = rx / 4. Designed as such. That is, the region switches SW1 to SW2 configured by the R-2R type are designed so that the resistance value ron is approximately ½ times each time the bit of the digital input signal is increased by one digit. Further, for the switches SW3 to SW5 configured as segment types, all the on-resistances are set equal.

  Furthermore, in the D / A converter 200 according to the present embodiment, the wiring resistances rw0 to rw5 of the wirings connecting the resistors R and 2R and the reference voltage source 20 are also expressed by the relational expressions rw0 = rw1 = ry and rw2 = ry. / 2, rw3 = rw4 = rw5 = ry / 4. That is, the plurality of wirings connecting the connection nodes ND0 to ND5 of the plurality of resistors and the ground terminal or the reference voltage source 20 via the switches SW0 to SW5 are also designed to match the resistance values.

FIG. 6 is a diagram showing an example of the layout of the D / A converter 200 of FIG. 5 on the semiconductor integrated circuit.
As shown in FIG. 6, the transistor size ratio of the switches SW0 to SW5 is set to 1: 1: 2: 4: 4: 4, and the ratio of the on-resistances ron0 to ron5 is 4: 4: 4: 2: It is designed to be 1: 1.

In FIG. 6, W0 to W5 indicate wirings connecting the connection nodes ND1 to ND5 of the resistor and the ground terminal or the reference voltage source 20 through the switches SW0 to SW5, respectively.
As shown in FIG. 3, the wirings W0 to W5 are set to have the same wiring length and the wiring width is set to 1: 1: 2: 4: 4: 4. The resistance values rw0 to rw5 are also 4: 4: 4: 2: 1: 1.

  Returning to FIG. 5, the accuracy of the D / A converter 200 configured as described above will be examined. When the ON resistances of the switches SW0 to SW5 and the resistance values of the wirings W0 to W5 are set as described above, the impedance viewed from the lower side from the connection node ND1 and the impedance viewed from the left side are both Rz1 = 2R + rx + ry. equal. Further, the impedance viewed from the lower side and the impedance viewed from the left side from the connection node ND2 are both equal to Rz2 = 2R + (rx + ry) / 2.

Next, attention is focused on the portion formed by the segment type. The impedance when the lower side is viewed from the connection node ND3 is Rz2 / 2 = R + (rx + ry) / 2. Further, since the impedance viewed from the left side from the connection node ND3 is also R + rx / 4 + ry / 4, it is equal to the impedance viewed from the lower side.
The same applies to the connection nodes ND4 and ND5.

  As described above, in the D / A converter 200 according to the present embodiment, the impedance of the network resistor network 10 is adjusted with high accuracy by adjusting the impedance of the switches SW0 to SW5 and the wirings W0 to W5. A segmented R-2R type digital-to-analog converter can be constructed, and high-precision digital-to-analog conversion is possible.

(Third embodiment)
The third embodiment is a ΔΣ analog-to-digital converter using the R-2R type or segment R-2R type digital-analog converter described in the first and second embodiments.
FIG. 7 is a block diagram showing a configuration of the ΔΣ analog-digital converter.
The ΔΣ A / D converter 500 includes two blocks, a ΔΣ modulation circuit 520 and a decimation filter 530. The ΔΣ modulation circuit 520 includes an integrator 600, a D / A converter 610, and an A / D converter 620.

Such a ΔΣ modulation circuit 520 of the ΔΣ A / D converter 500 is required to have a digital / analog converter that operates with a low number of bits and high accuracy.
Since the D / A converter 200 according to the first and second embodiments can be used as a high-precision digital-to-analog converter with a low number of bits, as described above, the D / A inside the ΔΣ modulation circuit 520 can be used. Suitable for use as converter 610. For example, when the 4-bit D / A converters 100 and 200 according to the first and second embodiments are used in the 12-bit ΔΣ A / D converter 500, the ΔΣ A / D converter 500 as a whole realizes 12-bit accuracy. be able to.

  The D / A converters 100 and 200 according to the first and second embodiments are R-2R type and segment R-2R type digital-analog converters, so that active elements such as amplifiers are not required, and thus low power consumption. This has the advantage that the current and the circuit scale can be reduced. When the D / A converters 100 and 200 are used as the D / A converter 610 in the ΔΣ modulation circuit 520, the current consumption of the ΔΣ A / D converter 500 is reduced. In addition, the circuit scale can be reduced.

(Fourth embodiment)
The D / A converters 100 and 200 according to the first and second embodiments, and the ΔΣ A / D converter 500 according to the third embodiment using them are suitable for mobile communication terminal devices such as mobile phones. Can be used.
FIG. 8 is a block diagram showing a configuration of mobile communication terminal 800. The mobile communication terminal 800 includes a DSP 810, an analog front end circuit 820, an RF circuit 830, a power amplifier 840, a low noise amplifier 850, a duplexer 860, and an antenna 870.
The DSP 810 is a baseband circuit or the like, and is a block that performs various signal processing such as coding audio signals. The DSP 810 outputs a modulated signal IQd subjected to modulation such as CDMA modulation or GMSK modulation.
The analog front end circuit 820 A / D converts the modulation signal IQd output from the DSP 810 and outputs the result to the RF circuit 830. The RF circuit 830 mixes the analog modulation signal IQa output from the analog front end circuit 820 with the carrier frequency by a mixer, and converts it into a high frequency signal. The power amplifier 840 amplifies the high frequency signal, and the amplified high frequency signal is transmitted from the antenna 870 via the duplexer 860.

  The high frequency signal received from the antenna 870 is amplified by the low noise amplifier 850 and input to the RF circuit 830. The RF circuit 830 converts the received high frequency signal into a local frequency and outputs it to the analog front end circuit 820. The analog front-end circuit 820 performs analog-to-digital conversion on the received signal of the local frequency and outputs it to the DSP 810.

  Thus, the analog front end circuit 820 of the mobile communication terminal 800 performs both digital-analog conversion and analog-digital conversion. Therefore, the D / A converters 100 and 200 according to the first and second embodiments can be suitably used for a block that performs digital-analog conversion. Similarly, the ΔΣ A / D converter 500 according to the third embodiment can be used for a block that performs analog-digital conversion.

  Since the analog front-end circuit 820 often handles digital signals of about 12 bits, the 4-bit D / A converters 100 and 200 according to the first and second embodiments can be applied in many cases. As described above, since the D / A converters 100 and 200 consume less current, when used in the mobile communication terminal 800 driven by a battery, the driving time can be extended. Furthermore, since the D / A converters 100 and 200 need only have a small circuit scale, the mobile communication terminal 800 can be miniaturized.

  Those skilled in the art will understand that the above-described embodiment is an exemplification, and that various modifications can be made to combinations of the respective constituent elements and processing processes, and such modifications are also within the scope of the present invention. is there.

  For example, although a 4-bit D / A converter has been described in the embodiment, the present invention is not limited to this. For example, when a 6-bit D / A converter is configured as an R-2R type, the on-resistance of the switch SW may be set as ron5 = rx / 16, ron6 = rx / 32. Similarly, the wiring resistance may be rw5 = ry / 16 and rw6 = ry / 32. The same applies to the segment R-2R type.

  In the present embodiment, all elements constituting the D / A converter 100 may be integrated or may be divided into a plurality of integrated circuits. Which part is integrated may be determined by cost, occupied area, or the like.

1 is a circuit diagram showing a configuration of a D / A converter according to a first embodiment of the present invention. FIG. 2 is an equivalent circuit diagram of the D / A converter of FIG. 1. FIG. 3 is a diagram showing an example of a layout of the D / A converter of FIG. 2 on a semiconductor integrated circuit. It is a circuit diagram which shows the structure of the D / A converter which concerns on 2nd Embodiment. FIG. 5 is an equivalent circuit diagram of the D / A converter of FIG. 4. FIG. 6 is a diagram showing an example of the layout of the D / A converter of FIG. 5 on a semiconductor integrated circuit. It is a figure which shows the structure of a delta-sigma A / D converter. 2 is a block diagram showing a configuration of a mobile communication terminal 800. FIG.

Explanation of symbols

  10 network resistor network, 20 reference voltage source, SW switch, W wiring, 100 D / A converter, 200 D / A converter, ΔΣ A / D converter 500, mobile communication terminal 800.

Claims (5)

R-2R type digital-analog converter,
A ladder network resistor network to which a plurality of resistors are connected;
A reference voltage source for supplying a reference voltage to a connection node of the plurality of resistors;
A plurality of switches provided between a connection node of the plurality of resistors and the reference voltage source and turned on / off in association with a digital input signal;
Each of the plurality of switches has a resistance value approximately ½ times each time the bit of the digital input signal is increased by one digit, and the connection node of the plurality of resistors and the reference voltage source through the plurality of switches. Are formed such that each time the bit of the digital input signal increases by one digit, its resistance value is approximately ½ times .
The plurality of wirings connecting the connection nodes of the plurality of resistors and the reference voltage source have substantially the same wiring length, and the wiring width is approximately doubled every time the bit of the digital input signal is increased by one digit. A digital-to-analog converter characterized by being formed . 2. The digital-analog converter according to claim 1 , wherein the plurality of wirings are formed with an upper limit value when a wiring width reaches a predetermined upper limit value. 3. A segment R-2R type digital-analog converter,
A ladder network resistor network to which a plurality of resistors are connected;
A reference voltage source for supplying a reference voltage to a connection node of the plurality of resistors;
A plurality of switches provided between a connection node of the plurality of resistors and the reference voltage source and turned on / off in association with a digital input signal;
The m switches whose on / off is controlled by the lower m bits of the digital input signal are formed such that the resistance value is approximately ½ times each time the bit of the digital input signal is incremented by one digit, In addition, each of the plurality of wirings connecting the connection nodes of the plurality of resistors and the reference voltage source through the m switches has a resistance value approximately ½ times each time the bit of the digital input signal is increased by one digit. While being formed to be
The 2 ^n-1 switches whose on / off is controlled by upper n bits of data are formed so that their resistance values are substantially the same, and the plurality of resistors are connected via the 2 ^n-1 switches. The plurality of wirings connecting the connection node and the reference voltage source are formed so that their resistance values are substantially the same ,
The plurality of wirings connecting the connection nodes of the plurality of resistors and the reference voltage source through the m switches are set to have substantially the same wiring width, and each time the bit of the digital input signal increases by one digit, the wiring While formed to be approximately double the width,
The plurality of wirings connecting the connection nodes of the plurality of resistors and the reference voltage source via the 2 ^n-1 switches are formed so that the wiring width and the wiring length are substantially the same. Digital-to-analog converter. An integrator for integrating the input analog signal;
An analog-to-digital converter that converts the output of the integrator into a digital value;
The digital-to-analog converter according to any one of claims 1 to 3 , wherein an output of the analog-to-digital converter is converted into an analog value and output to the integrator.
A delta-sigma modulation analog-digital converter characterized by comprising: A mobile communication terminal comprising the ΔΣ modulation type analog-digital converter according to claim 4 .

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