JPH0461521A - Digital/analog converter - Google Patents

Abstract

PURPOSE:To maintain monotony of conversion without increasing an area occupied analog switches by decreasing the size of the analog switches of a D/A converter at a prescribed ration at each step transferring from a high-order bit to a low-order bit. CONSTITUTION:In each channel size of NMOS N0-N9, a channel length is all ln which is constant, and channel widths are respectively Wn0-Wn3. In each channel size of PMOS P0-P9, a channel length is all lp which is constant, and channel widths are respectively Wp0-Wp3. The size of analog switches is being decreased in a ratio of 1/sq. rt. 2 at each one step transferring from high-order bit to a low-order bit, and an ON resistance deltaN3P3 of the high-order bit N3, P3 is selected to be delta0. Then a difference from a change quantity error is considerably improved than the case with ON resistance set equal to each other. Moreover, the area of the analog switch section is reduced proportionally to the reduction in the channel width.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital-to-analog converter that converts a binary digital signal into an analog signal.

[Conventional technology]

FIG. 3 shows a circuit diagram of a conventionally used 4-bit voltage addition type R-2R digital-to-analog converter. In the figure, 1 is a first input terminal for inputting a first reference voltage, 2 is a second input terminal for inputting a second reference voltage, 3 is an output terminal for outputting a converted analog signal, 4a, 4b, 4c, and 4d are data input terminals to which original digital data to be converted from digital to analog is input.

Next, the operation will be explained.

This digital-to-analog converter has four N-channel type MO3 field effect transistors N0 to N, each of which constitutes an analog switch, and a P-channel type MO3 field effect transistor P0 for 4-bit digital data D0 to D. ~P is provided. N-channel MOS field effect transistor (hereinafter referred to as NMO3)
The input terminals of N, ~N3 are connected to the first input terminal 1 to which the reference voltage VrafL is applied, and the P-channel type MO3g
Field effect transistor (hereinafter referred to as PMO3) PG~P8
The input terminal of is connected to the second input terminal 2 to which the reference voltage V r*ru is applied. No of NMO3 and P of PMO3
o, N+ and Pl, Nt and P, and N, and P,
Four resistors each having a resistance value of 2R are connected to each output terminal.

Between the second input terminal 2 and the output terminal 3, one resistor having a resistance value of 2R and three resistors having a resistance value R are connected in series.

Then, a resistor network consisting of these resistors R and 2R and the above N-channel type MO3 field effect transistors N0 to N,
and P-channel MOS field effect transistor P0~
P, in response to N bits of digital data.
A voltage addition type R-2R digital-to-analog conversion circuit is configured to obtain an analog conversion signal by appropriately adding divided voltages of the voltage difference between the second reference potentials.

Binary digital data has a lower focus D.

is converted in parallel to the upper bit D. That is, the data input terminals 4a, 4 of this digital-to-analog converter
The analog switches NMO3 and PMO3 are driven depending on the state of the data input to b, 4c and 4d, respectively, and an analog signal corresponding to the digital signal is output to the output terminal 3.
It is output from

That is, only one of the NMO3 and PMO3 is turned on depending on the data input, and NMOSN0 and PMO3 are turned on depending on the data input.
P is two reference voltages ■1. ．． It is switched whether or not to generate a divided voltage of 1/24 of the differential voltage V d L f between υ and V rafL.

Hereafter, it is switched whether or not to generate a divided voltage that is twice as large for each bit, and NMOSN and PMO3
Pi is 2'/2' (=1
/2) Switch whether or not to generate twice the divided voltage. Therefore, from the output terminal 3, the above 1/2', ..., 1/
An analog signal is obtained in which divided voltages weighted by 2 are added according to each bit of data.

FIG. 2 is a diagram showing a pattern image of a conventional analog switch section based on the circuit diagram of FIG. ln and PMO3
The channel sizes of P0 to P are channel width wp, channel length lp, and all analog switches of the same size were used.

Here, the change amount error δ at the four points A, B, C, and D
v,, δVm+ δvc, δv0 are the ON resistance of the analog switch as δIf+IFY, δNIFl+δ, respectively.
□, □, δ. . Then, the following relationship holds true.

However, δ. −δ8°,. =δN1□=δN□, =68. Since P3, δV, = 0.56°, δV++ = 0.75δ
. , δVc=1.3756°, δ■. =2.68756
It becomes ゜.

[Problem to be solved by the invention]

The analog switch section of the conventional voltage addition type R-2R digital-to-analog converter has the circuit configuration as described above, and the channel size is the same regardless of whether it is upper or lower, so there is no difference in ON resistance. Therefore, the higher the bit, the larger the error. Therefore, in order to maintain the monotonicity of conversion, it is necessary to use a large analog switch, but this poses problems such as the need to lower the ON resistance.

This invention was made to solve the above-mentioned problems.
The purpose of the present invention is to obtain a digital-to-analog converter that can obtain uniform error accuracy regardless of lower bits and maintain monotony of conversion.

[Means to solve the problem]

The digital-to-analog converter according to the present invention is configured such that the analog switch is made smaller by a certain predetermined ratio for each stage transition from the upper bit side to the lower bit side, and the ON resistance of each is made to be the reciprocal of the analog switch. It is something.

[Effect]

In the digital-to-analog converter according to the present invention, by having the above-mentioned configuration, the output of the analog switch is
Since the digital-to-analog conversion error caused by the N resistance is independent of the upper and lower order, digital-to-analog conversion performance that maintains monotonicity can be obtained without occupying a large amount of analog switch size.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a pattern image of an analog switch section of a 4-bit digital-to-analog converter according to an embodiment of the present invention. In FIG. 0, 1 is a first input terminal, 2 is a second input terminal, 3 is the output terminal, 4a, 4b, 4
c, 4d are data input terminals, N0 to N, and P0 to P
, are NMO3 and PMO3, respectively, which constitute an analog switch.

Next, the operation will be explained.

The channel sizes of N0 to N of NMO3 that constitute the analog switch of this digital-to-analog converter are all constant at in, and the channel widths are W7゜+WllI+W,,,W,! It is. Furthermore, the channel sizes of P0 to P of PMO3 are all fixed at ip, and the channel widths are W, respectively. ,W,,,W,,,W,,. If we assume that the size of the analog switch is reduced by a ratio of 1/, /7 every time we move from the upper bit to the lower bit, then W7゜= i in −w,, t, W1= 1i(τ・
LttwRz=1/(7-w,,,W,,=1/7
T-w...

Wp, = 1/7 wt, wt = 1/(τ Wl
becomes. Therefore, the upper bit N, and the ON resistance δ of P3. . , δoF, −δ. Then, each set of N
The ON resistances of o and P, ,N, and P, ,N, and Pt are respectively δHopo−Fdδ□28. δNIPl=flδN! p
HδN Z P 2−rYδN3P! =4]δ.

That is, δ8゜. =2(τδ., δ□□=2δ..

δN! P! = r ding δ.

becomes.

Therefore, the variation errors δVA, δ at points A, B, C, and D
■6. From equation (1), δVc and δV are (4-fl)
δ.

ζ1.29δ.

= (7fl-4) δo 'i1.47
6°1 (2B-7fl) δ.

’-i2.　266゜ becomes.

Therefore, the difference in variation errors is considerably improved compared to when the ON resistances of the analog switches are all equal.

Furthermore, since the channel lengths are the same, the area of the analog switch section becomes smaller as the channel width becomes smaller.

In the above embodiment, each analog switch has NM.
Although O3 and PMO3 are used, a transmission gate type analog switch may also be used.

Further, in the above embodiment, a 4-bit data has been described, but it goes without saying that the data is not limited to this.

〔Effect of the invention〕

As described above, according to the present invention, the size of the analog switch of the digital-to-analog converter is reduced by a predetermined ratio each time it moves from the upper bit side to the lower bit side. This has the effect of maintaining monotony of conversion without increasing the occupied area.

[Brief explanation of drawings]

FIG. 1 is a pattern image diagram of an analog switch section of a 4-bit voltage addition type R-2R digital-analog converter according to an embodiment of the present invention, FIG. 2 is a pattern image diagram of a conventional pattern, and FIG. 3 is a conventional digital-analog converter. FIG. 2 is a circuit diagram of a converter. In the figure, 1 is the first input terminal, 2 is the second input terminal, 3
are output terminals, 4a, 4b, 4c, and 4d are data input terminals, P0 to P8 are PMO3, N, and .about.N are NMO3. Note that the same reference numerals in the figures indicate the same or equivalent parts. Sorry]. 2゜3゜4゜Procedural Amendment (Voluntary) November 1990/Japan Related Patent Applicant Address 2-2-3 Marunouchi, Chiyoda-ku, Tokyo Name (601) Mitsubishi Electric Corporation Representative Moriya Shiki

Claims (1)

[Claims] (1) First and second depending on N-bit digital data.
The voltage addition method R-2, R digital converter which obtains an analog conversion signal by appropriately adding the divided voltages of the difference voltage between the reference potentials of
In a digital-to-analog converter that includes an analog conversion circuit and converts an N-bit binary digital signal into an analog signal, MOS field effect transistors forming the N analog switches provided in the digital-to-analog conversion circuit are provided. A digital-to-analog converter characterized in that it has a channel width that is reduced by a predetermined ratio each time it moves from the upper bit side to the lower bit side.