JP2682940B2 - Output circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a complementary MOS (hereinafter referred to as "C
(Referred to as “MOS”) integrated circuit.

[0002]

2. Description of the Related Art Output circuits in CMOS integrated circuits are
A CMOS transistor having a large gate width, that is, a large size is used in the final stage because it plays a role of driving another circuit by transmitting a signal over a long distance. FIG.
FIG. 6 is a diagram showing a final stage CMOS transistor of the output circuit.

When the input signals S ₁ and S ₂ of the CMOS transistor 10 change, the CMOS transistor 10 is configured to have a P-type transistor 11 and an N-type transistor 1.
When a through current I flowing through 2 is generated, the through current I has an extremely large rate of change dI / dt, which affects the power supply system as noise, which is one of the causes of malfunction and the like.

FIG. 4 shows a first method for preventing this shoot-through current.
It is the timing chart which showed one. CM shown in FIG.
P-type transistor 11 forming the OS transistor 10
The input signal S ₁ of the input signal S _{2 and} the timing of the input signal S ₂ of the N-type transistor 12 are shifted as shown in FIG.
By creating the moment when both the P-type transistor 11 and the N-type transistor 12 are turned off when the signal changes,
Generation of the through current I is prevented.

The signal output line 13 shown in FIG.
This CMOS transistor has a large load capacity 14.
Input signal S of the register 10₁ , S_Two Is larger each time
Charging current i₁ , Or discharge current i_Two Flow through them
Change rate di₁ / Dt, di _Two Since / dt is also large, this
This is also one of the causes of malfunctions that affect the power supply system as noise.
Becomes

FIG. 5 shows the rate of change di of the charging / discharging currents i ₁ and i _2.
1 / dt, which is a diagram showing one conventional proposal to suppress the di ₂ / dt (see JP-A-61-283217). The input signal S is divided into a plurality of systems (two systems in this example), the delay amount is sequentially changed, the output sides are connected to each other, and the load capacitance 14 is charged and discharged. By doing so, the intent of this proposal is to distribute the charging and discharging currents in time,
It is considered to be to suppress the rate of change of them to be small. However, in this circuit, there is a moment when one of the two output drivers 15 and 16 becomes H level and the other becomes L level when the input signal S changes, and at that moment, current flows from one to the other. This is not a realistic circuit.

FIG. 6 is a diagram showing another conventional proposal for suppressing the rate of change of discharge current (see the above publication). This figure 6
The idea for suppressing the rate of change of the discharge current in is similar to that shown in FIG. 5, the input signal S is divided into a plurality of systems (two systems in this example), and the delay amount is sequentially changed to the output side. Are connected to each other to discharge the electric charge accumulated in the load capacitance 14. This causes the discharge current to be dispersed over time,
The rate of change can be kept small.

[0008]

In order to realize both prevention of shoot-through current and suppression of change rate of charging / discharging current in constructing an output circuit, the method shown in FIG. 4 and FIGS. It is conceivable to incorporate both of the methods shown in 6. That is, a plurality of CMOS transistors 10 as shown in FIG. 3 are arranged and their outputs are connected to each other to drive the load capacitance 14, and originally, one input is equal to the number of arranged CMOS transistors 10. Two
It is conceivable that each CMOS transistor 10 is divided into two, and each of the branched inputs is connected to a delay circuit (see FIG. 6) in which the number of inverters is changed so that the delay times are different from each other. . However, in this case, there is a problem that the number of inverters forming the delay circuit becomes considerably large and the area occupied by the output circuit becomes large.

In view of the above circumstances, it is an object of the present invention to provide an output circuit which realizes both prevention of shoot-through current and reduction of change rate of charge / discharge current with a relatively small circuit scale.

[0010]

SUMMARY OF THE INVENTION An output circuit of the present invention for achieving the above object is a P-type MOS transistor and an N-type MOS.
A drive circuit which is composed of a plurality of complementary MOS transistors in which respective sources of the transistors are connected to a power supply and a ground and respective drains are connected to each other, and the outputs are connected to each other, and the outputs are connected to each other,
The input terminals are connected to each other and the output terminals are
Each of the complementary MO transistors includes a drive timing control circuit including a plurality of inverters connected to the gates of the P-type MOS transistors and the N-type MOS transistors that form the plurality of complementary MOS transistors.
The logical threshold value of the inverter connected to the gate of the P-type MOS transistor forming the S transistor is more than the logical threshold value of the inverter connected to the gate of the N-type MOS transistor forming the complementary MOS transistor. It is characterized in that it is high and the logical thresholds of the plurality of inverters constituting the drive timing control circuit are different from each other.

[0011]

The input signal does not undergo a complete step change, but changes gradually over a short period of time. In particular, in the case of the output circuit, as described above, a large-sized transistor is used in the final stage, and this large-sized transistor is driven by the small-sized transistor in the preceding stage. Becomes loose. The present invention has been completed by reaching this point.

That is, the output circuit of the present invention is configured so that each CMO
P-type MOS transistor forming an S transistor, N
Inverters are connected to the respective gates of the MOS transistor, and the inverters having different threshold values are used, so that the through current is prevented and the charging / discharging current is dispersed over time, and its change The rate is suppressed.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described below with reference to FIG.
FIG. 4 is a diagram showing an embodiment of an output circuit of the present invention. This output circuit comprises three CMOS transistors 20, 3
0, 40 drive circuit and P-type MOS transistor 2 constituting each CMOS transistor 20, 30, 40
1, 31, 41 and N-type MOS transistors 22, 3
The drive timing control circuit is composed of six inverters 51, 52, 53, 54, 55, 56 connected to the respective gates of 2, 42.

The sources of the P-type MOS transistors 21, 31, 41 of the three CMOS transistors 20, 30, 40 constituting the drive circuit are connected to the power source, and the N-type MOS transistors 22, 32, 42 are also connected. Source is connected to ground. Further, the drains of the P-type MOS transistors 21, 31, 41 and the drains of the N-type MOS transistors 22, 32, 42, which form the CMOS transistors 20, 30, 40, respectively, are CMOS.
Each transistor 20, 30, 40 and their CMO
The S transistors 20, 30, 40 are connected to each other and form the output terminal of this output circuit. The input terminals of the inverters 51, 52, 53, 54, 55 and 56 are connected to each other and form the input terminal of this output circuit.

FIG. 2 is a diagram showing the input signal waveform of the output circuit shown in FIG. 1 and the threshold value of each inverter. Logic thresholds Th51, Th52, Th53, Th54, Th of the inverters 51, 52, 53, 54, 55, 56.
55 and Th56 are different from each other as shown in the figure. Moreover, regarding each of the CMOS transistors 20, 30, and 40, for example, the logical threshold value of the inverter 53 connected to the P-type MOS transistor 21 forming the CMOS transistor 20 is shown. Th53 has the same CMOS
It is higher than the logical threshold value Th54 of the inverter 54 connected to the N-type MOS transistor 22 that forms the transistor. Further, the rising and falling of the input signal S are gentle to some extent, and therefore each inverter 5
The times at which the outputs of 1, 52, 53, 54, 55 and 56 are inverted are different from each other as shown in the figure. Therefore, when the input signal S changes, the P-type MOS transistors 21, 31, 41 and the N-type MOS transistors 22, 3 which form the CMOS transistors 20, 30, 40, respectively.
The generation of the shoot-through current is prevented by passing through the moment when both of the Nos. 2 and 42 are turned off. Further, temporal distribution of charge / discharge current is also realized. As a result, malfunction due to noise is prevented, and a highly reliable circuit is realized.

In the above embodiment, each inverter 5
1, 52, 53, 54, 55 and 56 are the logical threshold values Th51, Th52, Th53, Th54 and T in this order.
Higher h55 and Th56 are used, but the order is not limited to this order, and the above-mentioned (1) Each inverter 51, 52, 53, 54, 55, 5 is used.
The logic thresholds of 6 are different from each other (2) P-type MOS transistors 21, 31, 41 forming the respective CMOS transistors 20, 30, 40
The inverters 51, 52, 53 connected to the inverter are connected to the inverters 54, 55, 56 connected to the N-type MOS transistors 22, 32, 42 constituting the same CMOS transistors 20, 30, 40, respectively. High and low logic thresholds may be interchanged within a range that satisfies the two requirements of high logic thresholds.

In the above embodiment, the drive circuit is provided with three Cs.
Although the MOS transistors 20, 30, 40 are provided, it goes without saying that the drive circuit constituting the output circuit of the present invention is not limited to the one constituted by the three CMOS transistors 20, 30, 40. .

[0018]

As described above, in the output circuit of the present invention, the logical threshold value of the inverter connected to the gate of the P-type MOS transistor forming the CMOS transistor is the N-type forming the CMOS transistor. MOS
This is higher than the logic threshold of the inverter connected to the gate of the transistor, and the logic thresholds of the inverters that make up the drive timing control circuit are different from each other. Both reduction of the rate of change of the discharge current is achieved. As a result, generation of noise is suppressed, and a highly reliable semiconductor integrated circuit is realized.

[Brief description of the drawings]

FIG. 1 is a diagram showing an embodiment of an output circuit of the present invention.

FIG. 2 is a diagram showing input signal waveforms of the output circuit shown in FIG. 1 and threshold values of respective inverters.

FIG. 3 is a diagram showing a final stage CMOS transistor of the output circuit.

FIG. 4 is a timing chart showing one method of preventing a shoot-through current.

FIG. 5 is a diagram showing one of conventional proposals for suppressing the rate of change of charge / discharge current.

FIG. 6 is a diagram showing another conventional proposal for suppressing the rate of change of discharge current.

[Explanation of symbols]

 14 load capacitance 20, 30, 40 CMOS transistor 21, 31, 41 P-type MOS transistor 22, 32, 42 N-type MOS transistor 51, 52, 53, 54, 55, 56 Inverter

 ─────────────────────────────────────────────────── --- Continuation of the front page (56) References JP-A 61-167220 (JP, A) JP-A 2-122726 (JP, A) JP-A 62-48806 (JP, A) JP-A 4- 248713 (JP, A) JP 60-224328 (JP, A) JP 60-128715 (JP, A)

Claims (1)

(57) [Claims] 1. A source of a P-type MOS transistor and a source of an N-type MOS transistor are connected to a power source and a ground, respectively, and respective drains are connected to each other, and the outputs are connected to each other with the connection point as an output. A drive circuit including a plurality of complementary MOS transistors and input terminals thereof are connected to each other, and an output terminal of each of the P-type MOS transistors and the N-type MOS transistors constituting the plurality of complementary MOS transistors, respectively. A drive timing control circuit including a plurality of inverters connected to respective gates, and a P-type MOS forming each of the complementary MOS transistors
The logic threshold value of the inverter connected to the gate of the transistor is higher than the logic threshold value of the inverter connected to the gate of the N-type MOS transistor forming each complementary MOS transistor, and the drive timing An output circuit characterized in that a plurality of inverters constituting a control circuit have different logic threshold values.