JPH03245612A

JPH03245612A - D/a converter

Info

Publication number: JPH03245612A
Application number: JP4308290A
Authority: JP
Inventors: Kenji Suzuki; 謙二鈴木; Yasuhiro Yamada; 康裕山田
Original assignee: Sanyo Electric Co Ltd
Current assignee: Sanyo Electric Co Ltd
Priority date: 1990-02-23
Filing date: 1990-02-23
Publication date: 1991-11-01
Anticipated expiration: 2011-03-21
Also published as: JPH0828661B2

Abstract

PURPOSE:To improve the linearity of an output with respect to an input data by putting an output terminal into a high impedance period at the start or end of each conversion period, and including said period within a period except a period when a digital data is inputted to a serial/parallel conversion circuit. CONSTITUTION:When the conversion of one data is finished, a gate circuit 24 turns off both of switching transistors(TRs) 25a, 25b to make its output terminal to high impedance for a prescribed period TZ. This high impedance period TZ is set to a period other than that when a digital data DS is fetched in an SIPO register 4 and no change is caused in the input data for a high impedance period TZ. Thus, the level at the output terminal is kept to a level just before the high impedance period TZ. Then the level at the output terminal for the high impedance period is kept equal, the superimposition of an error onto an output level is suppressed and the reduction in the linearity is prevented.

Description

【発明の詳細な説明】（イ）産業上の利用分野本発明は、デジタルデータを音声信号等のアナログデー
タに変換するＤ／Ａ　（デジタル／アナログ）変換器に
関する。DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a D/A (digital/analog) converter that converts digital data into analog data such as audio signals.

（ロ）従来の技術一般的なり／Ａ変換器としては、振幅変調（ＡＭ）方式
とパルス幅変調（ＰＷＭ）方式とがあげられる。ＡＭ方
式は、高精度の抵抗列で分圧した基準電位をデジタルデ
ータに従って選択して出力するように構成されており、
高速で正確な動作が可能な反面、回路規模が大きくなる
という欠点を有している。一方ＰＷＭ方式は、一定周期
のクロックをカウントする計数回路の出力をデジタルデ
ータに従って合成するもので、高精度の抵抗列を必要と
せず回路規模は小さくできるが、高速動作には適さず、
高調波歪が大きいという欠点を有している。(b) Prior Art Conventional A/A converters include the amplitude modulation (AM) method and the pulse width modulation (PWM) method. The AM method is configured to select and output a reference potential divided by a high-precision resistor string according to digital data.
Although it is capable of high-speed and accurate operation, it has the disadvantage of increasing the circuit scale. On the other hand, the PWM method synthesizes the output of a counting circuit that counts clocks with a fixed period according to digital data, and although it does not require a high-precision resistor string and can reduce the circuit scale, it is not suitable for high-speed operation.
It has the disadvantage of high harmonic distortion.

Claims

[Claims]

(1) A serial/parallel conversion circuit that receives digital data arranged at regular intervals in units of K bits (K is an integer) in time series and outputs K bits of digital data in parallel; the output of this conversion circuit. A latch circuit that latches digital data every predetermined period, N bits (N is K
a binary counting circuit (the following integer); a pulse number corresponding to the N-bit digital data from the output data of the counting circuit based on N-bit digital data of the K-bit digital data latched in the latch circuit; a pulse forming circuit for synthesizing pulse signals having in each conversion period a switching circuit for selecting either one of the first and second reference potentials according to the pulse signal; a gate circuit that provides a period in which the output terminal is in a high impedance state without selecting any of the above, and forms the high impedance period at the beginning or end of each conversion period, and this high impedance period is in the serial/ A D/A converter, characterized in that the D/A converter is stored within a period excluding a period during which digital data is input to a parallel conversion circuit.

(2) a decoder that decodes the upper bits of the N-bit digital data applied to the pulse forming circuit; a voltage divider circuit that divides the voltage between the first potential and the second potential using a plurality of series resistors; a switching circuit that selectively takes out two nearby potentials according to the output of the decoder from the voltage circuit, and provides the two nearby potentials taken out to the switching circuit as first and second reference potentials of the switching circuit. The D/A converter according to claim 1, characterized in that:

(3) first and second resistor networks respectively provided at both ends of the voltage dividing circuit; a level shift circuit that varies the resistance value while maintaining the total sum, and first and second potentials are applied to the voltage divider circuit via the first and second resistor networks. The D/A converter according to item 2.