SU809549A1 - Digital-analogue converter with automatic correction of non-linearity - Google Patents

Description

(54) DIGITAL CONVERTER

WITH AUTOMATIC CORRECTION OF NONLINEARITY

neither in the phase detector and the analog storage elements of high-capacity capacitors.

The purpose of the invention is to increase the speed of the converter and improve the manufacturability of its manufacture.

The goal is achieved by the NTO in a digital-to-analog converter with automatic nonlinearity correction containing a chain current divider, a DC generator and a controlled current generator, the outputs of which are connected to the information inputs of current switches, the first outputs of which are connected to the inputs of the chain current divider, and the second - . common bus, control unit and analog storage elements, the outputs of which are connected to the inputs of controlled current generators, include a shift register, an additional analog storage element, an operational amplifier with a differential input, the first group of elements OR, the second group of elements OR elements and the number of bits of the converter, with the outputs of each previous one of the first group of elements OR connected to the first input of the next, and the first of them has the inputs combined, the outputs of all the elements OR in the second group and one element I are connected to the control inputs of the current switches, the first inputs of the elements OR of the second group are connected to the outputs of the control unit code to be converted, the second inputs to the outputs of the AND elements, and the third to the outputs of the Ban elements and the control inputs of the analog storage elements informational inputs of which are connected to the output of an operational amplifier with a differential input, the non-inverting input of which is connected to the output of the circuit current divider, and the inverting input is additionally connected to the output Analog storage element, output, sync pulses of the control unit are connected to the first inputs of the R and Ban elements, a control input of the additional analog storage element and the shift register synchronization input, the information input of which is connected to the output of the control unit and the outputs to the second inputs of the Ban elements and the second inputs elements OR of the first group, the second outputs of which are connected to the second inputs of elements I.

The drawing shows a block diagram of the proposed device.

A digital-to-analog converter with automatic nonlinearity correction contains a chain current divider 1, the inputs of which are connected to the outputs of switches 2 of the current of working bits and switch 3 of the current of the reference discharge, the second outputs of which are connected to the common bus, the control inputs of switches of the 2nd outputs of the OR 4 elements switch 3 output element And 5, the information inputs of the switches 2 working bits connected to the outputs of the controlled current generators 6, and the switch input 3 reference bits - with the output of the generator DC 7 Current The inputs of the controlled direct current generators 6 are connected to the outputs of the analog storage elements 8, the information inputs connected to the output of the differential operational amplifier 9 and the control inputs to the outputs of the 10 inhibit, the non-inverting input of the amplifier 9 is connected to the output chain divider 1 current, and inverting - with the output of additional analog storage element 11, the information input of which is connected to the output of the operational amplifier 9, and the control one - with the output of Inputs (s) of control unit 12 and synchronization input from shift register 13. The information input of the shift register 13 is connected to the output of the control unit 12. The outputs Bp, B, ... Vt of the shift register 13 are connected to the first inputs of the chain of elements OR 14, the second input of each of which is connected to the output of the next, and both inputs of the first element OR 14 are connected to each other The first inputs of the elements 15 and 15 10 The ban is connected to the SI output of the control unit 12. The second inputs of elements 10 of the Inhibit are connected to the outputs B (j, B, ... Vts of the shift register 13, and the second inputs of the And 15 elements are connected to the outputs of the OR 14 elements. The outputs of the 10 Ban elements and the And 15 elements are connected in pairs with the first and second the inputs of the elements OR 4, the third inputs of which are connected to the outputs of the control unit 12, they receive the converted code

AP, A,

.AL

about f 1 and

All elements of the device are widely known. Control unit 12 may be regenerated as a generator and pulse distributor. The concatenated pulse distributor circuit is determined by the application area of the DAC.

The device works as follows.

There are two modes of correction and conversion. In the correction mode, the control unit 12 stops issuing the converted codes, and the voltages corresponding to a logical zero are set at the corresponding outputs.

At the same time, at the output of the control unit 12, connected to the information input D of the shift register 13, a pulse appears, setting the low-order bit of the shift register 13 to one state. The correction cycle takes N clock cycles (N DAC bit width). At each clock cycle, the unit recorded in the shift register 13 is shifted by one bit towards the higher bits.

In the first correction cycle, as long as the sync pulse exists, signals corresponding to a logical unit are present at the outputs of the last cell of the OR 14 circuit and the first element AND 5. The current of the DC generator 7 is fed to the input of the current divider 1 and the voltage is allowed to be written additional analog storage element 11. At the output of the element 11, due to deep negative feedback, a voltage is established through the operational amplifier with a differential input.

J doKo + e) ..

where I o is the current of the direct current generator; Q Q - transfer coefficient

a current generator of direct current at the output E of the divider having a dimension of resistance; K and gains

operational, amplifier for inverting and non-inverting inputs, respectively;

e is the bias emf of the opamp.

After the termination of the sync pulse, the DC generator 7 is disconnected from the input of the circuit divider 1 current. Signals corresponding to the logical unit occur at the outputs of the element 10 of the Ban and the element. OR 4 corresponding to the lower bit of the DAC and on the control input of the analog memory element 8 connected to the generator 6 of the current of this bit.

Due to the deep negative feedback, the voltage on the analogue element of the low-order bit 8 is set, reducing the voltage imbalance at the inputs of the operational amplifier 9 to zero.

Ыых i.K U v «4- / --e

where K is the transfer rate of the low-order current to the output of the chain splitter 1. Thus, the voltage generated at the output of the DAC by the generator

The current of the second discharge becomes equal to the voltage generated by the DC generator 7.

Similarly, each successive i-OM correction cycle during the existence of a clock pulse at the output of the control unit 12 in the additional analog storage element 11 stores a voltage equal to the EMF of the operational amplifier and nonidentity

0 its transmission coefficients for different inputs) the sum of the weighting factors of all the lower i-1 bits and the reference one. And after the sync pulse expires, the analogue storage element 8 of the i-th bit sets such a voltage that

2-to-ko

And i) -KJ IO-KO

20

At the same time, errors caused by EMF bias and nonidentity of the transmission coefficients for different inputs of the operational amplifier in each

5 bars compensated.

After N cycles of correction, currents in all bits are set such that the weights of each bit are proportional to

0 integer two.

Control unit 12 automatically enters conversion mode. In this case, the outputs of block 12 control-. Lenin received codes to be

5 decoding. Through the elements of OR 4, these codes arrive at the control inputs of the current switches 2. The voltage at the output of the circuit divider 1 current in this case is proportional to the number

0 represented by input position binary code

n -1 x OCi-2,

one

about

H

where afi 0 or 1 is the i-ro value of the code being converted. Thus, the linearity of the conversion is ensured, regardless of the specific characteristics (in particular, of the manufacturing accuracy) of the current generators, current switches, and chain current divider.

The scale of the transformation is not stabilized in this case; for this, known nodes of automatic correction of the scale of the transformation can be applied.

Thus, the proposed device provides high accuracy of conversion without significant requirements to the accuracy of manufacturing circuit elements.

Unlike known devices, it does not require multiple alternation of key states when correcting each bit. yes and filtering

pulse signals in the phase detector, which significantly (50-100 times) reduces the required correction time. .

An additional effect that the proposed device provides is the reduction of the required capacitance values in analogue storage elements and phase detectors, which provides an opportunity for the integrated realization of the device.

Claims (2)

1. The author's certificate of the USSR № 349099, cl. H 03 K 13/00, 07.25.72 2. Microelectronic encoding and decoding converters. Ed. Smolova V.B. L., Energie, 1976 (prototype),