JPS63260242A - Serial/parallel converter - Google Patents

Abstract

PURPOSE:To eliminate the need for a reset signal from a microcomputer by sending a data from the microcomputer with bit constitution more than a data bit number by one bit. CONSTITUTION:Inverted 8-bit data 0-7 are consecutive in a data from the head of a start bit. In detecting the change point of the start bit, a gate G1 resets a FF 3 and clears a shift register 1. As a result, an output (inverted signal of data) of an inverted gate G3 is fetched sequentially from an input terminal Si of a shift register 1. Then the start bit reaching the final bit Q9 is inverted by an inversion gate G4 to set the FF 3 at the trailing and to close a clock input gate G2 and latches data outputs Q1-Q8 to a D latch 2. Since the register 1 and the FF3 are reset by the start bit in this way, no reset signal is required.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] A circuit that takes in serial data of N bits following a start bit into a shift register and converts it into parallel output is configured without requiring a counter for counting the number of bits of serial data.

[Industrial application field]

The present invention relates to a serial/parallel converter that converts serial data to parallel data.

[Conventional technology]

Devices using microcomputers (hereinafter referred to as microcomputers) exchange data using serial communication in order to make effective use of the limited number of ports (increasing the number of ports increases the number of pins, which increases costs). Sometimes.

Since the serial communication function of such microcontrollers is intelligent, it is convenient for microcontrollers or ICs that have communication functions in the microcontroller family, but general KCS such as TTL and C-MOS LOGi
In C, this is treated as a start bit (5TA in Figure 3) indicating the beginning of data and a stop bit (5T in Figure 3) indicating the end of data, in addition to the original data.
This is because P).

In order to receive serial data from a microcomputer with the above-mentioned general iC, a serial/parallel (abbreviated as S/P) converter as shown in FIG. 2 is required. This S/P converter includes a shift register 11 that converts serial data DATA sent from a microcomputer in synchronization with a clock CLOCK into parallel data, and the number of bits N (in this example, N =8)
Counter 1 that counts and controls the opening and closing of the switch SW
Consists of 2. This counter 12 is cleared by the reset signal RESET from the microcomputer, and the subsequent clock CL
Count OCK. The microcomputer presses D after RESET.
Since ATA is output, when the counter 12 counts 9, 8 bits of data are taken into the shift register 11 (the first start bit STA is shifted out).
. At this time, the counter 12 opens the switch SW to prohibit clocking to the shift register 11, and holds the internal data.

[Problem that the invention seeks to solve]

The S/P converter shown in Figure 2 requires a counter 12, which requires a large number of parts.Also, the microcontroller must issue a reset signal RESET, which requires the use of additional ports and complicates the software. There are drawbacks.

The present invention aims to provide an S/P converter that can operate without a reset signal from a microcomputer and does not require a counter.

[Means for solving problems]

The present invention includes a gate (G1) that clears an (N+1)-bit shift register that receives N-bit serial data that is input in synchronization with a clock, a gate (G2) that inputs a clock to the shift register, and a gate (G2) that inputs a clock to the shift register. Gate (G1
), the gate (G
2) is enabled.

[Effect]

In the present invention, the shift register is configured with one bit more than the number of data bits (N+1), thereby omitting the conventional counter, and detecting the beginning of data from the start bit, thereby eliminating the need for a reset signal from the microcomputer.

〔Example〕

FIG. 1 is a block diagram showing one embodiment of the present invention, where 1 is (N+
1) Bit (N=8 in this example) shift register, 2 is N-bit D latch, 3 is R-3 type flip-flop, G1 is OR gate for start bit detection, G2 is AND gate for clock input , G3 is shift register l
G4 is the shift-out output inverting gate of shift register 1.

The structure of the data DATA is such that a start bit STA is started, followed by inverted 8-bit data O to 7, and a stop bit STP is added at the end.

The start bit STA is 1 bit, and is characterized by the fact that it changes from H (high) level to low (low) level. On the other hand, stop bit STP is not limited to 1 bit,
It remains at H level until the next start bit STA appears.

When the gate G1 detects the change point (■) of the start bit STA, it resets the flip-flop 3 and clears the shift register 1 (clear terminal 5CLR becomes L=■). At this time, the outputs Q1 to Q9 of shift register 1
all become L, and at the same time, flip-flop 3 becomes FF2
The output becomes H (■), and the FFI output becomes L (■
'). When the FF2 output becomes H, the output of the gate Gl becomes H, so the clear terminal 5CLR returns to H (■). As a result, the output of the inverting gate G3 (inverted signal of data DATA) is sequentially taken in from the serial input terminal Si of the shift register 1. SCK is a clock input terminal, to which a clock is supplied after the FF2 output of the flip-flop 3 becomes H. As the number of clock inputs to this clock input terminal SCK increases, the output terminals Ql, Q2
．． Th11m data is shifted to . The beginning is the inversion STA of the start bit, and when this reaches the final bit Q9 (■), bits Q8 to Q!
8-bit data O to 7 are present.

Inversion STA of start bit reaching final bit Q9
is inverted again by the inversion gate G4, and its falling edge (ST
Flip-flop 3 is set at (corresponding to the rising edge of A). As a result, FF1. FF2 output is inverted (■■
'). The FF2 output is used to close the clock input gate G2 (■). Further, the FFI output is used as the clock RCK of the D latch 2 that launches the data outputs Q1 to QB of the shift register 1 in parallel.

As is clear from the above operation explanation, start bit S
TA clears shift register 1 and flip-flop 3
Since the reset is performed, there is no need for a cent signal like in the past. In addition, the flip-flop 3 that limits the number of clocks is reset by the start bit before inputting to the shift register 1, and is clocked by the start bit after shifting out the shift register 1, so a conventional counter is not required. I don't. When actually configuring
There is an iC in which QI''Qθ of shift register l and D latch 2 are integrated into one chip.Therefore, the number of parts can be reduced.

Note that each bit of the data DATA becomes valid at the rising edge of the clock CLOC. Further, the dotted lines and solid lines Q+, D+ to Qe, and De indicate the outputs Q1 to Qe of the shift register 1 and the outputs D1 to DB of the latch 2, respectively (D+ to D8 do not change until the rise of the FFI output). The gate signal GATE input to the D latch 2 enables D1 to D8 at L level and makes D1 to Da high impedance at H level. Since the serial data is inverted at the parallel outputs D1 to D11, it is inverted on the microcomputer side before being sent out, but this only requires one instruction.

〔Effect of the invention〕

As described above, according to the present invention, N bits of serial data following the start bit can be taken into the shift register without requiring a counter. Therefore, there is no need to issue a reset signal from the microcontroller side, and the number of ports can be reduced. Additionally, the software becomes easier in managing the timing of issuing reset signals from different ports prior to data transmission.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram of a conventional S/P converter, and FIG. 3 is a time chart showing the operation of the present invention. Applicant: Fujitsu Ten Ltd. Representative Patent Attorney Minoru Aoyagi 12-Court

Claims (1)

[Claims] an (N+1)-bit shift register (1) that receives N-bit serial data input in synchronization with a clock;
A gate that detects a start bit input one bit ahead of the serial data and clears the shift register
G1), a gate (G2) that inputs a clock to the shift register, and a flip-flop that is reset by the start bit detection output of the gate (G1) and set by the shift-out output of the start bit from the shift register. (3) A serial/parallel converter characterized in that the gate (G2) is enabled only while the flip-flop is being reset.