JPH01298816A - Serial interface circuit - Google Patents

Abstract

PURPOSE:To halve bit number of a shift register by detecting the transmission of bit number being a half the bit number of a serial data and transferring a data fetched in a latch circuit at the point of time to the shift register so as to send the serial data. CONSTITUTION:Only a data in n-bit being a half of 2n-bit among the data in 2n-bit to be transferred is stored in a shift register 1, the remaining data in n-bit is stored once in latch circuits 3a-3d and transferred to the shift register 1 after the transfer operation of n-bit in the shift register 1 is finished. That is, since the shift register 1 processes the data to be transferred by a half each, the number of stages by a half bit number has only to be prepared to a data length of the serial data. Thus, the shift register 1 is constituted by a fewer number of stages than a conventional stage number, the hardware is reduced and the chip area is decreased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a serial interface circuit that converts parallel data to serial data.

[Prior Art] Recently, in devices equipped with LSIs that handle digital data, such as microcomputers, in order to reduce the number of internal wiring between the LSIs within the device, data transfer between the LSIs is performed by serial transfer. I have to. Further, for the same reason, the use of serial transfer methods is increasing for data transfer with the outside of the device. For this reason, many recent LSIs are equipped with a serial interface circuit.

FIG. 3 is a diagram showing the configuration of such a conventional serial interface circuit.

Note that here, ° indicates a serial interface circuit that handles 8-bit data. This circuit basically includes an 8-bit shift register 31, a 1-bit latch circuit 32 that is not provided at the output stage of the shift register 31, and a counter 33 that counts the serial clock 2 signal CK. has been done. The shift register 31 is constructed by connecting eight stages of 1-bit flip-flop circuits 34. This shift register 31 operates on the data bus D when the data write signal WD is at high level.
The data on B is taken into each flip-flop circuit 34 in parallel, and then the data held in each flip-flop circuit 34 is shifted one bit at a time in synchronization with the serial clock signal CK, and is output to the latch circuit 32. Latch circuit 32
The serial data given to is output from the serial data output terminal SO. The serial clock signal CK is counted by the counter 33. When seven serial clock signals CK are counted, the output of the AND gate 35 becomes high level, and this signal is used to generate an interrupt request signal indicating the completion of serial data transmission.

The first stage 1-bit flip-flop circuit 34 constituting the shift register 31 includes, for example, a master latch circuit 4o and a slave latch circuit 41, as shown in FIG.

When writing data, the serial clock signal CK is at high level, that is, the output signal (G1) of the inverter 36
When data write signal WD (G2) is at low level
to a high level. As a result, the transfer gate 42 is turned on, the transfer gate 43 is turned off, and the transfer gate 44 is turned on, so write data PDi (D2
) are taken in via inverters 45, 46, 47, 48. When the serial clock signal CK becomes low level, the transfer gate 44 is turned off and the transfer gate 49 is turned on, so that the inverter 47.4
8 holds the data.

During serial data transfer, data write signal WD is set to low level. As a result, the transfer gate 42 is turned off, and the serial clock signal CK
Taking in the data S D +-t of the previous stage flip-flop circuit via the transfer gate 43 synchronized with the inverter 45°46 and transfer gate 59.6
The data is held in a 0 loop repeatedly, and the data is sequentially shifted to the master latch circuit 40 and the slave latch circuit 41, and a shift operation is performed.

[Problems to be Solved by the Invention] However, the conventional serial interface circuit described above has a relatively large number of elements constituting each flip-flop circuit of the shift register, as shown in FIG. As the number of bits increases, the number of bits of the shift register also increases, which results in an increase in the amount of hardware required when integrated into an LSI, resulting in an increase in chip area.

The present invention has been made in view of such problems, and includes:
It is an object of the present invention to provide a serial interface circuit that can configure a shift register with a small number of stages even when the data length of serial data is long, and can reduce the amount of hardware and, by extension, the chip area.

[Means for Solving the Problem] A serial interface circuit according to the present invention includes a latch circuit that stores upper or lower n bits of data of 2n (n is a natural number) bits to be serially transferred; Of the 2n bits of data to be serially transferred, the remaining n bits of data that are not stored in the latch circuit are stored, and a shift operation is performed in synchronization with the serial clock signal, and after the n shift operations are completed, the remaining n bits of data that are not stored in the latch circuit are stored. a shift register that inputs n-bit data stored in a latch circuit in parallel and performs a shift operation in synchronization with the serial clock signal; a counter that counts the serial clock signal; The present invention is characterized by comprising a logic circuit that detects counting of serial clock signals and provides timing for supplying data from the latch circuit to the shift register.

[Operation] According to the present invention, of the 2n-bit data to be transferred, only half of the n-bit data is stored in the shift register, and the remaining n-bit data is stored in the latch circuit and then transferred to the shift register. After the n-bit transfer operation is completed, the data is transferred to the shift register. In other words, since the shift register processes the data to be transferred one half at a time, it is sufficient to provide the number of stages equal to half the number of bits for the data length of the serial data. Therefore, the shift register can be configured with a smaller number of stages than conventional ones, and the amount of hardware and chip area can be reduced.

[Example] Next, an example of the present invention will be specifically described with reference to the accompanying drawings.

FIG. 1 is a block diagram of a serial interface circuit according to an embodiment of the present invention. Although the case where 8-bit serial data is handled is explained here, it goes without saying that the present invention can handle data of any number of bits as long as it is an even number of bits.

This serial interface circuit consists of a 4-bit shift register 1, a 1-bit latch circuit 2 provided at the output stage of this shift register 1, and 4 latch circuits arranged to hold 4-bit data. 3a, 3b
, 3c, 3d, and a counter 4 for counting the serial clock signal CK. The shift register 1 is a 1-bit flip-flop formed by cascading a master latch circuit 6i (i=a, b, c, or d, the same applies hereinafter) configured as shown in FIG. 4 and a slave latch circuit 71. It consists of four stages connected. A transfer gate 81 is inserted between master latch circuit 61 and slave latch circuit 71 to guide the output of master latch circuit 61 to slave latch circuit 71 during normal shift operation.

Further, a transfer gate 91 is inserted between the latch circuit 31 and the slave latch circuit 71 to guide the output of the latch circuit 31 to the slave latch circuit 71 when the data held in the latch circuits 3a to 3d is transferred to the shift register 1. has been done. Serial clock signal CK is provided as a clock signal to slave latch circuits 7a to 7d, and is also provided via inverter 10 as a clock signal to master latch circuits 6a to 6d. Further, this serial clock signal CK is given to the counter 4. The NOR gate 11 and the AND gate 12 are logic circuits that detect when the output of the counter 4 becomes "100", that is, "4". The output of this logic circuit is given as a control signal to transfer gates 9a to 9d, and is also provided as a control signal to transfer gates 8a to 9d via an inverter 13.
It is given as a control signal of 8d to 8d. Also, AN
The D gate 14 detects that the output of the counter 4 is "111", that is, "
7'' is detected and outputs a signal.

FIG. 2 shows a time chart of the serial interface circuit according to this embodiment configured as described above. When the data write signal WD becomes high level, the data bus D
Of the 8-bit data on B, the upper (or lower) 4 bits of data are stored in the shift register 1, and the remaining lower (or upper) 4 bits of data are taken into the latch circuits 3a to 3d. After that, the serial clock signal CK
When is input, the contents of the shift register 1 are shifted one bit at a time in synchronization with this, and are outputted from the serial data output terminal SO via the latch circuit 2. At the same time, counter 4 counts this serial clock signal CK. When the serial clock signal CK is generated four times, the output of the counter 4 becomes "100", and the AND gate 1
The output of inverter 2 becomes high level, therefore the output of inverter 13 becomes low level, and transfer gates 8a to 8d
is off and transfer gates 9a to 9d are on, prohibiting data on the mask side of shift register 1 from being transferred to the slave side and transferring the contents of latch circuits 3a to 3d to the slave side of shift register 1. and continue transmitting the lower (or upper) 4 bits of serial data. When the serial clock signal CK is generated seven times, the output value of the counter 4 becomes "111", and the AND
The output of gate 14 becomes high level. This signal is used to generate an interrupt request signal for completion of serial data transmission.

[Effects of the Invention] As described above, in the present invention, the upper or lower half of the serial data to be transmitted is stored in the shift register, and the remaining half is taken into another latch circuit. Then, it starts transmission, detects that half the number of bits of the serial data has been transmitted, and at that point transfers the data that has been captured in the aforementioned latch circuit to the shift register, and I am trying to send data. Therefore, the number of bits in the shift register can be halved,
This has the effect of reducing the amount of hardware and, by extension, reducing the chip area.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a serial interface circuit according to an embodiment of the present invention, FIG. 2 is a timing diagram during operation of the same circuit, FIG. 3 is a block diagram of a conventional serial interface circuit, and FIG. 4 is the same. FIG. 3 is a detailed circuit diagram of a shift register in the circuit. 1.31: Shift register, 2, 3a to 3d. 32; Latch circuit, 4.33; Counter, 6a to 6d
, 40; master latch circuits, 7a to 7d. 41; Slave latch circuit, 8a to 8d, 9a to 9
d, 42 to 44, 49, 59, 60;) transferate

Claims (1)

[Claims] (1) A latch circuit that stores the upper or lower n bits of data of 2n bits (n is a natural number) to be serially transferred; The remaining n bits of data that are not stored are stored, a shift operation is performed in synchronization with the serial clock signal, and after the n shift operations are completed, the n bits of data stored in the latch circuit are input in parallel. a shift register that performs a shift operation in synchronization with the serial clock signal, a counter that counts the serial clock signal, and detects that the counter has counted n serial clock signals;
A serial interface circuit comprising: a logic circuit that provides timing for supplying data from the latch circuit to the shift register.