JPS62229594A - Data idle area detection circuit for fifo circuit - Google Patents

Abstract

PURPOSE:To attain consecutive operation by high speed writing and idle area detection by forming a means for detecting at the time of data writing that a region with stage number larger by one than that of a data idle area to be detected by an FIFO circuit is an idle area. CONSTITUTION:The circuit consists of a NOR gate inputting signals Q1-Qn going to a high level when a data exists in the 1st-5th stages of the FIFO circuit and outputting a signal Q0 and a D.FF circuit inputting the signal Q0. In this circuit, the clock of the FF is used as a write signal WR in synchronism with the system clock to latch a high level of the signal Q0 before the signal Q1 goes to a high level. Thus, the presence of an idle area larger than the idle area to be detected by one stage is represented until the next data are written and a margin is provided for the detection time. Thus, high speed data write and the consecutive operation of the idle area detection are attained.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a state detection circuit for a FIF○ circuit used in semiconductor logic circuits, particularly digital circuits.

2. Prior Art Currently, in order to realize a method of outputting accumulated data in the order in which it is input (hereinafter referred to as the FIFO method), shift registers are used, and RAM (Random Acc.
ess Memory) may be used. especially,
A circuit that realizes a FIFO method (hereinafter referred to as a domino-type FIFO circuit) that is configured with a shift register controlled by a domino method using a shift clock with an analog delay generally has a high-speed shift operation, so it is a high-speed FIFO circuit.
It is widely used in circuits requiring FO operation.

Conventionally, when detecting a data empty area in a domino-type FIFO circuit of this type, it is common to generate a signal from information on the presence or absence of data indicated by control units at appropriate stages from the first stage to the final stage.

Figure 3 shows a conventional method for creating a signal indicating that data can be input at least four times in succession when there are four stages of empty data areas in a domino-type FIFO circuit consisting of 10 stages. FIG. 2 is a connection circuit diagram showing an example of a circuit.

This circuit consists of a FIFOI in the first stage and a FIFOI in the final stage.
A domino-type FIFO circuit consisting of 0 and signals Q1 to Q4 that become a noise level when data exists in the first to fourth stages of the FIFO circuit are input, and the output core is Q. It is composed of a 4-input NOR gate which is 0.degree., and a D-TYPE flip-flop which is a two-stage latch circuit which receives QO' as an input and uses the system clock .phi. as its clock.

FIG. 4 is a timing chart showing an example of the operation of each connection point in the connection circuit diagram shown in FIG. 3. This timing diagram uses the write signal WR synchronized with the system clock φ, and when the system clock φ is at /'% low level,
This diagram shows part of the timing when writing data to the first stage FIFO and detecting whether there is a data empty area for four stages are alternately and continuously performed.

A conventional detection circuit for a data empty area in a domino-type FIFO circuit shown in FIG. 3 will be described below using a timing diagram shown in FIG.

When the FIFO circuit has five or more stages of empty data areas, the input data written by the write signal WR at timing T1 is converted into signals Q and -, which indicate the presence or absence of data in the first to fourth stages of the FIFO circuit, respectively. As shown in the timing chart 04, the signal propagates from the first stage to the fourth stage. D-T
Since the YPE flip-flop circuit is clocked with a signal synchronized with the system clock φ, Q, -Q,
If the timing at which QOo, which is the output of the 4-input NOR whose inputs are from low level to high level again, is at least before the end of timing T3, then
The output E' of the YPE flip-flop is at a high level, that is, the information that there is a data empty area of 4 or more stages is output after timing T4.

This is a limitation when shortening the period of the system clock φ. In other words, the domino FIFO shown in Figure 3
The conventional data empty area detection circuit in the circuit uses the period of the system clock as the output Q of a 4-input NOR gate. The pulse width cannot be made shorter than the pulse width Two' during the period when ' is at a low level.

In particular, as the number of stages of data empty areas to be detected increases, the pulse width Two+ becomes longer, so it is clear that restrictions on shortening the period of the system clock φ become more severe. It is possible to shorten the pulse width of the signals from Q1 to Q4, but generally the Q
There is a limit to how short the pulse width from 1 to Q can be while ensuring stable operation.

Problems to be Solved by the Invention As can be seen from the above explanation, in the conventional data empty area detection circuit, the period of the system clock is determined by four inputs N
There is a drawback that high-speed writing cannot be performed because the pulse width cannot be made shorter than "Two" during the period when the output Q0° of the OR gate is at a low level. In particular, as the number of stages of data empty areas to be detected increases, the pulse width Two becomes shorter. ' becomes longer, so the restrictions become tighter.

In order to eliminate this drawback, it may be possible to shorten the pulse width of the signals Q to Q4, but there is a limit to ensuring stable operation.

SUMMARY OF THE INVENTION In view of the above circumstances, an object of the present invention is to provide a semiconductor logic circuit that can be configured with a relatively simple circuit and that can perform faster write operations.

Means for Solving the Problems The FIFO circuit data empty area detection circuit of the present invention which solves the above problems detects data from the first stage to the empty FIFO circuit which is one stage more than the data empty area to be detected. A logic circuit that creates a signal indicating that the
A signal created by a combination of a control signal for writing data to the circuit or a control signal for writing data to the first stage FIFO circuit and any other signal is used as a clock, and the output of the logic circuit is It has a latch circuit that receives an input signal.

Last month, the present invention had a hardware configuration that detects, at the time of data writing, that the number of stages (N+1), which is one stage more than the number of stages N of the data empty area to be detected by the FIFO circuit, is the empty data area. .

Each stage outputs a low level signal when there is data and no high level pedestal. These signals are input to the (N+1) input NOR gate, so by looking at the output of this NOR gate, it is possible to know whether there are at least N stages of empty areas. N
The output of the OR gate is a D-T clocked by the write signal.
Since it is input to the YPE gel flop, the existence of empty space will continue to be indicated until the next data is written.

Therefore, it becomes possible to perform continuous high-speed data writing as well as detect empty data areas.

Example The present invention will be described below with reference to the drawings.

Figure 1 shows the present invention as a domino-type FIFO consisting of 10 stages.
FIG. 2 is a connection circuit diagram showing an embodiment of the present invention implemented in a four-stage data empty area detection circuit in a circuit. The circuit of this embodiment is a domino-type FIF○ circuit consisting of an initial stage FIF○1 to a final stage PIF○10, and a FIF○ circuit in which each FIF○
Signals Q1 to Q that become high level when data exists in the 1st to 5th stages of the O circuit are input, and the output name is Q.
. It is composed of a 5-input NOR gate, and a D-TYPE flip 70, which is a two-stage latch circuit that uses Qo as an input and uses the write signal WR of the first-stage FIFO circuit as a clock.

An example of the operation will be explained using the timing chart shown in FIG. This timing diagram uses a write signal WR synchronized with the system clock φ to alternately and continuously write data and detect whether there is an empty data area for 4 stages when φ is high level. This figure shows part of the timing when it is executed.

01 to Q are signals that become high level when data exists in the first to fifth stage FIF◯ circuits, respectively. Therefore, Q is the output of a 5-input NOR circuit that receives Q1 to Q5 as inputs. When is at a high level, it can be seen that there is no data in at least the first to fifth stage FIFO circuits.

In the circuit of this embodiment, by using the write signal WR as the clock of the D-TYPE flip-flop, an empty area for 5 stages (4 stages plus 1 stage) before the signal Q becomes high level. The information that there is, that is, Q. To latch the high level of the FIFO circuit, at least 4
The existence of empty space in a column can be indicated until the next data is written.

In the case of the conventional four-stage empty area detection circuit shown in FIG.
Since the TYPE flip-flop circuit uses a signal synchronized with the system clock φ as its clock, the timing at which Qo' shown in FIG. 4 changes from low level to high level again must be at least before the end of timing T3. On the other hand, in the circuit of the embodiment of the present invention shown in FIG. 1, the D-TYPE flip-flop circuit uses the write signal W.
Since the clock is a signal synchronized with R, Q.

The timing when goes from low level to high level again is
This means that it must be at least before the end of timing T5. This indicates that it is possible for a domino-type FIFO circuit to continuously update data at high speed while detecting empty areas of data.

FIG. 5 shows the circuit of the embodiment of the present invention shown in FIG.
This is a timing diagram showing the timing when data written at timing TI is stored in the fifth stage because data exists from the sixth stage to the tenth stage of the FO circuit.

In this case, when further data is written at timing T5, since Q5 is at high level, the output Q of the 5-input NOR circuit. is at a low level after data writing at timing T1. Therefore, the output signal E of the D-TYPE flip-flop in FIG. 1 remains at a low level even after timing T5, indicating that the FIFO circuit no longer has an empty area for four stages.

In the above embodiment, the write signal WR to the first-stage PIF0 circuit is used as the clock, but a signal created by a combination of the write signal WR and any other signal may be used as the clock.

As described in detail, the free area detection circuit of the domino type FIF○ circuit of the present invention sets the number of stages of empty areas to be detected to N(N
is a positive integer smaller than the total number of stages in the FIFO circuit), it is possible to write data at high speed with a relatively simple hardware configuration that detects when data is written that the N+1 stage is an empty area for data. This has the effect of enabling continuous operation of data loading and data empty area detection. Generally speaking, the larger the number N of empty areas to be detected, the more time it takes to detect empty areas, making high-speed writing impossible.However, in the present invention, where there is plenty of time for empty area detection, the effect is even more remarkable. Become something.

[Brief explanation of drawings]

FIG. 1 shows the present invention in a domino-type FIF consisting of 10 stages.
A connection circuit diagram showing an example of implementation in a four-stage data empty area detection circuit in an O circuit. Figure 2 is an example of an operation showing the movement of each contact in the circuit shown in Figure 1. The timing diagram shown in Figure 3 is a domino type FI consisting of 10 stages.
A connection circuit diagram showing an example of a conventional detection circuit for a four-role data empty area in an FO circuit. Fig. 4 is a timing diagram showing an example of operation showing the movement of each contact point of the circuit shown in Fig. 3. , FIG. 5 is timing T1
2 is a timing chart showing an example of an operation showing the movement of each contact in the circuit shown in FIG. 1 when data written in is stored in a fifth stage FIFO circuit; FIG. (Main reference numbers) FIFOI - FIFOIO - 1st to 10th stage circuits of the FIFO circuit including a domino control section using analog delay, φ: system clock, WR: FIFO synchronized with system clock φ Write control signal of the circuit, Q, ~Q, -・(-n('FI FO1 ~ FI
Signal indicating the presence of data output from the control section of FO5, T1 to T5... Timing based on φ, Q, ・
・Output of a 5-input NOR circuit with Q, ~Q5 as inputs, Q,'...Output of a 4-input NOR circuit with Q, -Q as inputs, Two...Pulse width when Qo is low level, Two
” ・・Q o' is the pulse width of the low level ibis, E・
・D- with Qo as input and control signal WR as clock
Output of TYPE flip-flop, E"...Q Output of D-TYPE flip-flop with input of o' and system clock γ and φ

Claims (1)

[Claims] This is a data empty area detection circuit of a FIFO circuit, from the first stage to the F of one stage more than the data empty area to be detected.
Up to the IFO circuit, there is a logic circuit that creates a signal indicating that data does not exist, and a control signal for writing data to the first-stage FIFO circuit, or a control signal for writing data to the first-stage FIFO circuit. 1. A data empty area detection circuit for a FIFO circuit, comprising a latch circuit which uses a signal generated by combining the above logic circuit with another signal as a clock and whose input is an output of the logic circuit.