JPS63106987A - Detection circuit for data vacant area of fifo circuit - Google Patents

Abstract

PURPOSE:To shorten the flowing time of a through current to be generated when a data exists in a FIFO, by inputting a signal representing the existence of the data at the final stage of the FIFO to the gate of a MOS transistor used as a load MOS transistor. CONSTITUTION:The titled circuit is constituted of n-ch MOS transistors 21-30 setting signals Q1-Q10 which go to high levels when the data exist in stages 1-10 in a FIFO circuit 20 as gate inputs, and a p-ch MOS transistor 31 which becomes the load transistor of the transistor 21-29 only when the data exist in the stages 1-9. When a first data is inputted to a first stage, the transistor 21 is energized, and the transistor 31 functions as the load transistor, then, the through current starts to flow, and it flows until the data is inputted to the final stage. The flow time is 63ns at maximum, and hereafter, no through current flows as far as the data exist in the final stage.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention is directed to FIF used in digital semiconductor logic circuits.
This invention relates to a data empty area detection circuit of an O circuit.

[Conventional technology]

Currently, in order to realize the method of outputting accumulated data in the order in which it was input (hereinafter referred to as the FIFO method), there are two methods: using a shift register, and using RAM (Random Acc.
ess Me+++ory) may be used. In particular, a FIFO consisting of a shift register controlled in a domino manner using a shift I ~ clock using an analog delay.
A circuit that implements this method (hereinafter referred to as a domino FIFO circuit) generally has a high-speed shift operation, and is therefore widely used in circuits that require high-speed FIFO operation.

Conventionally, when detecting a data empty area in this type of domino-type FIFO circuit, a signal is generated from information on the presence or absence of data indicated by control units of appropriate stages from the first stage to the final stage.

FIG. 3 is a circuit diagram of a 10-stage FIFO circuit using the conventional domino method, and includes an example of a circuit for detecting that all stages are empty data areas. This circuit consists of 10
FIFO circuits 20 (FIFO1 to FIFo10), n-ch MOS transistors 21 to 30, and p-c
h MOS transistor 31.

FIG. 4 is a timing diagram showing an example of the operation of each connection point in FIG. , a case is shown in which 3 bytes of data are written into the first stage FIFO, and then 3 bytes of data are read out using a read signal RD asynchronous to the system clock φ.

[Problem that the invention seeks to solve]

In the data empty area detection circuit in the conventional domino-type FIFO circuit described above, when data is written to the FIFO, the MO transistor whose gate input is a signal indicating the presence or absence of data in the stage where data exists becomes conductive. Therefore, until all data is read out from the PIFO, the load P-ch MOS transistor 31 whose gate input is the ground is connected to the MOS transistor whose gate input is a signal indicating the presence or absence of data in the stage where the data exists. The drawback is that a through current flows through the cap for a time T'.

SUMMARY OF THE INVENTION An object of the present invention is to provide a data empty area detection circuit for a FIFO circuit that eliminates such drawbacks and shortens the time through which a through current flows.

[Means for solving problems]

The data empty area detection circuit of the FIFO circuit of the present invention includes N MOS transistors whose respective power supply terminals and output terminals are commonly connected, and whose gates each input a signal indicating the presence or absence of data in each stage of the N-stage FIFO. and an output terminal connected to a power source different from the N input circuit and commonly connected to the common output terminal, and the FIF
one MOS whose gate input is a signal indicating the presence or absence of data at the final stage of the MOS transistor, and which has a complementary relationship with the MOS transistor.
and a load circuit made of an S transistor, and outputs a signal indicating the presence or absence of data from the common output.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram including an embodiment of the present invention, and FIG.
The timing diagram shown in the figure shows the case where data empty area detection circuits in all stages are applied to a 10-stage domino-type FIFO circuit.
Domino FIFO circuit 20 configured with IFOIO
and signals Q1 to QIO that become high level when data exists in the 1st to 10th stages of the FIFO circuit, respectively.
n-ch MOS transistor 2 with gate input
1 to 30, and p-ch M which becomes a load transistor for n-ch MOS transistors 21 to 29 only when data exists in stages other than the final stage, that is, stages 1 to 9 of the FIFO.
It is composed of an OS transistor 31.

As the operation of this embodiment, a case will be described in which data is written into the FIFO using a write signal WR synchronized with the system clock φ as shown in FIG.

First, when the first data is input to the first stage of FIFO,
FIFO output Q1 becomes high level when data exists, so output Q1 is used as gate input for n-ch
MOS transistor 21 becomes conductive. In addition, the signal QIO becomes high level when data exists at this time.
p-ch MOS transistor 3 with gate input
1 serves as a load MOS transistor for the n-ch MOS transistor 21 which has the output Q1 as its gate input, so by the ratio operation of the two, the output Q1 is the gate input from the p-ch MOS transistor 30 which has the output QIO as its gate input. A through current begins to flow through the n-ch MOS transistor 21.

This through current flows for a time T until the first data is input to the final stage (10th stage). Since this data moves in 7 ns at the latest per stage, in this embodiment the data moves from the first stage to the last stage in 63 ns at the latest. When this data is input to the final stage, the output QIO becomes high level if data exists, so the p-ch MOS transistor 30 whose gate input is the output QIO becomes non-conductive, and no through current flows. . Thereafter, as long as data exists in the final stage, the p-ch MOS transistor 30 whose gate input is the output QIO is in a non-conductive state, so no through current flows.

In this embodiment, each stage of the N-stage FIFO includes N n-ch MOS transistors whose gate inputs are signals that go high when data exists, and a final stage (N stage). In other words, p-ch becomes a load MOS transistor for an n-ch MOS transistor only when data exists in stages 1 to N-1.
Although the case of a circuit composed of MOS transistors is shown, conversely, in each stage of an N-stage FIFO, N p-ch MOS transistors whose gate input is a signal that becomes low level when data is present are used. and,
A similar effect can be obtained for a circuit composed of n-ch MOS transistors that serve as load MOS transistors for these p-ch MOS transistors only when data exists in the 1st to N-1 stages after the final stage (Nth stage). It is clear that it can be obtained.

〔Effect of the invention〕

As explained above, the empty area detection circuit of the FIFO circuit of the present invention inputs a signal indicating the presence or absence of data at the final stage of the FIFO to the gate input of the MOS transistor conventionally used as a load MO3 transistor. According to
The time T' in which a through current flows, which conventionally occurs when data exists in a FIFO, has been reduced to a very short time, from when the first data is input to the first stage of the FIFO until the first data is input to the final stage. It has the effect of being able to suppress the temperature within T.

Further, the present invention provides that the longer the interval between data write signals to the FIFO and the interval between the data read signals from the FIFO, the more the number of continuous data input to the FIFO increases. The larger the number, the more pronounced the effect will be.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an embodiment in which the present invention is applied to a data empty area detection circuit of a domino-type FIFO circuit, FIG. 2 is a timing diagram showing an example of the operation of each contact point in FIG. 1, and FIG. FIG. 4 is a circuit diagram showing an example of an all-stage data empty area detection circuit of a conventional domino-type 10-stage FIFO circuit, and FIG. 4 is a timing diagram showing an example of the operation of each contact point in FIG. 3. 2O-FIFO circuit, 21-30...-n-ch
MOS I-transistor, 3l-p-ch MOS
Transistor, φ...system clock, FIFO
I~FIFOIO...FIF including domino control unit
Each stage circuit of O circuit, WR... write control signal, RD...
- Read control signal, Q1 to QIO...output signal indicating the presence or absence of data, EMP signal...empty signal for all stages of the FIFO circuit, T, T'...through current time.

Claims (1)

[Claims] N MOS transistors each having each power supply terminal and each output terminal connected in common and inputting a signal indicating the presence or absence of data in each stage of the N stage FIFO to each gate.
an input circuit, an output terminal connected to a power source different from that of the N input circuit and commonly connected to the common output terminal; a signal indicating the presence or absence of data at the final stage of the FIFO; 1. A data empty area detection circuit for a FIFO circuit, comprising a load circuit consisting of one MOS transistor in a complementary relationship with a transistor, and outputting a signal indicating the presence or absence of data from the common output.