JPH065090A - Shift register circuit - Google Patents

Abstract

PURPOSE:To prevent a shift malfunction due to the delay of an operating clock by a method wherein a third latch circuit is installed, data is input when the operating clock rises and data is output when it falls after one cycle and an output to a next-stage FF circuit is delayed by a half cycle. CONSTITUTION:An FF (i) circuit 1 constitutes a second latch circuit in the following manner: it is operated by an enable signal whose logic is inverse to a first latch circuit; and it sends out input data SI (i) from the first latch circuit as output data. Then, a third circuit 4 which is constituted in the following manner is installed: it is operated by an enable signal whose logic is the same as the first latch circuit; and it sends out signal data from the second latch circuit as output data SO (i). By this constitution, the timing of an operating clock SCK (i) can obtain the margin of a half-cycle portion, and the shift operation of the title circuit can be performed surely even when the operating clock is delayed due to an interconnection capacity and a resistance.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a shift register circuit composed of semiconductor circuits.

[0002]

2. Description of the Related Art FIG. 5 is a block diagram showing a flip-flop circuit used in a conventional one-phase shift register circuit. In the figure, 1 is a flip-flop circuit and 2 and 3 are latch circuits. A is a node of the input section of the flip-flop circuit 1 and a node of the input section of the latch circuit 2. B is a node of the output part of the latch circuit 2 and a node of the input part of the latch circuit 3. C is a node of the output part of the latch circuit 3 and a node of the output part of the flip-flop circuit 1. SCK is an operation clock of the flip-flop circuit 1. Operating clock SC
K is input to the latch circuits 2 and 3, the latch circuit 2 operates with a low enable signal, and the latch circuit 3 operates with a high enable signal.

FIG. 6 is a timing chart showing the operation clock and internal waveform of the flip-flop circuit 1.
In this way, the latch circuit 2 inputs the data of the node A and outputs the data to the node B by the low enable signal of the operation clock SCK. The latch circuit 3 inputs the data of the node B by the high enable signal of the operation clock SCK and outputs the data to the node C. Therefore, the flip-flop circuit 1 inputs the data of the node A at the falling timing of the operation clock SCK, and the node C at the rising timing of the operation clock SCK after a half cycle.
Output the data to. In addition, each latch circuit 2,
3 has a delay, so that the output data also has a delay.

FIG. 7 is a block diagram showing a conventional one-phase shift register circuit. FF (i), FF (i + 1), FF (j)
Is a flip-flop circuit 1 equivalent to that shown in FIG. SI (i), SI (i + 1), SI (j) are flip-flop circuits FF (i), FF (i + 1), FF, respectively.
It is the input data of (j). In addition, SO (i), SO (i + 1)
, SO (j) are flip-flop circuits FF (i), respectively.
, FF (i + 1), FF (j) output data. Here, since the flip-flop circuits FF (i) and FF (i + 1) are directly connected, SO (i) and SI (i + 1) have the same data. In addition, SCK (i), SCK (i + 1), SCK
(j) are flip-flop circuits FF (i) and FF, respectively.
It is an operation clock given to (i + 1) and FF (j).

FIG. 8 is a timing chart showing operation clocks and internal waveforms of the shift register circuit of FIG. Here, SCK (i-1) is a flip-flop circuit FF
This is the operation clock of the flip-flop circuit in the previous stage of (i). Each of t1 to t3 is the operation clock SCK (i-
1), SCK (i), SCK (i + 1) are rising times, t4 is the time when the data SI (i) changes, and t5
Is the time when the data SI (i + 1) changes. Also, a ~
d is data.

Next, the operation will be described. In the one-phase clock operation shift register circuit, the operation clock SCK is delayed due to the capacitance and resistance of the wiring. For example,
In FIG. 8, flip-flop circuits FF (i) and FF (i
+1), operation clock SCK (i-1) input to FF (j)
, SCK (i), SCK (i + 1) rise times are t1, t2, and t3, respectively, and a delay occurs.

The delay of the operation clock is small like the rising times t1 and t2, and the rising time t2 of the operation clock SCK (i) is input data SI (i) output by the rising of the operation clock SCK (i-1). Change time t4
If it is faster than SI, the data b of SI (i) is the operation clock S
Flip-flop circuit FF due to the fall of CK (i)
It is input to (i), and is shifted and output at the subsequent rising t2. As described above, when the delay of the operation clock is small, the output data can be normally shifted and output.

[0008]

Since the conventional one-phase shift register circuit is constructed as described above, the latch circuits 2 and 3 have a delay, and the operation clock SCK is caused by the capacitance and resistance of the wiring. Delay occurs. Therefore, in FIG. 8, the delay of the operation clock is large at the rising times t2 and t3, and the operation clock SCK (i + 1)
If the rising time t3 of the output clock is later than the time t5 of the change of the output data SO (i) output by the rising t2 of the operation clock SCK (i), the SO to be shifted out should be output.
The data a of (i) is not shifted and output, and b is output to the flip-flop circuit FF (i + 1). As described above, when the delay of the operation clock is large, there is a problem that the flip-flop circuit does not perform a normal shift operation and malfunctions.

The present invention has been made to solve the above problems, and an object of the present invention is to obtain a shift register circuit which prevents a malfunction of a shift operation due to a delay of an operation clock.

[0010]

In a shift register circuit according to the present invention, a flip-flop circuit is operated by an enable signal having an inverse logic to that of a first latch circuit, and input data from the first latch circuit is output as output data. And a third latch circuit which operates with an enable signal having the same logic as that of the first latch circuit and sends the input data from the second latch circuit as output data. It is constructed by connecting a plurality of the flip-flop circuits in series.

[0011]

In the flip-flop circuit according to the present invention, by providing the third latch circuit, the data output to the next-stage flip-flop circuit is delayed by a half cycle. Therefore, a timing margin of half a cycle of the operation clock can be obtained, and the shift operation can be ensured even if the operation clock has a delay.

[0012]

【Example】

Example 1. An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, reference numeral 1 is a flip-flop circuit equivalent to the flip-flop circuit 1 shown in FIGS. 5 and 7 of the related art, and 4 is a latch circuit for sending input data from the flip-flop circuit 1 as output data ( Third latch circuit) and 5 are flip-flop circuits FF (i), FF (i + 1) and FF (j), respectively. SI (i), SI (i + 1), SI (j) are input data of the flip-flop circuits FF (i), FF (i + 1), FF (j), respectively. In addition, SO (i), SO (i + 1), SO
(j) are flip-flop circuits FF (i) and FF, respectively.
These are the output data of (i + 1) and FF (j). Here, since the flip-flop circuits FF (i) and FF (i + 1) are directly connected, SO (i) and SI (i + 1) have the same data. Also, SCK (i), SCK (i + 1), SCK (j) are
Flip-flop circuits FF (i), FF (i + 1),
It is an operation clock given to FF (j).

FIG. 2 is a block diagram showing a flip-flop circuit used in the one-phase shift register circuit of FIG. 1. In the figure, 1 is a flip-flop circuit equivalent to the conventional technique, and 2 is a low enable signal. A latch circuit (first latch circuit) 3 for sending input data as output data is a latch circuit (first latch circuit) 3 which operates with a high enable signal having an inverse logic to that of the latch circuit 2 and sends the input data from the latch circuit 2 as output data (first latch circuit). Second latch circuit). Reference numeral 4 denotes a latch circuit (third latch circuit) which operates with a low enable signal having the same logic as that of the latch circuit 2 and sends the input data from the latch circuit 3 as output data.
Reference numeral 5 is a flip-flop circuit used in the one-phase shift register circuit of the present invention. A is a node of the input section of the flip-flop circuit 5 and a node of the input section of the latch circuit 2. B is a node of the output part of the latch circuit 2 and a node of the input part of the latch circuit 3. C is a node of the output part of the latch circuit 3 and a node of the input part of the latch circuit 4. D is a node of the output section of the latch circuit 4 and a node of the output section of the flip-flop circuit 5. SCK is the flip-flop circuit 5
Is the operating clock of.

FIG. 3 is a timing chart showing operation clocks and internal waveforms of the flip-flop circuit 5.
In this way, the latch circuit 2 inputs the data of the node A and outputs the data to the node B by the low enable signal of the operation clock SCK. The latch circuit 3 inputs the data of the node B by the high enable signal of the operation clock SCK and outputs the data to the node C. Further, the latch circuit 4 inputs the data of the node C by the low enable signal of the operation clock SCK and outputs the data to the node D. Therefore, the flip-flop circuit 5 inputs the data of the node A at the fall timing of the operation clock SCK and outputs the data to the node D at the fall timing of the operation clock SCK one cycle later.

FIG. 4 is a timing chart showing operation clocks and internal waveforms of the shift register circuit of FIG. t6 and t7 are operation clocks SCK (i) and S, respectively.
CK (i + 1) is the rising time, t8 is the falling time of the operation clock SCK (i), and t9 is the data SO.
It is the time when (i) changes. Further, k to n are data.

Next, the operation will be described. In the one-phase clock operation shift register circuit, the operation clock SCK is delayed due to the capacitance and resistance of the wiring. For example,
In FIG. 4, flip-flop circuits FF (i) and FF (i
Operation clocks SCK (i) and SCK (i +) input to (+1)
The rising times of 1) are t6 and t7, respectively,
There is a delay.

As described above, the operation clock SCK (i + 1)
If the rising time t7 of is earlier than the changing time t9 of the data SO (i) output at the falling time t8 of the operation clock SCK (i), the output data can be normally shifted and output. In the flip-flop circuit FF (i) used in this embodiment, as shown in FIG. 4, data is input until the rising time t6 of the operation clock SCK (i), and the data is output at the falling time t8. That is, the falling time t8 of outputting data is performed after the rising time t7 of SCK (i + 1) which is the final time of data input. Therefore, the next flip-flop circuit FF (i
Rising time t7 of the operation clock SCK (i + 1) of (+1)
Can be normally shifted and output between t6 and t8.

[0018]

As described above, according to the present invention, the third latch circuit is provided to input data at the falling edge of the operation clock and output data at the falling edge after one cycle. The data output to the stage flip-flop circuit is delayed by a half cycle. Therefore, it is possible to obtain a timing margin for a half cycle of the operation clock and to ensure the shift operation even if the operation clock has a delay.

[Brief description of drawings]

FIG. 1 is a block diagram showing a one-phase shift register circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a flip-flop circuit used in the one-phase shift register circuit of FIG.

FIG. 3 is a timing chart showing an operation clock and internal waveforms of the flip-flop circuit of FIG.

4 is a timing chart showing operation clocks and internal waveforms of the shift register circuit of FIG.

FIG. 5 is a block diagram showing a flip-flop circuit used in a conventional one-phase shift register circuit.

6 is a timing chart showing operation clocks and internal waveforms of the flip-flop circuit of FIG.

FIG. 7 is a block diagram showing a conventional one-phase shift register circuit.

8 is a timing chart showing operation clocks and internal waveforms of the shift register circuit of FIG.

[Explanation of symbols]

 2 Latch circuit (first latch circuit) 3 Latch circuit (second latch circuit) 4 Latch circuit (third latch circuit) 5 Flip-flop circuit

Claims (1)

[Claims] 1. A shift register circuit in which a plurality of flip-flop circuits are connected in series, a first latch circuit which operates with an enable signal and sends output data to the flip-flop circuit, and a reverse circuit of the first latch circuit. A second latch circuit that operates with a logic enable signal and sends the input data from the first latch circuit as output data, and a second latch circuit that operates with the same logic enable signal as the first latch circuit And a third latch circuit for transmitting the input data of the above as output data.