JPH07122094A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce noise caused by the change in the condition of a flip-flop. CONSTITUTION:A shift register is constituted by serially connecting plural flip-flops 113 to 11n. Between clock signal input terminals of the flip-flops 111 to 11n, delay circuits 121 to 12(n-1) are respectively placed and clock signals SCK supplied to the flip-flops 111 to 11n are made to flow in the opposite direction of the data input direction of the shift register. Thus, the supply timing of the signals SCK to the flip-flops 111 to 11n is mutually shifted so that the occurrence of large noise caused by the simultaneous changes in the condition of many flip-flops 111 to 11n is prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit,
In particular, the present invention relates to a semiconductor integrated circuit having a shift register that operates in synchronization with a clock signal.

[0002]

2. Description of the Related Art Conventionally, a semiconductor integrated circuit having a shift register which operates in synchronization with a clock signal is shown in FIG.
As shown in FIG. 3, a plurality of flip-flops synchronized with a clock signal are connected in series to form a shift register. In the circuit of FIG. 3, the flip-flops 111 to 11n are connected in series, and the data input terminal D of the flip-flop 111 is the data input terminal 1
4 is connected. In addition, the flip-flop 11
The clock input terminals 1 to 11n are connected to the clock signal input terminal 13.

For the shift register configured as described above, the clock signal S _{CK is} input from the clock signal input terminal 13.
, The flip-flops 111 to 11n change their states in synchronization with the clock signal S _CK , so that the input data supplied from the data input terminal 14 is read into the shift register.

[0004]

However, in the semiconductor integrated circuit having the shift register described above, when the data is input to the shift register, the plurality of flip-flops forming the shift register are synchronized with the clock signal S _CK. Therefore, there is a possibility that a large amount of noise may occur with respect to the power supply voltage because the state is changed at the same time.

In view of the above-mentioned problems, it is an object of the present invention to provide a semiconductor integrated circuit having a shift register in which noise generated due to a change in the state of a flip-flop is small.

[0006]

In order to solve the above-mentioned problems, a semiconductor integrated circuit of the present invention is a semiconductor integrated circuit having a shift register in which a plurality of flip-flops are connected in series. Delay circuits are provided between the clock signal input terminals of the shift registers, the clock signals are supplied to the respective flip-flops through the delay circuits, and the clock signals flow in the direction opposite to the data input direction of the shift register. It is characterized by doing so.

[0007]

Since the present invention comprises the above technical means, the clock signals are not simultaneously input to the plurality of flip-flops forming the shift register, so that the timings at which the states of the flip-flops change are shifted from each other. Therefore, noise generation at the time of data input that may occur due to the states of many flip-flops changing simultaneously is reduced.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram of a shift register for reducing noise generation during data input according to an embodiment of the present invention.

In the circuit shown in FIG. 1, the flip-flops 111 to 11n are connected in series, and the data input terminal D of the flip-flop 111 is the data input terminal 1.
4 is connected to 4 to form a shift register. Further, delay circuits 121 to 12 (n-1) are connected between the clock input terminals of the flip-flops 111 to 11n. The delay circuits 121 to 12 (n-1) are connected in series in the direction opposite to the data input direction of the shift register, and the input terminal of the delay circuit 12 (n-1) is connected to the clock signal input terminal 13. ing.

In the circuit of FIG. 1, the data input terminal 14
When inputting more data, each of the flip-flops 111 to 11n forming the shift register includes the delay circuit 121.
A clock signal delay of ~ 12 (n-1) changes the state in a staggered manner.

That is, the clock signal S _CK supplied from the clock signal input terminal 13 is supplied to the flip-flop 11
n is directly supplied to the flip-flop 11 (n-1)
Is supplied to the flip-flop 11 (n-2) via the delay circuit 12 (n-1).
And 12 (n-2), ..., Flip-flop 112 is supplied via delay circuits 12 (n-1) to 122, and flip-flop 111 is supplied to delay circuits 12 (n-1) to 122 (n-1). Supplied via 121. Therefore, as shown in FIG. 2, the timings of the flip-flops 111 to 11n are shifted in the order of the flip-flop 11n, the flip-flop 11 (n-1), ..., And the flip-flop 111 in the direction opposite to the data input direction. Change the state by shape.

Thus, the data can be normally shifted and the state change of many flip-flops can be prevented from occurring at a certain timing at the same time although the timing of the state inversion is shifted in each flip-flop. Therefore, noise can be reduced in the entire circuit.

[0014]

As described above, according to the present invention, the timing of the state change of the flip-flops forming the shift register can be shifted, so that the generation of noise due to data input can be significantly reduced. .

[Brief description of drawings]

FIG. 1 is a circuit diagram of a shift register that reduces noise generation during data input according to an embodiment of the present invention.

FIG. 2 is a timing chart showing a state change of a flip-flop when data is input to the circuit of FIG.

FIG. 3 is a circuit diagram of a conventional shift register.

[Explanation of symbols]

 111-11n Flip-flop 121-12 (n-1) Delay circuit 13 Clock signal input terminal 14 Data input terminal

Claims (1)

[Claims] 1. A semiconductor integrated circuit having a shift register in which a plurality of flip-flops are connected in series, wherein delay circuits are provided between clock signal input terminals of the respective flip-flops, and the delay circuits are provided through the delay circuits. A semiconductor integrated circuit characterized in that a clock signal is supplied to each flip-flop and the clock signal is caused to flow in a direction opposite to a data input direction of the shift register.