JP2602340Y2 - Custom LSI circuits - Google Patents

Description

[Detailed description of the invention]

[0001]

[Industrial application] High speed and used for IC tester
The present invention relates to a custom LSI circuit for simultaneously processing many bits in parallel.

[0002]

2. Description of the Related Art In recent IC testers, the test speed has been increasing year by year, and some of them have a speed of several hundred MHz. Naturally, the repetition time of the basic clock such as the control of the internal sequence and the timing generator operates at a high speed of several nanoseconds. At the same time, miniaturization is being promoted by increasing the integration density by using a custom LSI. At this time, that is, when a high-speed LSI is realized, it is becoming a problem how much the pattern length of the printed circuit board between the LSI modules can be secured.

This will be described with reference to FIGS. 3 and 4. FIG. No.
The first LSI module 21 has a storage circuit including a flip-flop type circuit (hereinafter abbreviated as an FF circuit) 31 therein, and the second LSI module 22 has an F
The structure has a storage circuit including the F circuit 38. Since the FF circuit is originally composed of a large number of bits, there are as many FF circuits as the number of bits, but they are omitted here in FIGS. 3, 5, and 1. An output terminal 27 of the first LSI module 21 and an input terminal 28 of the second LSI module 22 are connected by a pattern on a printed circuit board.

[0004] In FIG. 4, t 0: clock repetition time t 1 : delay time until the data stored in the first LSI module 21 reaches the output terminal 27 t 2 : data of the clock with respect to the second LSI module 22 Setup time t3: pattern and second LSI module for clock signal 2a input to first LSI module 21
Lumpur 22 until the clock variation time Internal ta: 3, when the delay time between the terminal 27 to the terminal 28 is allowed to the data signal can be expressed as ta = t0 -t1 -t2 ± t3 . If t0 = 4 ns, the pattern length is limited to about 10 cm.

As a method for improving this, there is an interleaved circuit shown in FIG. The outline of the operation will be described below. Input data signal 1 (a, b, c, d,
e, f,...) are stored once in the FF circuit 31. On the other hand, the clock signal is frequency-divided by FF circuits 32 and 37, and Q outputs 4 and 10 are applied to FF circuits 33 and 35, and the other / Q outputs 5 and 11 are applied to FF circuits 34 and 36.
Therefore, the output signal 6 of the FF circuit 33 has data a, c,
.., and this becomes the input data signal of the FF circuit 35. Also, as the output signal 7 of the FF circuit 34, data b, d, f,... Are sequentially sent out, and this becomes the input data signal of the FF circuit 36. The output 8 of the FF circuit 35 and the output 9 of the FF circuit 36 are alternately selected by the multiplexer 39, and the output 12 of the output data sequence a, b, c,
are returned to d, e, f,... and input to the FF circuit 38. The FF circuit 38 stores this input data once at the timing of the clock 2b, and outputs its output 4 times from the original data.
Output as a signal of cycle delay.

The timing is shown in FIG. In FIG. 6, t1 ': FF circuit 3 inside the first LSI module 23
3, a delay time tb for the data stored at the output terminal 27 to reach the output terminal 27: In FIG. 5, when a delay time allowed for the data signal from the terminal 27 to the terminal 28 is set, it is regarded that t1 ′ ≒ t1. And tb = 2t0
−t1 −t2 ± t3, which is tb −
ta = t0 It is possible to lengthen the pattern by the time.

[0007]

[Problems to be Solved by the Invention] The first LSI module shown in FIG.
When the module 21 is compared with the first LSI module 23 in FIG. 5, the number of FF circuits is increased four times at a stroke.
Therefore, a basic cell (custom LSI) having four times the number of bits
(A basic unit of a cell for forming a circuit inside), which restricts configuring other functions inside the LSI. Therefore, the present invention provides a custom LSI that can reduce the number of basic cells used and maintain a required pattern length on a printed circuit board.
It is intended to provide.

[0008]

The storage circuit is not formed by the FF circuit, but is instead formed by the latch circuit.

[0009]

In order to configure one FF circuit with the internal circuit of the custom LSI, two basic cells are required, but the latch circuit can be configured by using only one basic cell. Therefore, one basic cell can be saved for one FF circuit.

[0010]

FIG. 1 shows an embodiment of the present invention. FIG. 2 shows the timing of FIG. First LSI module shown in FIG.
Yuru 23 to be respectively used in the second LSI modules within 24, FF circuits (33, 34) and FF circuits (35,
36) is replaced with the first LSI module 25 and the second
Latch circuit ( 41, 42 ) shown in SI module 26
Replacing each latch circuits (43, 44) and. The circuit operation of each unit is the same as that described with reference to FIG. The difference is that in FIG.
4 is that the signal a has already appeared. The period between the shaded portions 14 is a period in which when the input data signal 3 of the latch circuit 41 changes, the output signal 6 also changes in accordance with the change. 6 is determined. Therefore, when the signal 6 is determined by the edge 15, each of the LS
Delay time t of data inside the I module ( 21, 23 )
1 and t1 'can be regarded as nonexistent. In FIG. 2, the data delay time tc allowed from the terminal 27 to the terminal 28 is tc = t0−t2 ± t3. The reduction rate of Basic cell is the first LSI module
In the first LSI module 23
5%.

[0011]

[Effect of the invention] As shown above, the basic cell can be reduced by 25%. The custom LSI can be used for other functions. Further, in the pattern length on the printed circuit board, tc> ta was satisfied, and the pattern could be lengthened by an amount corresponding to t1 from ta.

[Brief description of the drawings]

FIG. 1 is a block diagram of a custom LSI circuit according to a first embodiment.

FIG. 2 is a diagram illustrating timings of a block diagram according to the first embodiment.

FIG. 3 is a block diagram of a circuit showing a first conventional example;

FIG. 4 is a diagram showing timings of a block diagram of a first conventional example.

FIG. 5 is a block diagram of a circuit showing a second conventional example.

FIG. 6 is a diagram showing timings of a block diagram of a second conventional example.

[Explanation of symbols]

Reference Signs List 1 input data 2 input clock 3 output signal of FF1 4 Q output signal of FF2 5 / Q output signal of FF2 6 input signal of FF35 7 input signal of FF36 8 output signal of FF35 9 output signal of FF36 10 Q output signal of FF37 11 / Q output signal of FF37 12 multiplexer output signal 13 output signal of FF38 14 period in which output of latch circuit 41 follows change of input 15 edge where clock transitions from low level to high level 21 Prior art example 1 The first LSI module 22 The second LSI module 23 of the prior art example 1 The first LSI module 24 of the prior art example 2 The second LSI module 25 of the prior art example 2 Implementation of the first LSI module 26 of the embodiment Example second LSI module 27 Output terminal of LSI module 28 L Input terminals of SI module 31, 32, 33, 34, 35, 36, 37, 38F
F circuit 39 Multiplexer 41, 42, 43, 44 Latch circuit

Claims (1)

(57) [Scope of request for utility model registration] 1. A constituting the interleave circuit inputs the clock signal and the data signal, the two LSI modules
Keep custom LSI circuit comprising, a clock signal first LSI module and the second LS
I module , and a data signal composed of a large number of bits as a continuous signal in synchronization with the clock signal is input to the first LSI module , and the data signal is input to the first LS module.
A circuit for storing in latch circuit in the I module, the output signal from the first LSI module corresponding to the data signal, the input data signals of the second LSI module, the input data signals a second LSI A custom LSI circuit, comprising: a circuit that stores data in a latch type circuit in the module .