JPH0720581U - Custom LSI circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] In a high-speed interleaved custom LSI used in an IC tester, the amount of basic cells in the custom LSI circuit is reduced to suppress redundancy and print. LSI on the board
It is an object of the present invention to provide a custom LSI that can secure a necessary and sufficient pattern length that connects the spaces. [Structure] Instead of forming a memory circuit inside a custom LSI circuit by a flip-flop type circuit, it is formed by a latch type circuit.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to a high speed and custom L SI circuit which is used for an IC tester and simultaneously processes many bits in parallel.

[0002]

[Prior art]

 In recent IC testers, the test speed has been increasing year by year, and some IC testers have a speed of several hundred MHz. As a matter of course, the repetition time of the basic clock such as internal sequence control and timing generator operates at a high speed of several nanoseconds. At the same time, custom LSIs are being used to increase the integration density and reduce the size. At this time, that is, at a high speed and when integrated into an LSI, it has become a problem how much the pattern length margin of the printed circuit board between the LSI modules can be obtained.

This will be described with reference to FIGS. 3 and 4. The custom LSI 21 has a storage circuit including a flip-flop type circuit (hereinafter abbreviated as FF circuit) 31 inside, and the custom LSI 22 has a structure including a storage circuit including an FF circuit 38 inside. Originally, since it is composed of a large number of bits, there are as many FF circuits as there are bits, but they are omitted here in FIGS. 3, 5, and 1. The output terminal 27 of the custom LSI 21 and the input terminal 28 of the custom LSI 22 are connected by a pattern on the printed circuit board.

In FIG. 4, t _{0 is a} clock repetition time t ₁ is a delay time until the data stored inside the LSI 21 reaches the output terminal 27 t ₂ is a data setup time for the clock in the LSI 22 t ₃ : LSI 21 The variation time of the clock between the pattern and the inside of the LSI 22 with respect to the clock signal 2a input to t _a : In FIG. 3, assuming that the delay time allowed for the data signal between the terminals 27 and 28 is t _a = It can be expressed as t ₀ −t ₁ −t ₂ ± t ₃ . If t ₀ = 4 nanoseconds, the pattern length is limited to about 10 cm.

As a method for improving this, there is an interleave system circuit shown in FIG. The outline of the operation will be described below. The input data signal 1 (a, b, c, d, e, f, ...) Is once stored in the FF circuit 31. On the other hand, the clock signal is divided in half by FF circuits 32 and 37, Q outputs 4 and 10 are given to FF circuits 33 and 35, and other / Q outputs 5 and 11 are given to FF circuits 34 and 36. Therefore, the output signal 6 of the FF circuit 33 becomes data a, c, e, ... And this becomes the input data signal of the FF circuit 35. Further, as the output signal 7 of the FF circuit 34, data b, d, f, ... Are sequentially sent out, and this becomes the input data signal of the FF circuit 36. The output 8 of the FF circuit 35 and the output 9 of the FF circuit 36 are alternately selected by the multiplexer 39, and the output 12 is restored to the original data sequence a, b, c, d, e, f, .... Is input to the FF circuit 38. The FF circuit 38 stores this input data once at the timing of the clock 2b, and outputs the output as a signal delayed by 4 cycles from the original data.

The timing is shown in FIG. In FIG. 6, t ₁ ': delay time until the data stored in the FF circuit 33 inside the LSI 23 reaches the output terminal 27 t _b : In FIG. 5, the data signal is allowed between the terminals 27 and 28. when the delay time, if regarded as _{t 1 '≒ t 1, t} b = 2t 0 -t 1 -t 2 ± t 3 next FIG 3 t _b -t _a = t ₀ hours than in the case of the pattern Can be lengthened.

[0007]

When the custom LSI 21 of FIG. 3 and the custom LSI 23 of FIG. 5 are compared, the number of FF circuits is increased four times at a stroke. Therefore, it is necessary to use four times as many basic cells (basic unit of cells to configure a circuit inside the custom LSI) as possible, which limits the configuration of other functions inside the LSI. I have done it. Therefore, an object of the present invention is to provide a custom LSI that can reduce the number of basic cells used and can also maintain a required pattern length on a printed circuit board.

[0008]

[Means for Solving the Problems]

 The memory circuit is stopped from being composed of the FF circuit, and the memory circuit is composed of the latch circuit instead.

[0009]

[Action]

 To configure one FF circuit with the custom LSI internal circuit, 2 Basic cells are required, but with the latch circuit, it can be configured by using only 1 Basic cell. Therefore, one Basic cell is saved for one FF circuit.

[0010]

【Example】

An embodiment of the present invention is shown in FIG. Moreover, the timing of FIG. 1 is shown in FIG. The FF circuits 33, 34, 35, 36 used in the custom LSIs 23, 24 shown in FIG. 5 are replaced with the latch circuits 41, 42, 43, 44 shown in the custom LSIs 25, 26 of FIG. The circuit operation of each unit is the same as that described with reference to FIG. The difference is that in the timing diagram 2, the signal a has already appeared in the shaded portion 14 of the signal 6. If the input data signal 3 of the latch circuit 41 changes, the output signal 6 also changes between the shaded portions 14, and the clock signal 2a is a signal at the edge 15 where the low level changes to the high level. 6 is confirmed. Therefore, when the signal 6 is determined by the edge 15, it can be considered that the delay time t ₁ or t ₁ 'of the data in the custom LSIs 21 and 23 mentioned above does not exist. In FIG. 2, the data delay time t _c allowed from the terminal 27 to the terminal 28 is t _c = t ₀ −t ₂ ± t ₃ . The reduction rate of the basic cell is 25% in the custom LSI 25 with respect to the custom LSI 23.

[0011]

[Effect of device]

As shown above, the basic cell can be reduced by 25%. This can be used for other functions in the custom LSI. Further, the pattern length on the printed circuit board was t _c > t _a , and the pattern could be made longer than t _a by _{a value} corresponding to t ₁ .

[Brief description of drawings]

FIG. 1 is a block diagram of a custom LSI circuit according to a first embodiment.

FIG. 2 is a diagram showing the timing of the block diagram of the first embodiment.

FIG. 3 is a block diagram of a circuit showing a first conventional technology.

FIG. 4 is a diagram showing a timing of a block diagram of a prior art example 1;

FIG. 5 is a block diagram of a circuit showing a second conventional technique.

FIG. 6 is a diagram showing a timing of a block diagram of a prior art example 2;

[Explanation of symbols]

1 Input data 2 Input clock 3 Output signal of FF1 4 Q output signal of FF2 5 / Q output signal of FF2 6 Input signal of FF35 7 Input signal of FF36 8 Output signal of FF35 9 Output signal of FF36 10 Output signal of FF37 11 / Q output signal of FF 37 12 output signal of multiplexer 13 output signal of FF 38 14 period during which output follows change of input in latch circuit 41 15 edge where clock shifts from low level to high level 21, 22 Prior Art Example 1 custom LSI circuit 23, 24 custom LSI circuit 25, 26 of prior art example 2 custom LSI circuit 27 embodiment custom LSI circuit output terminal 28 custom LSI circuit input terminal 31, 32, 33, 34, 35, 36 , 37, 38 F
F circuit 39 multiplexer 41, 42, 43, 44 latch circuit

Claims (1)

[Scope of utility model registration request] 1. In two custom LSI circuits for inputting a clock signal and a data signal to form an interleave circuit, the clock signal (2) is inputted to the custom LSI (25, 26) and the clock signal (2) is inputted. Data signal (1) consisting of multiple bits in a synchronized and continuous signal is custom L
A circuit for inputting to the SI (25) and storing the data signal in the latch type circuit (41, 42) and an output signal (6, 7) from the custom LSI (25) corresponding to the data signal are supplied to the custom LSI. (26) as an input data signal, and the input data signal is a latch type circuit (4
3, 44) and a circuit stored in the custom LSI circuit.