JP3431754B2 - Synchronous counter - Google Patents

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a general-purpose IC and ASI.
C relates to a synchronous counter used for pulse measurement.

[0002]

2. Description of the Related Art Conventionally, there are a ripple carry type counter and a parallel carry type counter as a synchronous type counter.
A ripple carry type counter is shown in FIG. In the ripple carry type counter, flip-flops are arranged for each digit, and a two-input AND gate is connected to the input of each digit flip-flop. Then, in the 2-input AND gate, the output of the AND gate of the previous digit is input to one input, and the output of the flip-flop of the previous digit is input to the other input. A parallel carry type counter is shown in FIG. In the parallel carry method, a counter having a multi-input AND gate that receives the outputs of all the flip-flops in the lower digits as input to the flip-flops in each digit is proposed.

[0003]

The above-described ripple carry method has the advantages that the hardware resources are reduced and the circuit structure is simplified, but the delay occurs due to the carry passing through a large number of gates. There is a problem that the clock frequency cannot be increased because the carry needs to propagate from the least significant bit to the most significant bit. FIG. 5 shows a timing waveform used in the conventional synchronous counter. The carry needs to propagate from the least significant bit to the most significant bit during the clock cycle Tc in the figure. On the other hand, in the parallel carry method, on the contrary, the number of gates that the carry needs to propagate in one clock is only one stage, which has the advantage that the clock frequency can be increased. As the number of input signals increases, the circuit configuration becomes more complicated. Therefore, LSI
When it is used inside a circuit, there is a problem in that the chip size of the LSI circuit becomes large, which deteriorates the yield and increases the manufacturing cost. An object of the synchronous counter according to the present invention is to provide a synchronous counter having a high clock frequency upper limit with a simple hardware configuration.

[0004]

A synchronous counter according to the present invention comprises a first counter composed of a first flip-flop group which outputs a lower digit and a second flip-flop group which outputs a higher digit. Is a synchronous counter that operates in synchronism with a common clock signal, wherein the first counter is a digit of the second counter when the logic of the first flip-flop group is complete. The carry-up signal is output, and the second counter outputs from the second flip-flop based on the carry signal from the first counter and the output signal from the lower digit in the second flip-flop group. It is characterized by

The second counter propagates the carry signal in the second counter to the most significant digit after the output of the carry signal is completed and before the output of the next carry signal is completed. The second counter is output when the output of the next carry signal is completed.

In the synchronous counter according to the present invention, the first counter is provided with a gate circuit on the output side of the flip-flop, in which all the outputs of the lower-order flip-flops are collected.
The second counter is provided with a first gate circuit which receives the output signal of a predetermined flip-flop and the signal from the first gate circuit of the one lower digit, and is provided with the carry signal and the first carry signal.
Is provided with a second gate circuit for inputting a signal from the gate circuit of 1 to output to a flip-flop of one upper digit.

[0007]

BEST MODE FOR CARRYING OUT THE INVENTION An up counter will be described below as an embodiment of the present invention. The structure of the synchronous counter according to the present invention is shown in FIG.

Here, in order to facilitate understanding, all flip-flops are T flip-flops. In this T flip-flop, when a clock is input when the T input is 1, the Q output is inverted at the rising edge of the clock. Even if a clock is input when the T input is 0, the Q output does not change.

As shown in FIG. 1, in the synchronous counter according to the present invention, a lower digit side counter 1 and an upper digit side counter 2 are provided.
It was divided into two parts. The lower digit side counter 1 is configured as a 3-bit parallel carry type synchronous counter.
On the other hand, the upper digit side counter 2 is composed of a synchronous counter as described below. Outputs q0, q1, q2, q3, q4, q from these two synchronous counters 1, 2
5, q6, q7, ... Are the outputs of the desired counter, and q0 is the least significant bit. Hereinafter, the structure of the synchronous counter will be described in detail.

A common clock is input to each flip-flop of the synchronous counters 1 and 2.

The lower digit side counter 1 is provided with three flip-flops 10, 11 and 12. The T input of the flip-flop 12 is a multi-input A whose inputs are outputs q0 and q1 of all the flip-flops 11 and 12 of lower digits.
The ND gate 21 is provided. In addition, a multi-input AND which receives the outputs of all the flip-flops 10, 11, and 12
A gate 22 is provided, and the output of the AND gate circuit 22 becomes the output of the lower digit side counter 1. Therefore, all the flip-flops 10, 11, of the lower digit side counter 1,
When the output of 12 becomes 1, the carry signal (hereinafter, Cy
1 is output to the (L) and is input to the upper digit side counter 2.

The high-order digit side counter 2 includes flip-flops 13, 14, 15, 16, 17, ...
Input AND gate circuits 23b, 24a, 24b ...
Is equipped with.

The output CyL is the upper digit side counter 2
Of the first-stage flip-flop 13 and all 2-input AND gates 23b, 24b, 25b, 26b, 27
It is connected to one input of b.

In the upper digit side counter 2, each two-input AND gate 23b, except for the flip-flop 13 at the first stage,
The outputs of 24b, 25b, 26b, 27b ... Are connected to the T inputs of the flip-flops 14, 15, 16, 17 ,.

Each 2-input AND in the upper digit side counter 2
The other inputs of the gates 24b, 25b, 26b, 27b ... Are two-input AND gates 24a, 25a, 26, respectively.
The outputs of a, 27a ... Are connected. However, the output of the flip-flop 13 is connected only to the other input of the first-stage two-input AND gate 23b.

Each 2-input AND in the upper digit counter 2
The outputs q4, q5, q6 of the flip-flops of the previous digit are input to one input of the gates 25a, 26a, 27a.
... are connected to the other input, and the outputs of the two-input AND gates 24a, 25a, 26a, ... Of the previous digit are connected to the other input. However, the input q of the first two-input AND gate 24a has the output q of the flip-flop 13 at the second previous digit.
3 and the output q4 of the flip-flop 14 of the previous digit are connected.

Next, the operation of the synchronous counter of the present invention will be described. FIG. 2 shows a diagram of a timing waveform of the synchronous counter according to the present invention.

When the lower digit side counter 1 is counted up by the clock input, waveforms q0, q1 and q2 of each bit are output as shown in FIG. When all of these 3 bits become 1, CyL is output as shown in FIG.
Since CyL is input to the AND gate b immediately before the T input of the flip-flop of each digit of the high-order digit side counter 2, when CyL is input, data is input to the flip-flop of each digit and it becomes t0. Sometimes, it is evaluated by each flip-flop. The period of the valid clock in the upper digit side counter 2 is limited to the time t0 when CyL falls.

When the output of a flip-flop in the high-order digit side counter 2 changes, the period during which the clock supplied to the flip-flop is valid is shown in FIG.
Although the time is Ts for only one clock, the propagation of data in the high-order side counter 2 is independent from the AND gate 24a,
25a, 26a ... Can be completed during the cycle Tp of CyL, and the AND gates 24a, 25a, 2
2 gates of AND gate 2 through 6a, 27a, ...
Input to 4b, 25b, 26b, 27b ...
In Tp period.

The T input of each flip-flop of the high-order digit side counter 2 has a logical sum formed by a 2-input AND gate circuit in a period Ts from t1 when CyL becomes 1 to t2 when CyL becomes 0 next. A signal is sent. Since the propagation of the data input to the flip-flop of the most significant bit is completed in the period of Tp, each AND gate 2 is operated in the period of Ts.
It suffices if there is time to pass through only one stage such as 4b or 25b.

The propagation of the carry signal in the counter 2 on the upper digit side starts from t0 in FIG. 2, and CyL becomes 1 at t1.
The time t2 is valid until the clock becomes valid, even after the clock becomes.

Thereafter, at time t2, the outputs are evaluated by the T flip-flop to determine the outputs q3, q4, q5, ....

By devising the carry propagation circuit in this way, the carry propagation time is not limited to the period of one clock, and the carry counter can operate as a complete synchronous counter even when it is longer than one clock.

The number of bits of the upper digit side counter 2 is AND
The carry time of the carriers passing through the gate a in sequence is set to be within the time Tp. When the carry propagation time exceeds Tp, the carry time can be doubled by increasing the number of bits of the high-order digit side counter 1 by one bit.

In the above embodiments, the up counter has been described as an example, but the down counter can be easily constructed by inverting the signal of the T input of each T flip-flop.
Further, as the flip-flop, in the present embodiment, a T flip-flop is used for simplification of description.
A flip-flop or a JK flip-flop can be similarly configured.

When this system is compared with the ripple carry system, the carry propagation from the lower flip-flop to the uppermost flip-flop of the ripple carry system is limited to the period Tc of one clock cycle. In the method, the CyL shown in FIG. 2 falls and the next rising CyL needs to be completed in the period of time Tp until it falls. In the present embodiment, there is a time margin of 8 times. This time depends on the number of bits in the counter,
Assuming that the number of bits of the lower digit side counter 2 is m, a time margin of 2 to the mth power is provided as compared with the ripple carry method, and the lower digit side counter 1 having a complicated circuit configuration has a small number of bits. Even if configured, a great effect can be obtained, and operation with a clock having a higher frequency becomes possible.

Therefore, the carry propagation time is longer than that of the conventional synchronous counter, the clock frequency of the counter can be increased many times, and a high-speed synchronous counter can be realized.

Further, when this system is compared with the parallel carry system, a counter having the same number of bits can be constructed with a smaller occupied area. Generally, A inside the LSI
The area of the ND gate is proportional to the number of input terminals of the AND gate. In the case of an n-bit parallel carry type synchronous counter, the total number of input terminals of the AND gate is 2 + 3 + 4 + 5 + ... + n≈n (n + 1) / 2, and the total number of input terminals of this type of synchronous counter is , (Number of input terminals of lower side counter) + 2 + 4 + 4 + 4 +
4 + ... + 4≈4n. From the above, it can be seen that as the number of bits of the counter increases, this method can reduce the occupied area of the input terminal in the LSI as compared with the parallel carry method.

[0029]

According to the synchronous counter of the present invention,
It is composed of a parallel carry type lower digit side counter capable of high-speed operation and an upper digit side counter having a simple circuit configuration although the output change is slow. The carry of the carry is completed in the flip-flop of the most significant bit while the value of the lower digit side counter makes one cycle, and the carry signal of the second counter which has completed the propagation is the maximum value of the lower digit side counter (down counter). In this case, the flip-flop is configured to be input when it reaches the minimum value). Therefore, it takes a sufficient time for the carry to propagate, and the upper limit of the clock frequency is set high even in the case of a synchronous counter with an extremely large number of digits. In addition, it can be realized with a simple circuit configuration.

[Brief description of drawings]

FIG. 1 is a diagram of a circuit configuration showing a synchronous counter according to the present invention.

FIG. 2 is a timing chart showing the operation of the synchronous counter according to the present invention.

FIG. 3 is a configuration diagram of a conventional ripple carry type synchronous counter.

FIG. 4 is a block diagram of a conventional parallel carry type synchronous counter.

FIG. 5 is a timing chart of a conventional synchronous counter.

[Explanation of symbols]

1 Lower digit side counter 2 Higher digit side counter 10-17 Flip-flops 21, 22, 24a to 27a, 23b to 27b AND
Gate circuit

Claims (2)

(57) [Claims] 1. A first counter comprising a first flip-flop group for outputting a lower digit and a second counter for outputting an upper digit.
A second counter consisting of a flip-flop group of
A synchronous counter that operates in synchronization with a common clock signal, wherein the first counter outputs a carry signal to the second counter when the logics of the first flip-flop group are aligned, The second counter is a second counter in the synchronous counter that outputs from the second flip-flop based on the carry signal from the first counter and the output signal from the lower digit in the second flip-flop group . The counter will not output the carry signal.
The second counter until the next carry signal is output.
Carry signal in the carrier up to the most significant digit and carry
The second counter is output when the output signal is completed.
A synchronous counter characterized in that 2. A first counter is provided with a gate circuit, on the output side of the flip-flop, which collects all the outputs of the lower-order flip-flops, and the second counter has an output signal of a predetermined flip-flop. A first gate circuit, which receives the signal from the first gate circuit of the one lower digit, is provided, and the carry signal and the signal from the first gate circuit are input, and a flip-flop of the one upper digit is provided. The synchronous counter according to claim 1, further comprising a second gate circuit for outputting to the.