JPH0668691A - Shift register circuit - Google Patents

Abstract

PURPOSE:To prevent malfunction of shifting operation caused by skewness of a clock signal, in a shift register circuit which operates with one phase clock. CONSTITUTION:A flip flop circuit 1 is constituted so that a flip flop circuit 2 is connected in series to a tristate buffer circuit 5 which is operated with a low enable signal. A flip flop circuit 2 is constituted so that a latch circuit 3 which is operated with the low enable signal is connected in series to a latch circuit 4 which is operated with a high enable signal. Consequently, even if skewness of a clock signal occurs in the flip flop circuit, since sufficient time for timing of half period of the clock signal is obtained, reliable shifting operation can be performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a shift register circuit, and more particularly to a shift register circuit operating with a one-phase clock, which prevents a malfunction of a shift operation caused by a skew of the shift clock.

[0002]

2. Description of the Related Art FIG. 6 is a block diagram of a conventional one-phase n-stage shift register circuit 100. Shift register circuit 1
A flip-flop circuit FF (j) (j = 1 to n) is connected in series with 00.

For example, (i-1) th flip-flop circuit FF (i-1), i-th flip-flop circuit FF
(i), (i + 1) th flip-flop circuit FF (i +
1) are connected in this order. Then, the input signal SI of the shift register circuit 100 is transmitted by the flip-flop circuit and output as the output signal SO. That is, the flip-flop circuits FF (i-1), FF (i), FF (i
+1) are the output signals SO (i-1), SO (i), SO (i
+1), but the output signals SO (i-1) and SO (i) are input waveforms SI (i) and SI (i + 1) of the flip-flop circuits FF (i) and FF (i + 1), respectively. ) Is also.

The shift clock SCK given to the shift register circuit 100 is propagated and given to each flip-flop circuit. For example, the flip-flop circuit FF (i
-1), FF (i), and FF (i + 1) are given shift clocks SCK (i-1), SCK (i), and SCK (i + 1), respectively.

FIG. 7 is a block diagram showing the configuration of a conventional flip-flop circuit 2 which constitutes the shift register circuit 100. The flip-flop circuit 2 is used for any of the flip-flop circuits FF (j) (j = 1 to n).

The flip-flop circuit 2 is composed of a latch circuit 3 which operates with a low enable signal and a latch circuit 4 which operates with a high enable signal, which are connected in series.

The flip-flop circuit 2 has a node A as an input section and a node C as an output section, and each has a latch circuit 3.
Coincides with the node of the input section of and the node of the output section of the latch circuit 4. The node of the output section of the latch circuit 3 and the node of the input section of the latch circuit 4 coincide at the node B. A shift clock is applied to each of the latch circuits 3 and 4, and when the flip-flop circuit 2 is used as the flip-flop circuit FF (j) in the shift register circuit 100, the shift clock SCK (j) is applied.

FIG. 8 is a timing chart showing the relationship between the shift clock SCK (j) given to the flip-flop circuit 2 and the data at the nodes A, B and C.

The latch circuit 3 uses the shift clock SCK (j)
The data c given to the node A at the falling edge of is input (time t10), and the data c is output to the node B (time t11). The latch circuit 4 uses the shift clock SCK
The data c given to the node B by the rising of (j) is input (time t20), and the data c is output to the node C (time t21). Therefore, it can be considered that the flip-flop circuit 2 operates as a whole at the rising timing of the shift clock SCK (j).

However, there is a delay in the latch circuits 3 and 4 in this way, and a delay occurs in the input and output of the flip-flop circuit 2. Therefore, such a flip-flop circuit 2
The operation of the shift register circuit 100, which is configured by the serial connection of, is as follows.

FIG. 9 shows a conventional one-phase shift register circuit 10
6 is a timing chart showing a relationship between a shift clock and an input / output signal given to a flip-flop circuit that configures 0. Flip-flop circuit FF (i-1), FF (i)
, FF (i + 1) respectively, the shift clock S
CK (i-1), SCK (i), SCK (i + 1) and their output signals SO (i-1), SO (i) (SI (i + 1)), SO (i +)
The relationship of 1) is shown. Data a, b, c, and d are sequentially input to the shift register circuit 100.

[0012]

In the configuration of the conventional flip-flop circuit 2, since two latch circuits 3 and 4 having different enable signal logics are connected in series, a delay occurs in the latch circuits 3 and 4. Therefore, there is a delay between the input and the output of the flip-flop circuit 2. On the other hand, due to wiring capacitance and resistance, the shift clock SCK
Skew also occurs in (j). Therefore, a malfunction may occur in the shift register circuit 100 including a plurality of flip-flop circuits 2 connected in series.

This will be described with reference to FIG. Shift clocks SCK (i-1), SCK (i), SC input to each flip-flop circuit FF (i-1), FF (i), FF (i + 1)
The time of the rising timing of K (i + 1) is t1 respectively.
, T2, t3 (t4, t5, t6), and skew has occurred.

The skew is small as t2-t1 (t5-t4), and the rising time t2 of the shift clock SCK (i) is calculated from the change of SO (i-1) output by the shift clock SCK (i-1). If it is also faster, the data b is input to the flip-flop circuit FF (i), shifted and output at the rising timing of SCK (i).

Similarly, at time t5, the data c propagates through the flip-flop circuit FF (i). The flip-flop circuit FF (i) to which the shift clock SCK (i) having a small skew is applied is
SI (i) is input at the rising edge of K (i) and SO (i)
Is normally shifted and output.

On the other hand, the skew is large as t6-t5 (t3-t2), and the rising time t6 of the shift clock SCK (i + 1) is determined from the change of SO (i) output by the shift clock SCK (i). Also consider the case when it is too late. In such a case, at time t6 when the shift clock SCK (i + 1) rises, the output signal SO (i) has already changed from the data b to the data c. Therefore, not the data b but the data c is input to the flip-flop circuit FF (i + 1), and the data is shifted and output. Similarly, at time t3, not the data a but the data b propagates through the flip-flop circuit FF (i + 1).

Therefore, when any of the shift clocks SCK (j) given to the respective flip-flop circuits FF (j) has a large skew, the shift register circuit 1
00 has a problem that a normal shift operation is not performed and a malfunction occurs.

The present invention has been made to solve the above problems, and an object thereof is to obtain a shift register circuit which does not malfunction even if the skew of the shift clock is large.

[0019]

A shift register circuit according to the present invention comprises a series connection of a plurality of flip-flop circuits which operate on the basis of a clock signal which makes first and second transitions. The flip-flop circuit is the first
The first signal transmitting means operating by the transition, the second signal transmitting means operating by the second transition, and the third signal transmitting means operating by the first transition are connected in series in this order. It has a different configuration.

Preferably, the third signal transmission means is a tristate buffer.

[0021]

The flip-flop circuit according to the present invention inputs data at the second transition of the clock signal and outputs data at the first transition of the clock signal.

[0022]

1 is a block diagram showing the configuration of a flip-flop circuit 1 used to construct a one-phase shift register circuit according to the present invention. The flip-flop circuit 1 is used for any of the flip-flop circuits FF (j) (j = 1 to n) that form a one-phase shift register circuit described later.

The flip-flop circuit 1 comprises a series connection of a flip-flop circuit 2 and a tri-state buffer circuit 5 which operates with a low enable signal.
The flip-flop circuit 2 is composed of a series connection of a latch circuit 3 that operates with a low enable signal and a latch circuit 4 that operates with a high enable signal.

The flip-flop circuit 1 has a node A as an input section and a node D as an output section, and each has a latch circuit 3.
And the node of the output section of the tri-state buffer circuit 5 coincides. The node of the output section of the latch circuit 3 and the node of the input section of the latch circuit 4 coincide at the node B. The node at the output of the latch circuit 4 and the node at the input of the tristate buffer circuit 5 coincide with each other at node C. A shift clock is given to all the latch circuits 3 and 4 and the tristate buffer circuit 5, and when the flip-flop circuit 1 is used as the flip-flop circuit FF (j) in the shift register circuit 100, the shift clock SCK (j ) Is given.

Further, the wiring capacitance 6 is parasitically connected to the flip-flop circuit 1 at the node D of the output section.

In FIG. 2, a shift clock SCK (j) given to the flip-flop circuit 1 and nodes A, B, C and D are shown.
6 is a timing chart showing the relationship with the data in FIG.

The latch circuit 3 uses the shift clock SCK (j)
The data c given to the node A is input at the falling edge of, and the data c is output to the node B (time ts
0). The latch circuit 4 inputs the data c given to the node B at the rising edge of the shift clock SCK (j) and outputs the data c to the node C (time ts1). Therefore, it can be considered that the flip-flop circuit 2 operates as a whole at the rising timing (time ts1) of the shift clock SCK (j).

Since the fall of the shift clock SCK (j) has not occurred between the time ts1 and the time ts2, the tristate buffer circuit 5 does not transmit data. On the other hand, since the latch circuit 4 has a delay, the output data of the latch circuit 4 is not output to the node D if the data output of the latch circuit 4 is between the time ts1 and the time ts2. At this time, the node D holds the previous data due to the capacitance 6 of the wiring.

In this way, the next fall of the shift clock SCK (j) occurs at the time ts2 where the data c is supplied to the node C, so that the tristate buffer circuit 5 operates and the data c To node D. In other words, the data of node C is the data of node D
The data output to the node D and given to the node D will be updated.

From the above, it can be considered that the flip-flop circuit 1 operates to input data at the rising edge of the clock and output data at the falling edge of the clock.

FIG. 3 is a block diagram of a one-phase n-stage shift register circuit 200 formed by connecting the flip-flop circuits 1 having the above structure in series. The shift register circuit 200 includes a flip-flop circuit FF (j) (j = 1 to 1
n) connected in series. Each of the flip-flop circuits FF (j) (j = 1 to n) is composed of the flip-flop circuit 1.

For example, the i-th flip-flop circuit FF
(i), (i + 1) th flip-flop circuit FF (i +
1) are connected in this order. The input signal SI of the shift register circuit 200 is transmitted by the flip-flop circuit and output as the output signal SO. That is, the flip-flop circuits FF (i) and FF (i + 1) output the output signals SO (i) and SO (i + 1), respectively, but the output signal SO (i) outputs the flip-flop circuit FF (i + 1). ) Input waveform SI (i + 1).

The shift clock SCK given to the shift register circuit 200 is propagated and given to each flip-flop circuit. For example, flip-flop circuit FF
(i) and FF (i + 1) each have a shift clock SCK.
(i) and SCK (i + 1) are given.

FIG. 4 is a timing chart showing the relationship between the shift clock and the input / output signals applied to the flip-flop circuit which constitutes the one-phase shift register circuit 200 shown in FIG. Flip-flop circuit FF (i),
Shift clock SCK given to FF (i + 1) respectively
(i), SCK (i + 1) and their output signals SO (i) (S
I (i + 1)), SO (i + 1). Data a, b, c, d are sequentially input to the shift register circuit 200.

Shift clock SCK at time tm1
(i) rises, and the data c is read in the flip-flop circuit FF (i). However, since the output signal SO (i) of the flip-flop circuit FF (i) is output at the falling timing of the shift clock SCK (i), the shift clock S falling at the time tm3.
The previous data b is output until the data is updated by CK (i) at time tm4.

By the way, shift clock skew occurs due to wiring capacitance and resistance. Therefore, the rising edge of the shift clock SCK (i + 1) occurs at time tm2. The shift clock SCK (i + 1) is given to the flip-flop circuit FF (i + 1), and the flip-flop circuit F
F (i + 1) is the output signal S of the flip-flop circuit FF (i)
O (i) is received as an input signal SI (i + 1). Therefore, in order for the shift register circuit 200 to perform a normal shift operation, a certain margin is required for the skew of the shift clock SCK (i + 1).

That is, the rising time tm2 of the shift clock SCK (i + 1) is earlier than the change time tm4 of the output signal SO (i) (SI (i + 1)) output by the flip-flop circuit FF (i). If so, the normal shift operation of the shift register circuit 200 is ensured.

In the present invention, as described above, the shift clock SCK (i) falling at the time tm3 causes the shift to the time t.
Until the data is updated in m4, output signal SO
(i) (SI (i + 1)) holds the previous data b. Therefore, if the rising time tm2 of the shift clock SCK (i + 1) is at least earlier than the falling time tm3 of the shift clock SCK (i), the correct shift operation is performed.

Therefore, even if there is a skew of the shift clock between the flip-flop circuits, at least a half cycle of the shift clock can provide a timing margin, so that a malfunction in the shift register circuit 200 can be avoided and a normal shift operation can be performed. You can do it.

In the above embodiment, in the flip-flop circuit 1 constituting the shift register circuit 200, the latch circuit 3 and the tri-state buffer circuit 5 operate with a low enable signal and the latch circuit 4 operates with a high enable signal. However, these logics may be reversed.

FIG. 5 shows this, and is a block diagram showing the configuration of the flip-flop circuit 11. The flip-flop circuit 11 is a shift register circuit 200.
Of the flip-flop circuit FF (j) (j = 1 to n).

The flip-flop circuit 11 comprises a series connection of a flip-flop circuit 21 and a tri-state buffer circuit 51 which operates with a high enable signal. The flip-flop circuit 21 is composed of a series connection of a latch circuit 4 which operates with a high enable signal and a latch circuit 3 which operates with a low enable signal.

The flip-flop circuit 11 has an input node A and an output node D, and the input node of the latch circuit 4 and the tristate buffer circuit 5 respectively.
1 corresponds to the node of the output section. The node of the output section of the latch circuit 4 and the node of the input section of the latch circuit 3 are node B.
Matches with. The node at the output of the latch circuit 3 and the node at the input of the tristate buffer circuit 51 coincide with each other at node C. A shift clock is applied to any of the latch circuits 3 and 4 and the tristate buffer circuit 51, and the flip-flop circuit 11 shifts to the shift register circuit 2.
When used as the flip-flop circuit FF (j) in 00, the shift clock SCK (j) is given.

It can be considered that the flip-flop circuit 11 configured as described above operates to input data at the falling edge of the shift clock and output data at the rising edge of the shift clock. Therefore, even when these are connected in series to configure the shift register circuit 200, the same effect as that of the above-described embodiment can be obtained.

[0045]

As described above, according to the present invention, even if there is a skew of the clock signal between the flip-flops, at least a half cycle of the timing of the clock signal can be obtained, and a reliable shift operation can be performed. That is, it is possible to prevent the shift operation of the shift register from malfunctioning due to the skew of the clock signal.

[Brief description of drawings]

FIG. 1 is a block diagram of a flip-flop circuit showing an embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the flip-flop shown in FIG.

FIG. 3 is a block diagram of a shift register circuit showing an embodiment of the present invention.

FIG. 4 is a timing chart showing an operation of the shift register circuit shown in FIG.

FIG. 5 is a block diagram of a flip-flop circuit showing another embodiment of the present invention.

FIG. 6 is a block diagram of a conventional shift register circuit.

FIG. 7 is a block diagram of a conventional flip-flop circuit.

FIG. 8 is a timing chart showing the operation of a conventional flip-flop circuit.

FIG. 9 is a timing chart showing an operation of a conventional shift register circuit.

[Explanation of symbols]

1, 2 Flip-flop circuit 3, 4 Latch circuit 5 Tri-state buffer SCK, SCK (i-1), SCK (i), SCK (i + 1) Shift clock FF (i-1), FF (i), FF (i + 1) flip-flop circuit

Claims (2)

[Claims] 1. A shift register circuit comprising a series connection of a plurality of flip-flop circuits that operate based on a clock signal that performs first and second transitions, wherein the flip-flop circuit comprises the first transitions. A first signal transmitting means operating according to the second transition, a second signal transmitting means operating according to the second transition, and a third signal transmitting means operating according to the first transition are connected in series in this order. Shift register circuit having the above configuration. 2. The shift register circuit according to claim 1, wherein the third signal transmission means is a tri-state buffer.