GB2276474A - Shift register with delay matching clock buffer - Google Patents
Shift register with delay matching clock buffer Download PDFInfo
- Publication number
- GB2276474A GB2276474A GB9404474A GB9404474A GB2276474A GB 2276474 A GB2276474 A GB 2276474A GB 9404474 A GB9404474 A GB 9404474A GB 9404474 A GB9404474 A GB 9404474A GB 2276474 A GB2276474 A GB 2276474A
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- GB
- United Kingdom
- Prior art keywords
- flip
- flop
- stage
- input end
- logic circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
Description
2276474 LOGIC CIRCUIT WITH MULTI-STAGE KASTER/SLAVE D FLIP-FLOPS
BACKGROUND OF THE INVENTION
The present invention relates to a logic circuit with multi-stage master/slave D flip-flops.
FIG. 8 shows a shift register 10A in which n stage of master/slave D flipflops 11 to ln are connected In cascade. The clock signal CK is supplied commonly to the clock input end C of each D flip-flop 11 to 1n. In practise, however, because of the difference in the length of the line from the output end of a timing generator to the clock input end C, of each of the D flip-flops 11 to 1n, the timing of the clock signal supplied to the clock input end C is not the sam for each. This presents a possible cause of erroneous operation when the clock frequency is Increased.
In order to prevent such erroneous operation, in the prior art, the clock CK is supplied to the clock input end C of the D flip-flop 11 via a delay circuit 21 (1 = 1 to n) as shown in FIG. 9 and by connecting delay circuit 31 between the non-inverse output end of the D flip-flop li-1 and the data input end D of the D flip-flop li, the timing of the clock for the input data is adjusted for each D flip-flop.
The maximum operating frequency, fmax, of the shift register 10B is expressed as fmax = 1/(tp + t, + t,),... (1) where, tF: propagation delay time of D flip-flop from clock input to data output, to: setup time of D flip-flop, and tn: propagation delay time of delay circuit 31.
As is clear from the formula (1), by connecting the delay circuits 3i between the D flip-flops, the fmax is reduced.
FIG. 10 shows a pattern generating circuit 10C in the prior art. In this circuit, the D flip-flops 11 to 16 are connected in cascade, the output D03 of the D flip-flop 13 and the output D04 of the D flip-flop 14 are supplied to the combinational logic circuit LC and the output of the combinational logic circuit LC is fed back to the data input end D of the D flip-flop 11. By supplying the clock signal CK commonly to the clock input end C of each of the D flip-flops 11 to 16, a specific pattern is output from the non-inverse output end of the D flipflop 16. When the propagation delay time of the logic circuit LC is tL and the hold time of the D flip-flop is tH, the maximum operating frequency, fmax, of this pattern generating circuit 10C is expressed as flnaX 1/(tP to ' tH 'I' tL) (2) As is clear from the formula (2), the fmax is reduced due to the propagation delay time tL of the logic circuit LC.
SUMARY OF THE INVENTION
Accordingly, an object of the present invention is to improve the maximum operating frequency of the logic circuit with multi-stage master/slave D flip-flops.
According to the first aspect of the present invention, there is provided a logic circuit with n stages of master/slave D flip-flops connected in cascade, comprising: n-1 stages of first buffer gates connected in cascade directly, the i-th stage of the first buffer gates being connected at its output end to a clock input end of the (i+l)-th stage D flip-flop for each i that is 1 to n-1, the first stage of the first buffer gates being connected at its input end to a clock input end of the first stage D flip-flop, the propagation delay time of the 1-th stage of the first buffer gates being approximately equal to the propagation delay time from a data input end of the i-th stage D flip-flop to a data input end of th (i+l)-th D flip-flop for each i that is 1 to n-l. - The maximum operating frequency, fmax, of this logic circuit is approximately fmax = l/to when the setup time of the D flip-flop is to. The fmax is determined solely by the setup time to of the D flip-flop. Since, generally speaking, the setup time to is considerably less than the propagation delay time tr of the D flip-flop, it becomes possible to greatly improve the fmax in comparison with what has been possible in the prior art.
In the first form of the first aspect of the invention, the output end of the i-th stage D flip-flop is directly connected to the data input end of the (i+l)-th D flip-flop for each i that is 1 to n-1, and the propagation delay time of the i-th stage of the first buffer gates being approximately equal to the propagation delay time of the i-th stage D flip-flop for each i that is 1 to n-l.
The second form of the first aspect of the invention further comprises: n1 combinational logic circuits the i-th of which is connected at its input end to the output end of the i-th stage D flip-flop and at its output end to the data input end of the (i+l)-th D flip-flop for each i that is 1 to n-1, the propagation delay time of the i-th combinational logic circuit being approximately equal to the difference between that of the i-th stage of the first buffer gates and that of the 1-th D flip-flop for each i that is 1 to n-l.
In the third form of the first aspect of the invention, the n combinational logic circuits are n selectors each of which has a control input end to which a selection control signal is supplied so as to output one of input signals, the third form further comprises: n-1 stages of second buffer gates connected in cascade directly, the i-th stage of the first buffer gates being connected at its output end to the control input end of the i-th selector for each i that Is 1 to n-1, the selection control signal being input an input end of the first stage of the second buffer gates, the propagation delay time of the i-th stage of the second buffer gates being approximately equal to that of the i-th stage of the first buffer gates for each i that Is 1 to n-l.
The fourth form of the first aspect of the invention further comprises for each i that is 1 to n-l: n-i stages of third buffer gates connected in cascade, Input end of the third buffer gates being connected to the output end of the i-th stage D flip-flop, the propagation delay time of the third buffer gates and the n stages of master/slave D flip-flops being approximately equal to each other, whereby a parallel data being output from the output ends of both the third buffer gates and the n-th stage D flip-flop, matching output timing of all bits of the parallel data.
According to the second aspect of the present invention, there is provided a logic circuit with n stages of master/slave D flip-flops connected In cascade and a combinational logic circuit connected at its input end to an output end of the j-th stage D flip-flop and at its output end to a data input end of the i-th D flip-flop, where i and j satisfy a relation 1 5 i < j:5 n, comprising: a buffer gate connected at its output end to a clock input end of the i-th stage D flip- flop and at its input end to a clock line; and a clock line connected to an input end of the buffer gate and to a clock input end of the J-th stage D flip-flop directly.
With this, the maximum operating frequency, fmax, of the logic circuit can be improved.
According to the third aspect of the present invention, there is provided a semiconductor integrated circuit comprising anyone of above-described logic circuit.
Detail features and advantages of the present invention will become apparent from the following description of the preferred embodiments when the same is read in conjunction with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a circuit diagram showing a shift register of the first embodiment of the present invention; FIG. 2 is a timing chart illustrating the operation of the circuit in FIG. 1; FIG. 3 is a diagram showing a logic circuit of the second embodiment of the present invention; FIG. 4 is a circuit diagram showing a shift register of the third embodiment of the present invention; FIG. 5 is a diagram showing a pattern generating circuit of the fourth embodiment of the present Invention; -7 FIG. 6 is a diagram showing a pattern generating circuit of the fifth embodiment of the present invention; FIG. 7 is a circuit diagram showing a shift register of the sixth embodiment of the present invention; FIG. 8 is a circuit diagram showing a shift register of the prior art;
FIG. 9 is a circuit diagram showing another shift register of the prior art; and
FIG. 10 is a diagram showing a pattern generating circuit of the prior art.
DESCRIPTION OF THE PREFERRED EMBODIMENT First Embodimen
FIG. 1 shows a shift register 10D in which n stages of master/slave D flip-flops 11 to ln are connected in cascade.
The output end of the non-inverse buffer gate 4i for delay is connected to the clock input end C of the D flip-flop li (i = 2 to n) and the input end of the non-inverse buffer gate 4i is connected to the clock input end C of the D flip-flop li-1. The D flip-flops 11 to ln have identical characteristics each other and likewise, non-inverse buffer gates 42 to 4n have identical characteristics each other. The outputs of the D flip- flop 11 and the non-inverse buffer gate 4i+l, when the data DI and -a- the clock CK are supplied to the data input end D and the clock input end C respectively of the D flip-flop 11, are represented D0i and CM respectively.
FIG. 2 is a timing chart that illustrates the operation of the circuit shown in FIG. 1. In FIG. 2; t,: propagation delay time of D flip-flop from clock input to data output, to: setup time of the D flip-flop, tu: hold time of the D flip-flop, and to: propagation delay time of the non-inverse buffer gate 41.
The maximum operating frequency, fmax, of the shift register 10D is expressed as fmax = 11 (t, + to - t,).... (3) By setting circuit constants so that th will equal to tr, the formula (3) can now be simply expressed as fmax = llto.... (4) As a result, the maximum operating frequency, fmax, is determined solely by the setup time to of the D flip-flop li. Since the setup time to is generally much shorter than the propagation delay time tr of the D flip- flop, the maximum operating frequency, fmax, is greatly improved in comparison with the prior art.
1 -g- Second Embodiment FIG. 3 is a diagram of a logic circuit 10E of the second embodiment. Components identical to those in FIG. 1 are designated with the same reference characters.
In this circuit, a combinational logic circuit 5i+l is connected between the noninverse output end 0 of the D flip-flop li and the data input end D of the D flip-flop li+1. All other aspects of the structure of this embodiment are identical to the circuit shown In FIG. 1. With the propagation delay time for each logic circuit 51 designated as tL, the maximum operating frequency, fmax, of the logic circuit 10E is expressed as fmax = l/ (t, + t, + t, - t,).... (5) By setting the circuit constants so that tz is equal to ty + tL, this formula becomes identical to the earlier formula (4) and, just as in the first embodiment described above, the fmax is greatly improved in comparison with the prior art.
Third Embodiment FIG. 4 shows shift register 1OF of the third embodiment. Components identical to those in FIG. 1 are designated with the same reference characters.
In this circuit, one of the two input ends to the selector 61 is connected to the non-inverse output end of the D flip-flop li-1 and the set data Di is supplied to the other input end. The output end of the selector 61 is connected to the data input end D of the D flip-flop li. Also, the non-inverse buffer gates 72 to 7n for delay are connected in cascade and the output end of the non-inverse buffer gate 71 is connected to the selection control input end of the selector 61. The non-inverse buffer gates 42 to 4n and 72 to 7n have identical characteristics each other.
When the selection control signal SL, which is supplied to the input end of the non-inverse buffer gate 72, is set to low, the selector 61 selects the output of the D flip-flop li-1 and when the selection control signal SL is set to high, the selector 61 selects the set data Di.
The propagation delay time of the selector 6i is designated as t,,. When the propagation delay times ta of both the non-inverse buffer gates 4i and 7i are the same value, the maximum operating frequency, fmax, of the shift register 1OF is expressed as fmax = 1/(tp + t, + teL - tz).... (6) By setting the circuit constants so that ta is equal to ty + ton, the formula (6) becomes identical to the earlier formula (4) and, just as in the first embodiment described above, the fmax is greatly improved in comparison with the prior art.
Fourth Embodiment FIG. 5 shows the pattern generating circuit 1OG of the fourth embodiment. Components identical to those in FIG 10 are designated with the same reference characters.
The difference between this pattern generating circuit 1OG and the pattern generating circuit 10C shown in FIG. 10 is that in this circuit, a non-inverse buffer gate 81 for delay is connected to the clock input end C of the D flip-flop 11 to which the output from the combinational logic circuit LC is fed back. The maximum operating frequency, fmax, of the pattern generating circuit 1OG is the smaller value of the two values expressed as fmax 1 = 1/(t,+ to + tH + t, - to), fmax 2 = 1/(tp + to + tH + to).... (8) The fmax is the largest when to tL/2 and the fmax at this point is expressed as fmax 2 = l/ (ty + to + tx + tL/2).... (9) Whereas the maximum operating frequency, fmax, for the pattern generating circuit in FIG. 10 is expressed with the earlier formula (2).
As is obvious from the formulae (9) and (2), with this fourth embodiment, the fmax is improved in comparison with the prior art.
Fifth Embodiment FIG. 6 shows the pattern generating circuit 10H of the fifth embodiment. Components identical to those in FIG. 5 are designated with the same reference characters.
In this circuit, the clock input end C of the D flip-flops 11, 12, 15 and 16 are connected with the output ends of non-inverse buffer gates for delay 81, 82, 85 and 86 respectively. The input end of the non-inverse buffer gates 81, 82, 85 and 86 and the clock input ends C of the D flipflops 13 and 14 are commonly connected and the clock CK is commonly supplied to them. The non-inverse buffer gates 81, 82, 85 and 86 have identical characteristics each other.
The maximum operating frequency, fmax, of the pattern generating circuit 10H is the same as in the fourth embodiment above.
FIG. 7 shows the shift register lOI of the sixth embodiment. Components identical to those in FIG. 1 are designated with the same reference characters.
Here, the difference from the circuit shown in FIG. 1 is that n-i stages of non-inverse buffer gates 9n-i for delay are connected to the noninverse output end of the D flip-flop li and the output D0i is taken from the non-inverse buffer gates 9n-i. In this manner, the timing for data D01 to DOn output from the output ends of the non-inverse buffer gates 9n- 1 to 91 and the D flip-flop ln can be made to match.
Having described specific embodiments of the present invention, it is to be understood that modification and variation of the invention are possible without departing from the spirit and scope thereof.
Claims (20)
1. A logic circuit with n stages of master/slave D flip-flops connected in cascade, comprising:
n-1 stages of first buffer gates connected in cascade directly, the i-th stage of said first buffer gates being connected at its output end to a clock input end of the (i+l)-th stage D flip-flop for each i that is 1 to n-1, the first stage of said first buffer gates being connected at its input end to a clock input end of the first stage D flip-flop.
2. A logic circuit according to claim 1, wherein a propagation delay time of said i-th stage of said first buffer gates is approximately equal to a propagation delay time from a data input end of said i-th stage D flip-flop to a data input end of said (i+l)-th D flip-flop for each i that is 1 to n-l.
3. A logic circuit according to claim 2, wherein the output end of said i-th stage D flip-flop is directly connected to the data input end of said (1+1)-th D flip-flop for each i that is 1 to n-1, and a propagation delay time of the i-th stage of said first buffer gates being approximately equal to a propagation delay time of the i-th stage D flip-flop for each i that is 1 to n-l.
4. A logic circuit according to claim 2, further comprising:
n-1 combinational logic circuits the i-th of 1 -'R is connected at its input end to the output end of said i-th stage D flip-flop and at its output end to the data input end of said (i+l)-th D flip-flop for each 1 that is 1 to n-1, a propagation delay time of said i-th combinational logic circuit being approximately equal to a difference between that of the i-th stage of said first buffer gates and that of the i-th D flip-flop for each i that is 1 to n-l.
5. A logic circuit according to claim 4, wherein said n combinational logic circuits are n selectors each of which has a control input end to which a selection control signal is supplied so as to output one of input signals, further comprising:
n-1 stages of second buffer gates connected in cascade directly, the i-th stage of said first buffer gates being connected at its output end to said control input end of the i-th selector for each i that is 1 to n-1, said selection control signal being input to an input end of the first stage of said second buffer gates, a propagation delay time of the i-th stage of said second buffer gates being approximately equal to that of the i-th stage of said first buffer gates for each i that is 1 to n-l.
6. A logic circuit according to claim 2, further comprising for each i that is 1 to n-l:
n-i stages of third buffer gates connected in cascade, input end of said third buffer gates being connected to the output end of said i-th stage D flip-flop, a propagation delay time of said third buffer gates and said n stages of master/slave D flip- flops being approximately equal to each other, whereby a parallel data being output from the output ends of both said third buffer gates and the n-th stage D flip-flop, matching output timing of all bits of the parallel data.
7. A logic circuit according to claim 3, further comprising for each i that is 1 to n-l:
n-i stages of third buffer gates connected in cascade, input end of said third buffer gates being connected to the output end of said i-th stage D flip-flop, a propagation delay time of said third buffer gates and said n stages of master/slave D flip-flops being approximately equal to each other, whereby a parallel data being output from the output ends of both said third buffer gates and the n-th stage D flip-flop, matching output timing of all bits of the parallel data.
8. A logic circuit according to claim 4, further comprising for each i that is 1 to n-l:
n-i stages of third buffer gates connected in cascade, input end of said third buffer gates being connected to the output end of said i-th stage D flip-flop, the Y:
z!, m -17 propagation delay time of said third buffer gates and said n stages of master/slave D flip-flops being approximately equal to each other, whereby a parallel data being output from the output ends of both said third buffer gates and the n-th stage D flip-flop, matching output timing of all bits of the parallel data.
9. A logic circuit according to claim 5, further comprising for each i that is 1 to n-l:
n-i stages of third buffer gates connected in cascade, input end of said third buffer gates being connected to the output end of said 1-th stage D flip-flop, the propagation delay time of said third buffer gates and said n stages of master/slave D flip-flops being approximately equal to each other, whereby a parallel data being output from the output ends of both said third buffer gates and the n-th stage D flip-flop, matching output timing of all bits of the parallel data.
10. A logic circuit with n stages of master/slave D flip-flops conner-ted in cascade and a combinational logic circuit connected at its input end to an output end of the j-th stage D flip-flop and at its output end to a data input end of the i-th D flip-flop, where 1 and j satisfy a relation 1 5 1 < j 5 n, comprising:
a buffer gate connected at its output end to a clock input end of the ith stage D flip-flop and at its input end to a clock line; and a clock line connected to an input end of said buffer gate and to a clock input end of the J-th stage D flip-flop directly.
11. A logic circuit according to claim 10, wherein a propagation delay time of said buffer gate is approximately a half of that of said combinational logic circuit.
12. A logic circuit according to claim 11, further comprising for each i that is 1 to n-l:
n-i stages of third buffer gates connected in cascade, input end of said third buffer gates being connected to the output end of said i-th stage D flip-flop, the propagation delay time of said third buffer gates and said n stages of master/slave D flip-flops being approximately equal to each other, whereby a parallel data being output from the output ends of both said third buffer gates and the n-th stage D flip-flop, matching output timing of all bits of the parallel data.
13. A logic circuit with n stages of master/slave D flip-flops connected in cascade, comprising:
a buffer gate connected at its input end to a clock Input end of the first stage D flip-flop and at its output X m end to a clock input end of other stage D flip-flop than said first stage D flip-flop.
14. A semiconductor integrated circuit comprising said logic circuit of claim 2.
15. A semiconductor integrated circuit comprising said logic circuit of claim 3.
16. A semiconductor integrated circuit comprising said logic circuit of claim 4.
17. A semiconductor integrated circuit comprising said logic circuit of claim 5.
18. A semiconductor integrated circuit comprising said logic circuit of claim 6.
19. A semiconductor integrated circuit comprising said logic circuit of claim 10.
20. A semiconductor integrated circuit comprising said logic circuit of claim 12.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5058468A JPH06276062A (en) | 1993-03-18 | 1993-03-18 | Logic circuit with master/slave type d flip-flops connected in plural stages |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB9404474D0 GB9404474D0 (en) | 1994-04-20 |
| GB2276474A true GB2276474A (en) | 1994-09-28 |
Family
ID=13085269
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9404474A Withdrawn GB2276474A (en) | 1993-03-18 | 1994-03-08 | Shift register with delay matching clock buffer |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JPH06276062A (en) |
| DE (1) | DE4409371A1 (en) |
| GB (1) | GB2276474A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1096506B1 (en) * | 1999-10-29 | 2008-12-10 | Nec Corporation | Shift register allowing direct data insertion |
| EP2212996A1 (en) * | 2007-09-24 | 2010-08-04 | QUALCOMM Incorporated | Delay circuits matching delays of synchronous circuits |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE4422784C2 (en) * | 1994-06-29 | 1999-05-27 | Texas Instruments Deutschland | Circuit arrangement with at least one circuit unit such as a register, a memory cell, a memory arrangement or the like |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4843254A (en) * | 1987-03-02 | 1989-06-27 | Oki Electric Industry Co., Ltd. | Master-slave flip-flop circuit with three phase clocking |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04106798A (en) * | 1990-08-27 | 1992-04-08 | Oki Electric Ind Co Ltd | Shift register circuit |
-
1993
- 1993-03-18 JP JP5058468A patent/JPH06276062A/en not_active Withdrawn
-
1994
- 1994-03-08 GB GB9404474A patent/GB2276474A/en not_active Withdrawn
- 1994-03-18 DE DE19944409371 patent/DE4409371A1/en not_active Withdrawn
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4843254A (en) * | 1987-03-02 | 1989-06-27 | Oki Electric Industry Co., Ltd. | Master-slave flip-flop circuit with three phase clocking |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1096506B1 (en) * | 1999-10-29 | 2008-12-10 | Nec Corporation | Shift register allowing direct data insertion |
| EP2212996A1 (en) * | 2007-09-24 | 2010-08-04 | QUALCOMM Incorporated | Delay circuits matching delays of synchronous circuits |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH06276062A (en) | 1994-09-30 |
| DE4409371A1 (en) | 1994-09-22 |
| GB9404474D0 (en) | 1994-04-20 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |