DE4409371A1 - Logical circuit with multi-stage master-slave D flip-flops - Google Patents

Abstract

For each flip-flop stage 1i (i = 1 to n-1) the output end of the i-th stage D flip-flop 1i is connected to the data input end D of the stage (i+1) D flip-flop 1i+1 and the output end of the buffer gate 4i+1 is connected to the clock input end C of the stage (i+1) D flip-flop 1i+1. The propagation delay time of the buffer gate 4i+1 is the same as that of the D flip-flop 1i. The maximum operating frequency for such a shift register is equal to 1/ts, where ts is the setup time of the D flip-flop. Also disclosed is an arrangement including combination logic between each of the flip-flop stages and also an arrangement including only one matching buffer connected to the first stage and feedback from later stages. <IMAGE>

Description

The invention relates to a logic circuit with multi-stage master-slave D flip flops

Fig. 8 shows a shift register 10 A, in which n stages of master-slave D flip-flops 11 to 1n are connected in cascade. The clock signal CK is commonly supplied to the clock input terminal C of each D flip-flop 11 to 1n. Due to the different line lengths from the output terminal of a clock generator to the clock input terminal C of each D flip-flop 11 to 1n, the timing of the clock signals which are supplied to the clock input terminal C is not the same for everyone. With a reduced clock frequency, this leads to a possible cause of incorrect operation.

To prevent such an erroneous operation, the clock CK is supplied to the clock input terminal C of the D flip-flop 1 i via a delay circuit 2 i (i = 1 to n), as shown in FIG. 9, and by connecting one in the prior art Delay circuit 3 i between the non-inverting output terminal of the D flip-flop 1 i-1 and the data input terminal D of the D flip-flop 1 i is adapted to the timing of the clock for the input data for each D flip-flop.

The maximum operating frequency fmax of the shift register 10 B is with

fmax = 11 (t _F + t _S + t _D ). . .(1)

spent, where
t _F : the stage delay time of the D flip-flop from the clock input to the data output,
t _S : the response time of the D flip-flop and
t _D : the step delay time of the delay circuit 3 i.

From formula ( 1 ) it is clear that the connection of the delay circuits 3 i between the D flip-flops of the fmax is reduced.

Fig. 10 shows a pattern generating section 10 C of the prior art. In this circuit, the D flip-flops 11 to 16 are connected in cascade, the output signal DO3 of the D flip-flop 13 and the output signal DO4 of the D flip-flop 14 being supplied by means of the logic combination circuit LC and the output signal of the logic combination circuit LC being supplied to the data input terminal D. of the D flip-flop 11 is returned. By jointly supplying the clock signal CK to the clock input terminal C of each of the D flip-flops 11 to 16 , a specific pattern is output from the non-inverting output terminal of the D flip-flop 16 . If the step delay time of the logic circuit is LC t _L and the hold time of the D flip-flop is T _H , the maximum operating frequency fmax of this pattern generation circuit 10 C with

fmax = 1 / (t _F + t _S + t _H + t _L ). . . (2)

spent.

From the formula ( 2 ) it is clear that fmax is reduced due to the step delay time t _{L of} the logic circuit LC.

It is therefore an object of the invention to determine the maximum operating frequency of the multi-stage Master-slave D flip-flops to improve logic circuit.

According to a first embodiment of the invention, a logic circuit is included n stages of master-slave D flip-flops are provided, which are connected in cascade are, where:

Have n-1 stages of first buffer elements that are directly connected in cascade are, the i-th stage of the first buffer element at its output connection with a clock input terminal of the (i + 1) th stage D flip-flop is connected, i Includes values from 1 to n-1, the first stage of the first buffer element its input connection with a clock input connection of the first step D flip-flops is connected, the stage delay time of the i-th stage of the first Buffer element approximately equal to the step delay time of one Data input terminal of the i-th stage D flip-flop up to one Data input terminal of the (i + 1) th D flip-flop, where i values from 1 to n-1 assumes.

The maximum operating frequency fmax of this logic circuit is approximately fmax = 1 / t _S if the response time of the D flip-flop is t _S. fmax is determined solely by the response time t _{S of} the D flip-flop. Since, generally speaking, the setting time t _{S is} considerably less than the step delay time t _{F of} the D flip-flop, a significant improvement in fmax is possible compared to the possibilities in the prior art.

In the first form of the first embodiment of the invention, the Output terminal of the i-th stage D flip-flop directly to the data input terminal of the (i + 1) -th D flip-flop, where i takes values from 1 to n-1, and where the stage delay time of the i-th stage of the first buffer element is approximately the same is the stage delay time of the i-th stage D flip-flop, where i values from 1 to n- 1 assumes.

The second form of the first embodiment of the invention further comprises n-1 logical combination circuits, the i-th of which is connected to its input terminal with the output terminal of the i-th stage D flip-flop and with its Output terminal with the data input terminal of the (i + 1) th D flip-flop is connected, taking i values from 1 to n-1, the step delay time the i-th logical combination circuit is approximately equal to the difference between the is the i-th stage of the first buffer element and that of the i-th D flip-flop, i Assumes values from 1 to n-1.

In the third form of the first embodiment of the invention, the n are logical Combination circuits n selectors, each having an input control terminal has a selection control signal supplied so that one of the input signals is output, the third form still n-1 levels of second Has buffer elements that are directly connected in cascade, the i-th Stage of the first buffer element at its output connection with the Control input connection of the i-th selector is connected, where i values from 1 to n-1 assumes, the selection control signal at an input terminal of the third stage of the second buffer element is entered, the step delay time of the i-th Level of the second buffer element approximately equal to that of the i-th level of the first Is buffer element, where i assumes values from 1 to n-1.

The fourth form of the first embodiment of the invention also includes Values for i from 1 to n-1: n-i levels of third buffer elements that are cascaded are connected, wherein input connections of the third buffer elements with the Output terminal of the i-th stage D flip-flop are connected, the Step delay time of the third buffer element and the n steps of master-slave D flip-flops are approximately the same, with parallel data from the Output connections of the two of the third buffer elements and the nth step  D flip-flops are output, with the output timing of all bits of the parallel Data is adjusted.

According to the second embodiment of the invention, a logic circuit is included n stages of master-slave D flip-flops are provided, which are connected in cascade are, and a logical combination circuit provided on their Input terminal with an output terminal of the j-th stage D flip-flop and with its output terminal with a data input terminal of the i-th D flip-flop is connected, where i and j satisfy a relationship 1 i <j n, where a Buffer element is provided, which with its output connection to a Clock input terminal of the i-th stage D flip-flop and with its input terminal a clock line is connected, and has a clock line connected to a Input connection of the buffer element and directly to a clock input connection of the j th stage D flip-flops is connected.

In this way the maximum operating frequency is fmax of the logic circuit improved.

According to the third embodiment of the invention is an integrated one Semiconductor circuit provided which is a previously described logic circuits having.

The invention and its advantages are described below using exemplary embodiments explained in more detail with reference to the drawings.

Show it:

Figure 1 is a circuit diagram corresponding to the first embodiment of a shift register.

FIG. 2 is a timing diagram illustrating the operation of the circuit of FIG. 1;

Fig. 3 is a diagram illustrating a logic circuit of the second embodiment;

Fig. 4 is a circuit diagram of a shift register of the third embodiment;

Fig. 5 is a diagram illustrating a pattern generating circuit of the fourth embodiment;

Fig. 6 is a diagram illustrating a pattern generating circuit of the fifth embodiment;

Fig. 7 is a circuit diagram of a shift register of the sixth embodiment;

Fig. 8 is a circuit diagram of a known shift register;

Fig. 9 is a circuit diagram of another known shift register; and

Fig. 10 is a diagram illustrating a known pattern generating circuit.

Fig. 1 shows a shift register 10 D, in which n stages of master-slave D flip-flops 11 to 1n are connected in cascade.

The output terminal of the non-inverting buffer element 4 i is connected for delaying to the clock input terminal C of the D flip-flop 1 i (i = 2 to n) and the input terminal of the non-inverting buffer element 4 i is connected to the clock input terminal C of the D flip-flop 1 i-1 . The D flip-flops 11 to 1 n have identical properties to one another and the non-inverting buffer elements 42 to 4n also have identical properties to one another. The output signals of the D flip-flop 1 i and the non-inverting buffer element 4 i + 1 are correspondingly indicated by DI and CK if the data DI and the clock CK are supplied to the data input terminal D and the clock input terminal C of the D flip-flop 11 accordingly.

FIG. 2 shows a timing diagram illustrating the operation of the circuit shown in FIG. 1. In Fig. 2 denote:
t _F : the stage delay time of the D flip-flop from the clock input signal to the data output signal,
t _S : the response time of the D flip-flop,
t _H : the hold time of the D flip-flop, and
t _B : the stage delay time of the non-inverting buffer element 4 i.

The maximum operating frequency, fmax, of the shift register 10 D is indicated with

fmax = 1 / (t _F + t _S - t _B ). . . (3).

By setting the circuit constant so that t _{F is} equal to T _B , equation (3) can now be expressed in simplified terms with

fmax = 1 / t _S. . . (4).

Finally, the maximum operating frequency fmax is determined solely by the response time t _{S of} the D flip-flop 1 i. Since the setting time t _S is generally significantly shorter than the step delay time t _{F of} the D flip-flop, the maximum operating frequency fmax is significantly improved compared to the prior art.

FIG. 3 shows a logic circuit 10 E of the second exemplary embodiment. The n components that are identical to those in FIG. 1 are designated by the same reference numerals.

In this circuit, a logic combination circuit 5 i + 1 is connected between the non-inverting output terminal Q of the D flip-flop 1i and the data input terminal D of the D flip-flop 1 i + 1. All other aspects of the structure of this embodiment are identical to that of the circuit shown in FIG. 1. With the step delay time of each logic circuit 5 i, which is determined with t _L , the maximum operating frequency fmax of the logic circuit 10 E is as

fmax = 1 / (t _F + t _S + t _L - t _B ). . . (5)

expressed.

By inserting the circuit constant so that t _{B is} equal to t _F + t _L , this equation becomes identical to the previously given equation (4), and as just stated in the first embodiment, fmax is greatly improved compared to the prior art.

Fig. 4 shows a shift register 10 F of the third embodiment. The components that are identical to those in FIG. 1 are identified by the same reference numerals.

In this circuit, one of the two input connections of the selector 6 i is connected to the non-inverting output connection of the D flip-flop 1 i-1 and the data Di to be set are fed to the other input connections. The output terminal of the selector 6 i is connected to the data input terminal D of the D flip-flop 1 i. The non-inverting buffer elements 72 to 7n are also cascaded for delaying and the output terminal of the non-inverting buffer element 7 i is connected to the selector control input terminal of the selector 6 i. The non-inverting buffer elements 42 to 4n and 72 to 7n have identical properties to one another.

When the selection control signal SL which is supplied to the input terminal of the non-inverting buffer element 72 is set to "low", the selector 6 i selects the output signal of the D flip-flop 1 i-1 and when the selection control signal SL is set to "high" the selector 6 i the data to be set Di.

The step delay time of the selector 6 i is determined as t _SL . If the step delay time t _{B of} both non-inverting buffer elements 4 i and 7 i have the same value, the maximum operating frequency f max of the shift register 10 F becomes

fmax = 1 / (t _F + t _S + t _SL - t _B ). . . (6)

expressed.

By setting the circuit constant so that t _{B is} equal to t _F + t _SL , the formula (6) becomes identical to the previously given formula (4) and, as in the first embodiment described above, fmax is strong compared to the prior art improved.

Fig. 5 shows a pattern generation circuit 10 G of the fourth embodiment. Components identical to FIG. 10 are identified by the same reference numerals.

The difference between the pattern generating section 10 G and the pattern generating circuit 10 C, which is shown in Fig. 10 is that, that in this circuit, the D flip flop 11 is connected for delaying a non-inverting buffer member 81 to the clock input terminal C to which the output signal the logic combination circuit LC is returned. The maximum operating frequency fmax of the pattern generation circuit 10 G has the lower of the two values associated with

fmax 1 = 1 / (t _F + t _S + t _H + t _L - t _B ). . . (7)
fmax 2 = 1 / (t _F + T _S + t _H + t _B ). . .(8th)

are described.

Fmax has the greatest value if t _B = t _L / 2 and fmax at this point

fmax 2 = 1 / (t _F + T _S + t _H + t _L / 2). . . (9)

are expressed. Whereas the maximum operating frequency fmax for the pattern generation circuit from FIG. 10 is designated by the formula (2) given above.

With formulas (9) and (2), this fourth embodiment shows in obvious way that fmax is improved compared to the prior art.  

Fig. 6 shows the pattern generating circuit 10 H of the fifth embodiment. The components that are identical to those in FIG. 5 are identified by the same reference numerals.

In this circuit, for delaying the clock input terminal C of the D flip-flops 11 , 12 , 15 and 16 are connected to the output terminals of the non-inverting buffer elements 81 , 82 , 85 and 86, respectively. The input connections of the non-inverting buffer elements 81 , 82 , 85 and 86 and the clock input connections C of the D flip-flops 13 and 14 are connected together and the clock CK is supplied to them together. The non-inverting buffer elements 81 , 82 , 85 and 86 have identical properties to one another.

The maximum operating frequency fmax of the pattern generating circuit 10 H is the same as in the previous fourth embodiment.

Fig. 7 shows a shift register 101 of the sixth embodiment. The components that are identical to those in FIG. 1 are identified by the same reference numerals.

The difference from the circuit shown in Fig. 1 is that for delaying ni stages of non-inverting buffer elements 9 n-i are connected to the non-inverting output connections of the D flip-flop 1 i and that the output signal DOi of the non-inverting buffer element 9 n-i is used. In this manner, the timing for the data DO1 to DOn can outputted from output terminals of the noninverting buffer elements 9 n-1 to 91 and the D flip-flop 1 n, to be adjusted.

Claims (11)

1. Logic circuit with cascade-connected n stages of master-slave D flip-flops ( 1 i), characterized by n-1 stages of a first buffer element ( 4 i), which are directly connected to each other in a cascade manner, the i-th stage of the the first buffer element is connected with its output connection to a clock input connection (C) of the (i + 1) th stage D flip-flop ( 1 i), i taking values from 1 to n-1, the first stage of the first buffer element ( 42 ) is connected at its input terminal to a clock input terminal (C) of the first stage D flip-flop ( 11 ). 2. Logical circuit according to claim 1, characterized in that a stage delay time of the i-th stage of the first buffer element ( 4 i) approximately equal to a stage delay time from a data input connection (D) of the i-th stage D flip-flop to a data input connection ( D) of the (i + 1) th D flip-flop, where i assumes values from 1 to n-1. 3. Logical circuit according to claim 2, characterized in that the output terminal (Q) of the i-th stage D flip-flop is connected directly to the data input terminal (D) of the (i + 1) th D flip-flop, where i values assumes from 1 to n-1, and a stage delay time of the i-th stage of the first buffer element ( 42 ) is approximately equal to a stage delay time of the i-th stage D flip-flop, where i assumes values from 1 to n-1. 4. Logic circuit according to claim 2, characterized by n-1 logical combination circuits ( 5 i), wherein the i-th is connected with its input terminal to the output terminal (Q) of the i-th stage D flip-flop and with its output terminal is connected to the data input terminal (D) of the (i + 1) -th D flip-flop, where i takes values from 1 to n-1, wherein a stage delay time of the i-th logic combination circuit is approximately equal to a difference of that of the i-th stage of the first buffer element and that of the i-th D flip-flop, where i has values from 1 to n-1. 5. Logic circuit according to claim 4, characterized in that the n logic combination circuits are n selectors ( 6 i), each having a control input terminal, to which a selection control signal is supplied in order to output one of the input signals, and in that n-1 stages of second directly cascaded buffer elements ( 7 i) are provided, the i-th stage of the first buffer element ( 7 i) being connected with its output connection to the control input connection of the i-th selector (Ci), i assuming values from 1 to n-1 , wherein the selection control signal is input to an input terminal of the first stage of the second buffer element, wherein a stage delay time of the i-th stage of the second buffer element is approximately equal to that of the i-th stage of the first buffer element, where i assumes values from 1 to n-1 . 6. Logical circuit according to one of claims 1 to 5, characterized in that it assumes the values from 1 to n-1 for i: ni stages of cascade-connected third buffer elements ( 9 i), the input connection of the third buffer element with the output connection (Q) of the i-th stage D flip-flop ( 1 i) is connected, a stage delay time of the third buffer element and the n stages of the master-slave D flip-flops being approximately the same, with parallel data (DOi) from the output terminals of the two third buffer elements ( 9 i) and the n-th stage D flip-flop, the output signal timing of all bits of the parallel data being matched. 7. Logical circuit with n stages of master-slave D flip-flops, which are connected in cascade form, characterized by a logic combination circuit (LC), which has its input terminal at an output terminal (Q) of the jth stage D flip-flop and is connected at its output connection to a data input connection (D) of the i-th D flip-flop, where i and j satisfy the relationship ii <jn with:
A a buffer element ( 9 i) which is connected at its output terminal to a clock input terminal (C) of the i-th stage D flip-flop and with its input terminal to a clock line (CK), and a clock line which is connected to an input terminal of the buffer element ( 9 i) and is directly connected to a clock input connection (C) of the j-th stage D flip-flop ( 1 i). 8. Logic circuit according to claim 7, characterized in that a step delay time of the buffer element is approximately half that of the logical combination circuit (LC). 9. Logical circuit according to claim 7 or 8, characterized in that it has for i with values i from 1 to n-1: ni stages of third buffer elements ( 9 i) which are connected in cascade, the input connection of the third buffer elements with is connected to the output terminal (Q) of the i-th stage D flip-flop, the stage delay time of the third buffer element ( 9 i) and the n stages of master-slave D flip-flops being equal to one another, whereby parallel data from the output terminals of the two third buffer elements and the n-th stage D flip-flop are output, the output signal timing of all bits of the parallel data being matched. 10. Logical circuit with n stages of master-slave D flip-flops, which are connected in cascade form, characterized by a buffer element which has at its input terminal with a clock input terminal (C) of the first stage D flip-flop ( 11 ) and with its output terminal is connected to a clock input terminal (C) of a different stage D flip-flop than the first stage D flip-flop. 11. Integrated semiconductor circuit with the logic circuit according to one of the Claims 1 to 10.