JPS63261924A - Voice decoding device - Google Patents

Abstract

PURPOSE:To obtain a device without outputting noise or distorted sound by providing a switch circuit at an output of a decoder so as to shut off the output of the decoder when no frame synchronization is established. CONSTITUTION:An input signal 2 is inputted in parallel with a decoder 4 and a frame synchronizing section 6 and the decoder 4 decodes a digital signal string synchronously with the timing signal sent through a synchronizing signal line 7 from the synchronizing section 6. When the synchronizing section 6 detects the discrepancy for the prescribed number of times consecutively in the phase of the synchronizing bit and the timing signal of the output of a synchronizing oscillator, it is regarded as an error of a synchronizing oscillator and the synchronization of the synchronizing oscillator is taken again depending on the detected synchronizing bit. The synchronizing section 6 outputs a signal 8 during this time and the output 5 of the decoder 4 is shut off from the output signal line 3 by a switch circuit 9. Thus, noise or distorted sound is not given to a listener while the frame synchronization is not established.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a speech decoding device for decoding speech encoded by BA#-i.

[Conventional technology]

FIG. 3 is a block diagram showing the configuration of a voice encoding/decoding device shown, for example, in the Proceedings of the 1981 Telecommunications Society National Conference of Communication Division N1366, and in the figure (1
) is the decoding device, (2) is the input signal line of the decoding device (1), (3) is the output signal line of the decoding device (11), (4) is the decoder, (6) is the frame synchronization unit, (7) is a synchronization signal line, (10) is an encoding device, and (11) is an encoding device (10
), (12) is the output signal line of the encoding device (10), (13) is the encoder, (14) is the frame generator, (15) is the frame information line, and (16) is the transmission line. It is.

FIG. 4 is a format diagram showing the frame structure of one frame of the signal transmitted on the transmission path (16) in FIG. It consists of a total of n bits.

Synchronization bit Vi By detecting a device consisting of a specific bit/mother turn, it is possible to know that it is a synchronization bit within one frame, and therefore determine the position of auxiliary information and main information within the frame. and can perform correct decoding. Since the structure of the synchronization bit and the detection of frame synchronization are well known, a general explanation thereof will be omitted.

Furthermore, when encoding and transmitting audio signals, etc., the transmission band is often compressed by some method before transmission; for example, when the encoder (13) is an encoder that performs adaptive predictive encoding. The system processes the input audio every certain time unit and transmits the auxiliary information and main information in a frame as shown in Fig. 4, but the encoder (13) and decoder (4) Since this is well known, its explanation will be omitted.

An analog signal such as voice inputted from the input signal line (11) is converted into a desotal signal in the format shown in FIG.
) is output.゛The signal input via the input signal line (7) via the transmission path (16) is inputted in parallel to the decoder (4) and the frame synchronization unit (6),
) detects the synchronization bit and sends a timing signal indicating the frame synchronization point to the decoder (4) via the synchronization signal line (7).
). The decoder (4) decodes the dinotal signal string input from the input signal line (2) in synchronization with the timing signal sent via the synchronization signal line (7).

By the way, generally, the frame synchronizer {6} has a built-in synchronous oscillator, and the output of this synchronous oscillator is output as a timing signal onto the synchronous signal line (7). The oscillation of the oscillator is phase-locked by the synchronization bit on the input signal line (2).

Therefore, some time is required from when the input signal begins to arrive at the input signal line (2) until synchronization within the frame synchronization section (6) is established. Furthermore, if a bit error occurs due to a failure on the transmission path (16), loss of synchronization will occur. Also, if the frame synchronization unit (6) does not have a built-in synchronization oscillator and generates a timing signal directly from the detected synchronization bit, synchronization will be lost every time a bit error occurs for the synchronization bit. It's going to happen.

[Problem that the invention seeks to solve]

Since the conventional audio decoding device is configured as described above, even if frame synchronization has not been established, the decoder (4
) is output onto the signal output line (3), which poses a problem in that it causes audible noise.

This invention was made to solve the above-mentioned problems, and aims to provide an audio decoding device that does not output noise or distorted sound even when 7-frame synchronization is not established. The purpose is

[Means for solving problems]

In the apparatus of the present invention, a synchronization failure signal is output during a period when frame synchronization is not established in the 7-frame synchronization section, and the output of the decoder is cut off by this synchronization failure signal.

[Effect]

Since the output of the decoder is cut off during the period when frame synchronization is not established, the listener will not be exposed to significantly distorted speech or noise.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a clock diagram showing an embodiment of the present invention. In the figure, the same symbols as in FIG. 3 indicate the same or corresponding parts, {5} is the decoded signal output line, and (8) is the synchronization failure signal. The output line (9) is a switch circuit. Further, the encoding device (1o) and transmission line (16) corresponding to the decoding device (1) in FIG. 1 are as shown in FIG.

Further, in FIG. 1, the parts having the same reference numerals as those in FIG. 3 operate in the same manner as described with respect to FIG. 3, so a redundant explanation will be omitted.

In order to output a synchronization failure signal onto the synchronization failure signal output line {8}, for example, a set-reset type 7 rip-frog (not indicated, hereinafter F/F) is installed in the frame synchronization section (6).
In the initial state, this F/F is reset, and the timing signal of the output of the synchronous oscillator (not shown) in the frame synchronization part (6) and the timing signal detected by the frame synchronization part (61) are provided. If the phases of the synchronization bits match M times consecutively (M is an integer determined by design), a set signal is output and the F/F is set, and even if they do not match consecutively N times (N is an integer determined by design). If this is the case, output a reset signal to reset 扠1゛, set the state where & is set as a frame synchronization established state, and the state where &↑ is reset as a synchronization failure state.This synchronous oscillator is phase-synchronized by the synchronization bit detected by the frame synchronization unit (6), and after being phase-synchronized, it is continuous (N-1
) The phase mismatch during recovery is assumed to be an error in the detected synchronization bit, and the decoding in the decoder (4) K is synchronized with the timing signal of the output of this synchronization oscillator, and N consecutive mismatches are detected. If so, it is assumed that it is an error on the synchronous oscillator side, and
It operates to resynchronize the synchronous oscillator based on the detected synchronization bit.

The logic "0" output from the reset & is output on the signal line (8) as a synchronization failure signal, operating the switch circuit (9) and connecting the signal lines (5) and (3). cut off. When & is set and the signal logic on the signal line (8) becomes "1", the switch circuit (9) connects the signal lines (5) and (3).

Therefore, the output of the decoder (4) is not output to the signal line (3) during a period when frame synchronization is not established.

FIG. 2 is a block diagram showing another embodiment of the present invention. In FIG. 2, the same reference numerals as in FIG. 1 indicate the same or equivalent parts, and the operations are the same as in FIG. The detailed explanation will be omitted. (90) is a switch circuit corresponding to (9) in FIG.
) to ground.

Corresponding to the case where the signal line (3) is open in Fig. 1, the signal line (3) is grounded in Fig. 2, and the voltage induced in the signal line (31) due to inductive coupling etc. is completely grounded. It can be removed by

[Effects of the Invention] As described above, according to the present invention, an abnormal signal output from the decoder is interrupted when frame synchronization is not established by a simple configuration of providing a switch circuit at the decoder output. be able to.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a block diagram showing another embodiment of the invention, FIG. 3 is a block diagram showing the configuration of a conventional device, and FIG. 4 is a block diagram showing another embodiment of the invention. 4 is a format diagram showing a frame structure of a signal transmitted on the transmission path of FIG. 3; FIG. (1) is a decoding device, (2) is an input signal line, (3) is an output signal line, (4) is a decoder, (5) is a decoded signal output line,
(6) is a frame synchronization section, (7) is a synchronization signal line, (8)
is the synchronization failure signal output line, and (9) is the switch circuit. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (2)

[Claims] (1) In an audio decoding device that decodes an audio signal from a signal string obtained by adding bits for frame synchronization of the audio signal to an encoded audio signal, frame synchronization detects the frame synchronization point from the signal string. A decoder that decodes and outputs an audio signal from the signal sequence using the frame synchronization point detected by this frame synchronization unit, and a switch that connects or disconnects the output of this decoder to the output signal line. A switch circuit, means for outputting a synchronization failure signal during a period in which frame synchronization cannot be established in the frame synchronization section, and controlling the switch circuit to cut off the output of the decoder using the synchronization failure signal. An audio decoding device comprising: (2) The audio decoding device according to claim 1, wherein the switch circuit is configured to ground the output signal line when cutting off the output of the decoder due to a synchronization failure signal. .