JPS6014534B2 - Offset compensation method and circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an offset compensation circuit, and particularly to an offset compensation circuit suitable for use in a coder/decoder in a PCM communication system.

Generally, in a circuit including an operational amplifier or the like, DC errors usually occur due to various factors such as mismatch.

This DC error is usually called an offset, and it is required to compensate for it. For example, there is an encoder/decoder that includes this operational amplifier, but if the offset occurs in this encoder/decoder, the sound quality of the reproduced voice will deteriorate or noise will increase during no calls. This poses a problem, and it is imperative that it be resolved. Solving this problem is relatively easy when the encoder/decoder is composed of discrete components. This is because all of its internal circuits are exposed to the outside. However, in recent years, it has become common to form the encoder/decoder using a large-scale integrated circuit. This is aimed at stabilizing performance or lowering prices through mass production. Therefore, in order to solve the above problem, it has become impossible to directly modify the internal circuit. If we were forced to make any changes, we would only be able to do something about the input/output pins that protrude to the outside of the large-scale integrated circuit. For example, connect an external capacitor or external resistor to one of the input/output pins. However, providing these optimal external elements for each large-scale integrated circuit is not desirable for stabilizing performance and also leads to increased costs. For this reason, various proposals have been made for circuits that can perform offset compensation by themselves without using the external elements or the like. Among them, the polarity bit of the output code of the A/D converter is “1”.
'', there is a method of adding an offset correction voltage to the signal so that the number of "0"s becomes equal. Consider a case in which a periodic signal whose basic period is an odd multiple of the sampling period is input in such a method. In this case, the number of samples included in one period is an odd number. Therefore, even if offset voltages are not superimposed inside the signal processing circuit, the number of positive samples and the number of negative samples included in one cycle are not equal. The offset compensation circuit performs an offset compensation operation for such a signal as well. As a result, the output signal becomes stable with a certain offset voltage superimposed thereon. This offset voltage is highly dependent on the signal's frequency, amplitude and phase with respect to the sampling clock. Therefore, if these values fluctuate, the offset voltage corresponding to the value fluctuates, causing the output signal to oscillate. It is therefore an object of the present invention to provide an offset compensation method which eliminates the drawbacks that result in oscillations in the output signal, and a circuit that can be used directly for implementing the method.

The compensation method according to the present invention eliminates the offset voltage generated inside a signal processing circuit that inputs a signal whose amplitude polarity is positive and negative with equal probability. In an offset compensation method that corrects the number of samples to be equal to the number of negative samples, a periodic signal whose basic period is an odd multiple of the sampling period of the signal is detected, and offset compensation is performed. The feature is that the operation is stopped. Furthermore, the configuration of the offset compensation circuit used directly in such a method is such that the offset voltage generated inside the signal processing circuit, which receives a signal whose amplitude has equal probability of positive or negative, is compensated for by the offset voltage of the output signal. In an offset compensation circuit that corrects so that the number of samples whose magnetic properties are positive and the number of samples whose magnetic properties are negative are equal, the polarity of the signal sample value changes from negative to positive, and then , a means for counting the number of samples Np with positive polarity and the number Nn of samples with negative polarity that occur between the time point when the polarity changes from negative to positive, and the case where the difference between Np and Nn is 1 is 2. The present invention is characterized in that it has a means for generating a signal to stop the operation of correcting the offset voltage if the offset voltage continues to be greater than or equal to 1, until the difference between the counted values Np and Nn is no longer 1. The present invention will be described in detail below with reference to the drawings.

Note that the following description assumes that an analog/digital converter is used as the signal processing circuit. FIG. 1 is a block diagram showing an analog/digital converter equipped with a general offset compensation circuit. In this figure, A and n are input analog signals to be converted from analog to digital, and it is known that, in the case of audio, the polarity appears statistically with equal probability of positive or negative.

Note that the input analog signal Ain has already been passed through the low-pass filter filter (
(not shown), the frequency band is limited to, for example, 3.4 kHz or less. The input analog signal Ain is sent to the analog/digital converter 12 via the analog adder 11.
, thereby producing an output digital signal D. ut is taken out. This world power digital signal D. ut usually consists of a sign bit representing its polarity and several level indicating bits following this, of which the sign bit is applied to the integrating circuit 13. In principle, this integrating circuit 13
R-integration is performed, and its time constant is extremely large. Due to the large time constant, the output digital signal is ○. Most of the frequency components related to code bits that have a short period and statistically equal probability of positive or negative based on the audio component of ut are removed,
An extremely low frequency component or a DC component that fluctuates due to the offset of the silk bureau cycle is extracted and negatively fed back to the analog adder 11. Offset compensation is performed here. However, the general offset compensation circuit shown in FIG. 1 has the following drawbacks.

(2) Since offset compensation is constantly executed, distortion is added to the audio component of the output digital signal Dout.

(2) Large-capacity, high-resistance elements must be used as C and R of the integrating circuit 13, and large-scale integration cannot be achieved.

etc.

In addition, there is another format that periodically detects the offset and provides negative feedback to the analog adder.
In this case, a period for offset detection must be inserted, and high-speed analog/digital conversion cannot be performed.

Among the above-mentioned drawbacks, the drawback (2) can be solved by a switched capacitor type integrating circuit described later (already proposed by the applicant). Therefore, the present invention provides an offset compensation circuit suitable for eliminating the remaining two drawbacks. FIG. 2 shows an embodiment of an analog/digital converter including an offset compensation circuit based on the method of the present invention.

This is a diagram. In this figure, components similar to those in FIG. 1 are designated with the same reference numbers or symbols. 20 in the figure is an offset compensation circuit according to the method of the present invention, which includes an offset compensation signal generation circuit 21 and a signal detection circuit 22.
It is made up of. Offset compensation signal generation circuit 21
is the polarity bit (MSB) of the output sign of A/D converters 1 and 2.
) is a circuit that has a function of generating an offset correction voltage to be added to an input signal so that the number of "1" and "0" of The circuit according to the invention of Japanese Patent Application No. 54-73953 is applied.

A concrete example of the circuit is block 21 shown in FIG.
This corresponds to Therefore, the up/down counter 32 shown in FIG. 2 is the same as the up/down counter 32 shown in FIG. In order to facilitate understanding of the present invention, the operation of the offset compensation signal generation circuit 21 shown in FIG. 3 will first be explained.

The offset compensation signal generation circuit 21 is composed of a buffer means 30 and an integrating circuit 13 with a large time constant. Buffer means 30 outputs digital signal D.

It does not respond to fluctuations based on the audio component of ut, and on the other hand, the offset talk output digital signal Dout
When the cumulatively added variation due to the offset exceeds the positive or negative tolerance range, a control signal D (consisting of D and D2) is output in response. The control signal D activates the integrating circuit 13 and applies a negative feedback voltage to the analog adder 11 for a positive offset, and a positive feedback voltage for a negative offset, respectively. This buffer means 30 outputs an output digital signal D as a specific example. A register 31 that partially branches ut and stores it, and a signal ○ stored in the register 31. The sign bit S of ut is used as the count control input U/D and the clock CL
An up/down counter 32 that counts K3 and digital outputs A, A2, etc. of the up/down counter 32.
. . . It is composed of a control circuit 33 that receives Aw. Control circuit 33 outputs control signals D and D2. Control signals D and D2
are both input to the integrating circuit 13 to start it up. The sign bit S in the register 31 is a bit indicating polarity, and is updated every sampling (eg, peach ratio).

This sign bit U/D is “1” (positive) or “0” (
The up/down counter 32 that counts the clock CLK3 counts up or down, respectively, depending on whether the clock CLK3 is negative (negative). counter 32
is (0
If it is possible to take values from 0...0) to (11...1), the reference value for countdown and countup is set to (10...0), for example. This reference value is the preset data B, B...... in the figure.
...denoted as BM. This preset data B, &...
...... BM preset is to set a part of the control signal D2 to O.
Preset input (PRESET) through R gate 34
This is done by Since the audio signal changes with positive and negative polarities, the count value of the counter 32 is (00...
・・・・・・・・・・・・0) side or (11...
・・・・・・・・・・・・1) Fluctuation toward the side.

In this case, since the probability of occurrence of positive and negative polarities is statistically almost equal, the preset value (10...
It is stable at 0). The furthest distance from this preset value is the audio, which is the lower limit of 300.
This is when it became HZ. That is, if sampling is performed at the top, the sign bit U/D will be 1 continuously.
It becomes “0” 3 times (or “1” 13 times in a row),
Count output (00………0) (or (11・
・・・・・・・・・・・・1) Approach. However, even in such a case, the counter 32 has a 5-bit configuration, for example, so that neither underflow nor overflow occurs within one period of the audio signal. Therefore, the integrating circuit 13
does not start at all. However, if the output digital signal D contains an offset, the code bits U and D will be excessively on the "1" side or the "0" side, and the counter 32 will overflow during several cycles of the L audio signal.

It will flow down. These overflows or underflows become control signals D, D2.
As a result, when there is an underflow (there is a negative offset), the integrating circuit 13 applies a positive feedback voltage +Vf to the adder 11 to compensate for the negative offset. Conversely, in the event of an overflow (with a positive offset), the integrating circuit 13 applies a negative feedback voltage -Vf to the adder 11 to compensate for this positive offset. No matter which offset compensation is performed, the counter 32 is preset by the control signal D2 and returned to the reference value (B, Z...BM), and the same operation is repeated again. Therefore, this control signal D2 is a signal indicating that either overflow or underflow has occurred. On the other hand, the control signal D is a signal for indicating whether the offset is on the positive side or the negative side. If the offset is on the positive side (the count output of the counter 32 is (10
. . . 0) to the (11 . . . . 1) side), connect the switch SW to the contact P side and receive the positive reference voltage 10 Vref. The selected reference voltage, either positive or negative, is applied to the contact P of switch SW2 through an attenuator ATI if necessary, and is applied to the sample hold 9.
Capacitor C is charged. If there is an overflow or underflow, the switch SW2 is switched to the contact P2 side by the signal D2, and the operational amplifier O
The integrating capacitor C2 provided in the feedback loop of P is charged. These include switch SW2, sample-and-hold capacitor C, operational amplifier OP, and integrating capacitor C2.
The circuit as a whole forms a so-called switched capacitor type integrating circuit. Here, the capacitance value of the integrating capacitor C2 is expanded by the operational amplifier OP, and the resistance (R) value as the CR integrating circuit is also expanded by the switched capacitor. In addition, using a switched capacitor type integrating circuit,
The present applicant has already proposed reducing C and R in FIG. 1 to realize an offset compensation circuit suitable for large-scale integration. The output voltage from the operational amplifier OP is
If necessary, it passes through an attenuator AT2 and becomes a positive or negative offset feedback voltage Vf.

Furthermore, the input analog signal Ain is added using an analog adder.
to compensate for the offset. By the way, the above explanation was made with reference to raw audio whose frequency fluctuates randomly but where positive and negative polarities appear with statistically almost equal probability. Consideration will also be given to signals in which positive and negative polarities appear with statistically equal probability.

This is because when this type of signal, for example, speech in which vowels are prolonged for a long period of time, is input, it is expected that the offset compensation circuit of the present invention will malfunction.
Normally, the input analog signal A:n is a signal sampled at a constant sampling frequency of, for example, spherical Hz according to the sampling theorem, but in this case, a signal with a constant frequency is sampled at a constant sampling frequency. When the relationship between the phase of the sampled signal and the phase of the sampled signal is under special conditions, the sampled signal is sampled more toward the positive side (or negative side) within a certain finite interval. There are things that can be done.

In this case, even though in reality the polarity of the signal is equally likely to be positive or negative, as an offset compensation circuit, the polarity is positive (
It is assumed that an offset (or negative) has occurred and an attempt is made to compensate for this. However, this is clearly a conspiracy, and if left as is, it will result in an offset being given to a normal signal. Therefore, in order to cope with such a situation, the offset signal generator shown in FIG. ).

Appropriate means the timing at which T is delayed by a certain period of time by the delay circuit (timer) 35 after the control signal D2 is output, as shown in FIG. That is, when the delay circuit 35 is reset via the OR gate 34 by the control signal D2, D2' is output after a certain period T has passed, and the up/down signal is output via the OR gate 34.
The down counter 32 is preset. In this case, the way to find the fixed period T can be determined as appropriate depending on the waveform of the analog signal that is expected to be input, but if this T is too short, the original offset compensation operation will be hindered. On the other hand, if the delay circuit 25 is too long, the reason for the existence of the delay circuit 25 will be lost. To give one specific example, it has been confirmed that the intended purpose can be effectively achieved with T=30 [enemy S]. Regarding the embodiment of the system of the present invention shown in FIG.
No.) Although the description has been made using a circuit according to the invention, the present invention is not limited to such a circuit.

That is, it is sufficient to generate an offset compensation voltage so that the numbers of "1" and "0" of the polarity bits (MSB) are equal. However, in the operation of such a circuit, consider a case where a periodic signal whose basic period is an odd multiple of the sampling period is input.

In this case, the number of samples included in one period is an odd number. Therefore, even if the offset voltage does not overlap inside the signal processing circuit (A/○ converter), the number of positive samples and the number of negative samples included in one cycle are not equal. An offset compensation signal is also generated for such a signal, and an offset compensation operation is performed. As a result, the output signal becomes stable with a certain offset voltage applied.

This offset voltage is highly dependent on the signal's frequency, amplitude, and phase with respect to the sampling clock. Therefore, if these values fluctuate, the offset voltage corresponding to the value fluctuates, causing the output signal to oscillate. To solve this problem, detect the period of the signal, and if it is an odd multiple of the sampling period,
It is sufficient to exclude it from the object of offset compensation.

For this purpose, in the system of the present invention, a signal detection circuit 22 is provided, as shown in the embodiment of FIG. This circuit detects a period in which no offset compensation operation is required from the polarity bit MSB, and generates a signal at terminal L to control the offset compensation signal generation circuit 21. FIG. 4 is an operation waveform time chart of FIG. 2.

The polarity bit signal MSB of the output sign of the A/D converter 12 controls the up/down counter 32 of the offset compensation signal generation circuit 21 to count up and count down, and also controls the flip-flop 23 of the signal detection circuit 22.
is input.

Based on the polarity of the previous sample value stored in the flip-flop 23 and the polarity of the current sample value, the gate 2
4 indicates that the polarity of the sample is from negative (polarity bit “0”) to positive (
Detect the time point when the polarity bit changes to "1"). This is the point in time when the output P from the AND gate 24 becomes "1". Next, if the signal P is "1", the up/down counter 25 receives an AND gate 2 at the timing of CLK2.
By trigger P3 from 6, preset data (LS
B) [Guidance “.P Cape=-----……----:R=“
.

ToP. : Set “1” and up/down counter 25
will count the clock CLK3. Here, the up/down counter 25 is an up/down counter counter in the offset compensation signal generation circuit 21.
If it is "1", it counts up, and if it is "0", it counts down.

At the same time, gate 27 detects that the output of the counter is (MS
B) QM-,=“1”, QM-2=………………=Q2=”0
”, the time point when Q=“0” is detected.

If the preset count value is 0, the above count value will be equivalent to ±1. In other words, "This corresponds to the fact that the difference between the number of positive samples and the number of negative samples is 1. Thus, when P becomes "1" again,
A signal P2 obtained from the detection result P4 through the gate 28
latches to flip-flop 29. If this and the previous detection result P latched in the flip-flop 30 are both "1" (counter value is ±1),
A signal P6 is obtained via the gate 31 and appears at the terminal T2, causing the up/down counter 32 of the offset signal generating circuit 21 to stop counting. At the same time, the signal P3 again initializes the count value of the counter 25, and the above operation is repeated. As stated above, according to the present invention, even if the signal period is an odd multiple of the sampling period, the offset voltage caused by this is largely dependent on the amplitude of the signal and the phase of the sampling clock, resulting in vibration of the output signal. is achieved.

Furthermore, since only a simple logic circuit is inserted, large-scale integration is easy.

An offset compensation circuit having the following advantages is realized.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an analog-to-digital converter equipped with a general offset compensation circuit, and FIG. 2 is a block diagram showing an analog-to-digital converter equipped with an offset compensation circuit according to the present invention. FIG. 3 does not include a signal detection circuit, which is a premise of the present invention.
Embodiment of Offset Compensation Signal Generating Circuit FIG. 4 shows an operating waveform time chart of the embodiment of the present invention shown in FIG. In the figure, 11 is an analog adder, 12 is an analog-to-digital converter, 13 is an integrating circuit, 21 is a buffer means,
25 and 32 are up/down counters, Ain is an input analog signal, D skin is an output digital signal, S is a sign bit, and MSB is a polarity pit. Figure 3 Figure 1 Figure 2 Figure 4

Claims (1)

[Claims] 1. A signal processing circuit that samples an analog input signal whose amplitude polarity has equal probability of being positive or negative at a predetermined period and outputs each sample value as a digital signal, in which the polarity of each sample value is positive. Count the number of pieces that are negative and the number of pieces that are negative,
An offset compensation method for correcting the offset voltage generated inside the signal processing circuit so that the number of each sample value becomes equal, the method detecting a point in time when the polarity of the sample value changes from negative to positive, and detecting the point in time when the polarity of the sample value changes from negative to positive, It is identified that the period of the input analog signal is an odd number multiple of the sampling period because the difference between the number of positive and negative polarities of each sample value counted between is 1. An offset compensation method characterized in that the correction of the offset voltage is stopped. 2. The number of positive and negative polarity of each sample value of a signal processing circuit that samples an analog input signal whose amplitude polarity is positive and negative with equal probability at a predetermined period and outputs each sample value as a digital signal. An offset compensation circuit comprising: a counting means for counting a certain number of objects; and a means for correcting an offset voltage generated in the signal processing circuit so that the respective numbers counted by the counting means are equal. a detection means for detecting a change point in time when the polarity of the sample value changes from negative to positive; and a detection means for detecting a change point in time when the polarity of the sample value changes from negative to positive; means for outputting a signal when the difference between the number of objects and the number of objects that is negative is 1, and the correction method until the difference between the numbers becomes a value other than 1 due to the signal being outputted twice or more in succession. An offset compensation circuit comprising: means for stopping the operation of the means.