JPH0427040Y2 - - Google Patents

Description

[Detailed description of the invention] (Field of industrial application) The invention relates to a digital servo type analog memory circuit. The present invention relates to an analog memory circuit that allows the D/A converter to hold a count value that is compared and counted up or down depending on the output signal as an analog signal.

(Prior art) Conventionally, this type of analog memory circuit has
For example, one shown in FIG. 2 is provided. That is, in FIG. 2, the analog signal SA to be stored is input to the non-inverting input terminal of the comparator 11. The output side of this comparator 11 is connected to the U/D terminal of an up/down counter (hereinafter referred to as "U/D counter") 12, and this U/D counter 12 receives the input signal of the U/D terminal. Count-up or count-down is selected based on the logical value.

Next, clock terminal CK of U/D counter 12
An oscillator 13 is connected to the oscillator 13, and the clock pulse SC from the oscillator 13 causes the U/D counter 1 to
A count of 2 is now performed. Note that the U/D counter 12 is provided with a clock enable terminal CKE, and when the hold signal SH is input to this terminal, the clock pulse SC from the oscillator 13 is not accepted, and the U/D counter 12 is disabled. state and the output is held.

Next, the output terminal Q ₁ of the U/D counter 12 ~
Q _o is connected to the input side of the D/A converter 14, and the output signal of this D/A converter 14 becomes an output as an analog memory circuit and is also applied to the inverting input terminal of the comparator 11. .

To explain this operation, first, the analog signal SA is successively compared with the analog output SO of the D/A converter 14 in the comparator 11.
Based on this comparison result, selection of up/down of the U/D counter 12 is made. For example, SA<
At the time of SO, control is performed so that the count is down. The U/D counter 12 performs counting at the timing of the clock pulse SC of the oscillator 13 in accordance with the counting direction determined as described above.
The count value of the U/D counter 12 is then converted into an analog signal by the D/A converter 14 and input to the comparator 11.

By repeating this operation, the level of the analog output SO of the D/A converter 14 changes to match the level of the input analog signal SA, and when the two become approximately equal, a waveform as shown in FIG. 3 is obtained. becomes. In FIG. 3, for example at time _t1 , SA>SO, so the U/D counter 12 counts up. For this reason, D/A
The output signal SO of the converter 14 increases, but 1
When it increases by the number of bits, SA<SO as at time _t2 , and a state of down-counting occurs. The above operations are repeated, and the output signal of the D/A converter 14 is
SO is a clock pulse with analog signal SA as the boundary.
It will fluctuate up and down in synchronization with CK, and will be in a state where it stores a value almost equal to the analog signal SA.

In addition, when holding the output signal SO of the D/A converter 14, the hold signal SH is
Clock enable terminal CKE of D counter 12
is input. By inputting this hold signal SH, the count of the U/D counter 12 is stopped and the output is held, and the output signal SO of the D/A converter 14 is also held.
A value approximately equal to the input analog signal SA at that time is held.

(Problem to be solved by the invention) By the way, in the above analog memory circuit, the D/A converter 1 as shown in FIG.
When the output signal SO of No. 4 fluctuates, the switching noise is superimposed on the output signal SO. This switching noise is
Since the positive direction and the negative direction do not necessarily match, the output signal SO is the input analog signal as shown in Figure 4.
The waveform becomes vertically asymmetrical with SA at the center, and the range of change becomes large.

Furthermore, the difference between the average value SO' of the output signal SO of the D/A converter 14 and the input analog signal SA becomes large, and when the output signal SO is held,
If the asymmetric noise described above is large, the hold value may deviate significantly from the analog signal SA.
Therefore, to reduce the effects of such noise,
As shown in FIG. 5, it is necessary to make the width of the clock pulse CK sufficiently long to reduce its proportion in the noise of the output signal SO. In other words, the oscillation frequency of the oscillator is lowered.

Furthermore, in this circuit configuration, the comparator 11,
A delay in signal transmission occurs within the closed loop of the U/D counter 12 and the D/A converter 14. Therefore, if the frequency of the clock pulse CK is increased, the output signal of the D/A converter 14 will change with a width of one bit or more, and the value when held will deviate from the value of the analog signal SA.
From this point of view as well, the frequency of the clock pulse CK has to be low.

However, when the frequency of the clock pulse CK is lowered, the number of bits n of the U/D counter 12 and the D/A converter 14 is increased to make the unit change range finer and to improve accuracy, the time required for full-scale change is reduced. This results in a problem of slow response.

The present invention has been proposed to solve the above problems, and its purpose is to provide a simple analog memory circuit that is not affected by switching noise and has no response delay.

(Means for Solving the Problems) In order to achieve the above object, the present invention detects the difference between the analog signal to be stored and the output signal of the D/A converter using an absolute value detection means such as an absolute value amplification circuit. The present invention is characterized in that the frequency of the count clock pulse of the U/D counter is changed and controlled by frequency changing means such as a voltage controlled oscillator.

(Function) In the present invention, when the difference between the analog signal and the output signal of the D/A converter is large, the frequency of the clock pulse becomes high, the U/D counter counts quickly, and the response becomes fast. Also,
When the difference between the analog signal and the output signal of the D/A converter becomes smaller, the frequency of the clock pulse becomes lower, and the counting operation becomes slower and is not affected by switching noise or the like.

(Example) An example of the present invention will be described below with reference to the drawings. In FIG. 1, as before, 11 is a comparator;
12 is a U/D counter 12, 14 is a D/A converter 14, and a terminal TA connected to the non-inverting input terminal of the comparator 11 receives an analog signal to be stored.
SA is now entered.

Next, both terminals on the input side of the comparator 11 are connected to the input side of an absolute value amplification circuit 1 as an absolute value detection means, and an output terminal of this absolute value amplification circuit 1 is connected to a voltage control circuit as a frequency control means. Connected to the input side of oscillator 2. Furthermore, the output terminal of the voltage controlled oscillator 2 is the clock terminal of the U/D counter 12.
Connected to CK.

Of these, the absolute value amplification circuit 1 amplifies and outputs the absolute value of the difference between the analog signal SA and the output signal SO of the D/A converter 14, that is, |SA-SO|. In addition, the voltage controlled oscillator 2
The oscillation frequency changes in accordance with the magnitude of the input voltage, and in this embodiment, the oscillation frequency changes in proportion to the input voltage.

Next, this operation will be explained in detail.

First, when the analog signal SA is input,
Generally, the magnitude thereof is significantly different from that of the output signal SO of the D/A converter 14. Therefore, the output voltage of the absolute value amplifier circuit 1 is also large. Therefore, the voltage controlled oscillator 2 outputs a clock pulse SC having a relatively high frequency. This clock pulse SC causes the U/D counter 12 to count at a fast response speed. Therefore, the output signal SO of the D/A converter 14 rapidly approaches the analog signal SA.

When the output signal SO of the D/A converter 14 approaches the analog signal SA, |SA−SO| decreases, so the oscillation frequency of the voltage controlled oscillator 2 gradually decreases, and at the same time, the frequency of the clock pulse SC also gradually decreases. . Therefore, the counting operation of the U/D counter 12 gradually becomes slower, and the D/A converter 1
When the output signal SO of 4 becomes approximately equal to the analog signal SA, the D/
The switching noise of the A converter 14 is reduced, and furthermore, the switching noise of the A converter 14 and the U/D counter 1
Errors due to delays in the closing circuits of D/A converter 2 and D/A converter 14 are also reduced.

In other words, when the difference between the analog signal SA and the output signal SO of the D/A converter 14 is large, the U/A
Since the D counter 12 counts quickly, even if the variation range is reduced to improve accuracy as described above, the responsiveness of full-scale changes does not deteriorate. In addition, the output signal SO of the D/A converter 14
When approaches the value of the analog signal SA, the U/D counter 12 counts slowly, so the fifth
The state shown in the figure is reached, the influence of noise is reduced, and there is no inconvenience caused when the output signal SO of the D/A converter 14 changes with a width of one bit or more.

Note that the configuration of the present invention is not limited to this embodiment in any way; for example, the frequency of the clock pulse SC may be changed using something other than the voltage controlled oscillator 2.

(Effects of the invention) As described above, according to the invention, the absolute value of the difference between the analog signal to be stored and the output signal of the memory is detected, and the cycle of the counting operation is changed accordingly. Therefore, even with high precision, there is no response delay, and errors in memory values caused by noise and signal transmission delays can be reduced.

Furthermore, since the structure is simple, it can be provided at low cost.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.
FIG. 2 is a block diagram showing a conventional example, FIG. 3 is a diagram showing an example of an analog signal and an output signal, and FIGS. 4 and 5 are diagrams explaining the influence of switching noise caused by a D/A converter. . 1... Absolute value amplifier circuit, 2... Voltage controlled oscillator, 11... Comparator, 12... U/D counter,
14...D/A converter, SA...analog signal, SC...clock pulse, SH...hold signal, SO...output signal, SO'...average value of output signal SO.

Claims (1)

[Claims for Utility Model Registration] Compare the input analog signal with the output signal of the D/A converter, select the counting direction of the up-down count according to the result, and adjust the timing of the clock pulse according to the selected counting direction. In an analog memory circuit in which a count value of an up-down count counted by is analog-converted into the output signal by the D/A converter, the absolute value of the difference between the input analog signal and the output signal of the D/A converter 1. An analog memory circuit comprising: absolute value detection means for detecting the absolute value; and frequency control means for changing the frequency of the clock pulse in accordance with the absolute value.