JPH0247916A - Analog comparator - Google Patents

Abstract

PURPOSE:To prevent differential inputs due to the fluctuation of a power source voltage caused by noise from being precharged to an equal potential by connecting a capacitor to an output terminal of a bias potential generating circuit and retarding a precharge signal. CONSTITUTION:An input analog signal VIN and a comparison voltage VCMP via switches 1, 2 in response to a sample signal synchronously with a clock and a comparison signal are fed to a capacitor 3. On the other hand, an output from a bias potential generating circuit 4 via switches 6, 7 in response to a precharge signal synchronously with the clock is applied to the other terminal of a capacitor 3 and a capacitor 5, input voltages Va, Vb are processed by a differential amplifier 8 and the signal VIN is converted into a digital value. A capacitor 4a is connected to the output terminal of the circuit 4, precharged with a delay to the clock signal, and differential inputs are precharged to an equal potential without effect of the fluctuation of a power source voltage due to leading/trailing noise of the clock signal. Moreover, the precharge signal is retarded or both methods are used in common to obtain the same result.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an analog comparator circuit, and particularly to an analog comparator circuit that suppresses the influence of noise and improves comparison accuracy without providing a dedicated terminal.

[Conventional technology]

FIG. 3 shows a basic configuration block diagram of a conventional analog comparator circuit. The conventional analog comparator circuit is
The analog/4G input signal (hereinafter referred to as V) is synchronized with the sampling signal.
Set as IN. ) and a comparison voltage (hereinafter referred to as V.MP) in synchronization with the conveyor signal.

), the capacitor 33 connected to the output of the analog switch 31 or the analog switch 32 &, and the power supply voltage (hereinafter referred to as v, I)
A bias potential generation circuit 34 that generates a predetermined bias potential by dividing the voltage ( ) with a plurality of resistors R, a capacitor 35 connected to the output 34 of the bias potential generation circuit 34, and a precharge signal. It is comprised of analog switches 36 and 37 that transmit the potential of the output of the bias potential generation circuit 34 in synchronization with the 200, and a differential amplifier circuit 38.

In the conventional circuit, when the sampling signal becomes high level, the analog switch 31 is turned on and VIN is sampled. At the same time, the precharge signal becomes high level, the analog switches 36 and 37 are turned on, and the terminals V 1 , V b of the capacitors 33 and 35 are precharged to the potential of the output of the bias potential generation circuit 34 . Next, when the sampling signal and the precharge signal become low level and the conveyor signal becomes high level, the analog switches 31, 36 and 37 are turned off, and the analog switch 32 is turned on instead, so that VcMP is connected to the other terminal of the capacitor 33. is input. At this time, the potential of one input V is held constant, and the potential of the other input V is equal to VIN and V due to capacitive coupling of the capacitor 33. The potential difference of MP changes. This potential change is amplified by the differential amplifier 38, and ■! , and V. Compare MP.

The above comparator circuit is a microcomputer (hereinafter referred to as
The microcontroller converts analog voltage into digital values, and data processing is executed by the microcontroller.

[Problem to be solved by the invention]

Since microcontrollers generally operate in synchronization with the system clock, the system clock (for example, φ1) is used.
Noise occurs on the VDD line in synchronization with the Noise is particularly noticeable in microcontrollers that operate at high speeds. The precharge signal, sampling signal, etc. also change in synchronization with the system clock φ1.

When the conventional analog comparator circuit described above is built into a microcontroller, assuming that the precharge signal falls in synchronization with, for example, system clock φ1, noise will be generated on the VD line of the bias potential generation circuit in synchronization with system clock φ1. As a result, noise is also generated in the output of the bias potential generation circuit, and the analog switch 36.
At the moment when 37 is turned off, the bias potential changes due to the influence of noise on the VDD line. Since the change is very steep, if there is a slight time difference in the timing at which the analog switches 36 and 37 turn off, or if there is a difference in the wiring capacitance, the differential inputs V and V will be charged to the same potential. This has the disadvantage that the accuracy of the analog comparator output deteriorates.

In addition, in order to improve accuracy, it is possible to supply a voltage with less noise to the bias potential generation circuit from an external terminal instead of vnn, but this method requires a dedicated terminal for supplying the voltage. , the disadvantage is that the number of effective terminals that can be used as microcontroller ports is reduced.

[Means to solve the problem]

The analog comparator circuit of the present invention includes: a circuit that switches and inputs an analog input voltage and a comparison voltage; a first capacitor having one terminal connected to the output of the input circuit;
a bias potential generation circuit that generates a predetermined bias potential from a power supply voltage; a second capacitor having one terminal connected to the output of the bias potential generation circuit; and a third capacitor connected to the other terminal of the first capacitor. means for precharging both terminals of the capacitor to the predetermined bias potential; a comparator circuit for comparing the potential difference between the other terminals of the first and second capacitors; 1. and means for suppressing the second capacitor from being precharged.

The above-mentioned suppression means can be realized by connecting a third capacitor to the output terminal of the bias potential generation circuit, by delaying the precharge signal to shift the precharge timing, or by using both of these means in combination.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention;
The figure is a timing chart of precharge. 1 is an analog switch that inputs an analog input signal VIN in synchronization with the sampling signal, and 2 is a comparison voltage signal V in synchronization with the conveyor signal. Analog switch to input MP,
3 is a capacitor connected to the output of analog switch 1 or analog switch 2, and 4 is a power supply voltage VDD.
5 is a capacitor that receives the output of the bias potential generating circuit as an input, and 6 and 7 are bias potential generating circuits that generate a predetermined bias potential in synchronization with a precharge signal. A transfer gate precharges the output of the circuit, 8 is a differential amplifier circuit, 4-a and 4- are a capacitor and an R-string constituting the bias potential generation circuit 4.

In this embodiment, when the sampling signal becomes high level, the analog switch 1 is turned on and the analog input signal v1N is sampled. At the same time, the precharge signal becomes high level, analog switches 6 and 7 are turned on, and capacitors 3 and 5 are precharged to the potential of the output of bias potential generation circuit 4. Next, when the sampling signal and precharge signal become low level and the conveyor signal becomes high level, analog switches 1, 6 and 7
is turned off, analog switch 2 is turned on instead, and V CMP is input, and ■□ coins and V. If there is a difference in the potentials of MP, the potential of the differential input V changes, the differential amplifier 38 amplifies the change, and compares the magnitude of V input N and VCMP. When a capacitor 4-a is added to the center tap of the Vl)D line of the bias potential generation circuit 4, a time constant circuit is formed by a resistor and a capacitor, and the rise and fall of the center tap a noise is delayed. As shown in FIG. 2, even when the precharge signal falls in synchronization with the system clock φ1, the noise changes before it has completely risen, as shown by the solid line. The dotted line is the conventional example. ), the amplitude of the noise at the midpoint tap becomes smaller, and the noise at the output of the bias potential generation circuit decreases. Therefore, the variation in the precharge potentials of the differential inputs V and V is small, and a high-precision analog comparator circuit is obtained. Identical components are designated by the same numbers and their explanations are omitted.

In this embodiment, the precharge signal is delayed by an analog delay circuit 9. By providing the analog delay circuit 9 in this way, the precharge signal is delayed from the system clock φ1, as shown in FIG. 5, and the influence of noise generated on the bias potential in synchronization with the system clock φ1 is reduced. Precharging can be completed at the right timing and the potentials V, , V, of capacitors 3 and 5 can be precharged to the same potential.

FIG. 6 shows a third embodiment of the present invention, which is a combination of the two embodiments described above. Therefore, the effect of precharging to an equal potential is significantly improved.

〔Effect of the invention〕

As described above, the present invention has the effect of reducing the influence of noise on the vDD line and improving the accuracy of the analog comparator circuit without providing a dedicated V terminal.

Fig. 2 is a timing chart of precharging in Fig. 1, Fig. 3 is a circuit diagram of the conventional example, Fig. 4 is a circuit diagram of the second embodiment, Fig. 5 is its timing chart, and Fig. 6 is a timing chart of the precharge in Fig. 1. FIG. 3 is a circuit diagram of a third embodiment.

1.2, 6, 7, 31, 32, 36.37...
Analog switch, 3, 5, 4-a, 33, 35...
... Capacitor, 4, 34 ... Bias potential generation circuit, 4-b, 34-b ... Series resistor (R
- string), 8, 38... Differential amplifier.

Agent Patent Attorney Susumu Uchihara

[Brief explanation of the drawing]

Claims (1)

[Claims] an input circuit that switches and inputs a comparison voltage of an analog input voltage; a first capacitor having one terminal connected to the output of the input circuit; and a bias potential generation circuit that generates a predetermined bias potential from a power supply voltage; a second capacitor having one terminal connected to the output of the bias potential generation circuit; and means for precharging the other terminal of the first capacitor and both terminals of the third capacitor to the predetermined bias potential. , a comparison circuit that compares the potential difference between the other terminals of the first and second capacitors, and suppressing the first and second capacitors from being precharged with a bias potential that changes due to fluctuations in the power supply voltage. An analog comparator characterized by comprising means for.