JPS62202700U - - Google Patents
Info
- Publication number
- JPS62202700U JPS62202700U JP9236686U JP9236686U JPS62202700U JP S62202700 U JPS62202700 U JP S62202700U JP 9236686 U JP9236686 U JP 9236686U JP 9236686 U JP9236686 U JP 9236686U JP S62202700 U JPS62202700 U JP S62202700U
- Authority
- JP
- Japan
- Prior art keywords
- absolute value
- converter
- output signal
- analog
- clock pulse
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000001514 detection method Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Analogue/Digital Conversion (AREA)
Description
第１図は本考案の一実施例を示すブロツク図、
第２図は従来例を示すブロツク図、第３図はアナ
ログ信号と出力信号との一例を示す図、第４図お
よび第５図はＤ／Ａコンバータによる切換ノイズ
の影響を説明する図である。
１……絶対値増幅回路、２……電圧制御発振器
、１１……比較器、１２……Ｕ／Ｄカウンタ、１
４……Ｄ／Ａコンバータ、ＳＡ……アナログ信号
、ＳＣ……クロツクパルス、ＳＨ……ホールド信
号、ＳＯ……出力信号、ＳＯ′……出力信号ＳＯ
の平均値。
FIG. 1 is a block diagram showing an embodiment of the present invention.
FIG. 2 is a block diagram showing a conventional example, FIG. 3 is a diagram showing an example of an analog signal and an output signal, and FIGS. 4 and 5 are diagrams explaining the influence of switching noise caused by a D/A converter. . 1... Absolute value amplifier circuit, 2... Voltage controlled oscillator, 11... Comparator, 12... U/D counter, 1
4...D/A converter, SA...analog signal, SC...clock pulse, SH...hold signal, SO...output signal, SO'...output signal SO
average value.
Claims (1)
号と比較し、その結果に応じてアツプダウンカウ
ントのカウント方向を選択し、かつ選択されたカ
ウント方向に従つてクロツクパルスのタイミング
でカウントするアツプダウンカウントのカウント
値が、前記Ｄ／Ａコンバータにより前記出力信号
にアナログ変換されるアナログメモリ回路におい
て、 前記入力アナログ信号と、前記Ｄ／Ａコンバー
タの出力信号との差の絶対値を検出する絶対値検
出手段と、前記絶対値に応じて前記クロツクパル
スの周波数を変更する周波数制御手段とを備えた
ことを特徴とするアナログメモリ回路。[Claims for Utility Model Registration] Compare the input analog signal with the output signal of the D/A converter, select the counting direction of the up-down count according to the result, and adjust the timing of the clock pulse according to the selected counting direction. In an analog memory circuit in which a count value of an up-down count counted by is analog-converted into the output signal by the D/A converter, the absolute value of the difference between the input analog signal and the output signal of the D/A converter 1. An analog memory circuit comprising: absolute value detection means for detecting the absolute value; and frequency control means for changing the frequency of the clock pulse in accordance with the absolute value.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9236686U JPH0427040Y2 (en) | 1986-06-17 | 1986-06-17 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9236686U JPH0427040Y2 (en) | 1986-06-17 | 1986-06-17 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62202700U true JPS62202700U (en) | 1987-12-24 |
| JPH0427040Y2 JPH0427040Y2 (en) | 1992-06-29 |
Family
ID=30954010
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9236686U Expired JPH0427040Y2 (en) | 1986-06-17 | 1986-06-17 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0427040Y2 (en) |
-
1986
- 1986-06-17 JP JP9236686U patent/JPH0427040Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0427040Y2 (en) | 1992-06-29 |
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