JPH03114065U - - Google Patents
Info
- Publication number
- JPH03114065U JPH03114065U JP2392590U JP2392590U JPH03114065U JP H03114065 U JPH03114065 U JP H03114065U JP 2392590 U JP2392590 U JP 2392590U JP 2392590 U JP2392590 U JP 2392590U JP H03114065 U JPH03114065 U JP H03114065U
- Authority
- JP
- Japan
- Prior art keywords
- period
- voltage
- during
- output
- input voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 3
Description
第１図は、この考案の自動オフセツト電圧補正
装置の一例を示すブロツク図、第２図は、その動
作の説明に供するタイムチヤート、第３図は、入
力電圧と増幅器の出力電圧の一例を示す波形図、
第４図は、従来の自動オフセツト電圧補正装置の
一例を示すブロツク図である。
Fig. 1 is a block diagram showing an example of the automatic offset voltage correction device of this invention, Fig. 2 is a time chart for explaining its operation, and Fig. 3 shows an example of input voltage and output voltage of an amplifier. waveform diagram,
FIG. 4 is a block diagram showing an example of a conventional automatic offset voltage correction device.
Claims (1)
れに続く無信号期間からなる入力電圧を増幅する
増幅器と、 この増幅器の出力電圧を基準電圧と比較するコ
ンパレータと、 上記入力電圧の無信号期間内の上記コンパレー
タの出力が高レベルまたは低レベルとなる期間に
おいて上記入力電圧の周期より十分短い周期のク
ロツクをカウントアツプし、上記入力電圧の無信
号期間内の上記コンパレータの出力が低レベルま
たは高レベルとなる期間において上記クロツクを
カウントダウンするとともに、上記入力電圧の信
号期間においてカウント停止状態にされるアツプ
ダウンカウンタと、 このアツプダウンカウンタの出力データをアナ
ログ電圧に変換し、そのアナログ電圧をフイード
バツク電圧として上記増幅器に供給するＤＡコン
バータと、 を備える自動オフセツト電圧補正装置。[Claims for Utility Model Registration] An amplifier that amplifies an input voltage that has periodicity and each period consists of a signal period followed by a no-signal period, and a comparator that compares the output voltage of this amplifier with a reference voltage. , during the period in which the output of the comparator is at a high level or low level during the no-signal period of the input voltage, a clock whose cycle is sufficiently shorter than the period of the input voltage is counted up, An up-down counter that counts down the clock during the period when the output of the comparator is at a low level or high level, and stops counting during the signal period of the input voltage, and converts the output data of this up-down counter into an analog voltage. and a DA converter that supplies the analog voltage to the amplifier as a feedback voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2392590U JPH03114065U (en) | 1990-03-09 | 1990-03-09 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2392590U JPH03114065U (en) | 1990-03-09 | 1990-03-09 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03114065U true JPH03114065U (en) | 1991-11-22 |
Family
ID=31526904
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2392590U Pending JPH03114065U (en) | 1990-03-09 | 1990-03-09 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03114065U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2000057546A1 (en) * | 1999-03-19 | 2000-09-28 | Fujitsu Limited | Method of improving amplifier input offset, and amplifier |
| KR100532168B1 (en) * | 1997-04-24 | 2006-01-27 | 산요덴키가부시키가이샤 | Current detecting circuit having a automatic correlation circuit of offset voltage |
-
1990
- 1990-03-09 JP JP2392590U patent/JPH03114065U/ja active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100532168B1 (en) * | 1997-04-24 | 2006-01-27 | 산요덴키가부시키가이샤 | Current detecting circuit having a automatic correlation circuit of offset voltage |
| WO2000057546A1 (en) * | 1999-03-19 | 2000-09-28 | Fujitsu Limited | Method of improving amplifier input offset, and amplifier |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS5614721A (en) | Analog-digital converter | |
| JPH03114065U (en) | ||
| CA2329374A1 (en) | A pulse width modulated weighing platform | |
| JPH041421U (en) | ||
| JPS5840942U (en) | analog digital converter | |
| JPS6239343U (en) | ||
| EP0067109A3 (en) | Apparatus for signalling the end points of the ramp-down interval in a dual ramp analog to digital converter | |
| JPS60192542U (en) | AD converter | |
| JPH01168886U (en) | ||
| JPS5927414U (en) | automatic level adjustment device | |
| JPH02146313U (en) | ||
| JPS59195837U (en) | day glitch circuit | |
| JPS6138570U (en) | Analog voltage measuring device | |
| SU1280692A1 (en) | Servo analog-to-digital converter | |
| JPS62202700U (en) | ||
| JPS6340034U (en) | ||
| JPS6037938U (en) | A/D conversion circuit | |
| JPS5810016U (en) | Photoelectric encoder failure detection circuit | |
| JPH03109177U (en) | ||
| JPH0390133U (en) | ||
| JPS62180366U (en) | ||
| JPS56136075A (en) | Telephone number and call time recording system | |
| JPS63111030U (en) | ||
| JPS5840941U (en) | analog to digital converter | |
| JPH0225878U (en) |