WO2000057546A1

WO2000057546A1 - Method of improving amplifier input offset, and amplifier

Info

Publication number: WO2000057546A1
Application number: PCT/JP1999/001371
Authority: WO
Inventors: Kazuyoshi Shimizu
Original assignee: Fujitsu Limited
Priority date: 1999-03-19
Filing date: 1999-03-19
Publication date: 2000-09-28

Abstract

A small-signal amplifier of low current consumption and small circuit scale, whose input offset is improved. The amplifier comprises an amplifier circuit that includes a first input for receiving an input signal and a second input for receiving a reference voltage, an up/down counter, and a D/A converter for converting the count of the up/down counter to a corresponding analog value. The output of the D/A converter is the reference voltage. The amplifier further comprises an offset comparator for comparing the reference voltage from the amplifier circuit with the output voltage to produce the difference signal, and a counter control section that generates an increment signal for incrementing the up/down counter according to the output from the offset comparator. An ROM control section generates an increment signal for controlling the increment of the up/down counter so that the output of the offset comparator may become zero.

Description

Description Method for improving input offset of amplifier and amplifier to which the method is applied

The present invention relates to a method for improving an input offset in an amplifier for amplifying a small signal, and an amplifier to which the method is applied. Background art

In recent years, with the spread of burst signal transmission systems and the like, the necessity of a technique for compensating for the input offset of an amplifier has increased. An optical transmission system shown in FIG. 12 is an example of a burst signal transmission system. In the system shown in FIG. 12, the terminal 1 to the terminal N are connected to an optical receiving unit 300 through an optical fiber transmission line 200 via an optical power plug 100 on the way.

In the optical power plug 100, the optical signals transmitted from the terminal 1 to the terminal N are time-division multiplexed, while the multiplexed optical signal from the optical receiving unit 300 is And distributed to each terminal.

Here, the optical signals transmitted from the terminal 1 to the terminal N become burst optical signal trains having different levels due to variations in the optical fiber transmission line 200 connecting each terminal and the optical power bracket 100. It is input to the receiving section 300.

In the optical receiving section 300, the burst train of the input optical signal is converted into an electric signal of a corresponding level by the O / E conversion circuit 301. The burst signal sequence converted into the electric signal is widened by the main amplifier 302 so that the level becomes uniform. The output of the main amplifier 302 is converted into a digital signal by the decoder circuit _{303. In} such a system as shown in Fig. 12, the input level of the burst signal train with different levels is suppressed while suppressing the pulse width fluctuation. It is necessary to convert the signal sequence into a uniform signal sequence so as not to cause an identification error in the decoder circuit 303. The problem here is the input offset in the amplifier.

FIG. 13 is a diagram illustrating an input offset in the amplifier. amplification In general, the input-to-output characteristics of the device include a linear region I and regions Π and 示す that exhibit saturation characteristics in regions where the input potential is high and low. When the operating point, that is, the center level of the input signal of the amplifier is in the center of this linear region I, the input signal can be ideally amplified.

However, when an input offset voltage is generated and the center level of the input signal approaches the saturation characteristic area Π or m, the output of the amplifier will be in a state where the output amplitude value is limited (limited), and the output waveform will be distorted. . As a result, binary identification cannot be performed correctly for digital signals. Therefore, it is important for the amplifier to compensate for the input offset voltage.

Furthermore, this input offset voltage may be inherently applied during the manufacture of the amplifier, or may be caused by temperature fluctuations of the components of the amplifier. FIG. 14 is a diagram illustrating a method of compensating for an input offset voltage in an amplifier in the above-described burst transmission. FIG. 14 (A) shows the configuration of the amplifier, and FIG. 14 (B) shows an operation time chart thereof.

The circuit of FIG. 14 includes a peak detection circuit 310 for detecting a peak value and a bottom value of the signal input a when there is no signal between burst signals, and a bottom detection circuit 311. The peak detection circuit 310 and the bottom detection circuit 311 are reset between burst signals by a reset pulse d. As a result, the peak value and the bottom value of the input signal a when there is no signal can be detected.

The detected peak value and bottom value are resistance-divided and given as a reference potential of the amplifier circuit 312. Here, when there is no input offset in the amplifier circuit 312, the signal input a matches the reference potential, and therefore, the non-inverted output and the inverted output level of the amplifier circuit 312 match. If there is an input offset, the normal output and inverted output levels will not match.

Therefore, the switch SW is closed by the offset reset signal e, and the difference between the non-inverted output and the inverted output level is controlled to return to the reference potential through the comparison amplifier 313. Therefore, by this feedback control, the difference between the normal output and the inverted output level is controlled to be zero, and the input offset is canceled.

However, in the configuration of FIG. 14, the peak detection circuit 310 and the bottom detection circuit In addition to the reset operation of the circuit 311 (for discharging the charging element in the circuit not shown), an offset reset pulse for closing the switch SW is required. This has the disadvantage that control is complicated.

In addition, the ratio of the time required for the reset and the offset reset becomes larger than the time shown in the overall control. As a result, the interval between burst signals becomes longer, which is inevitably unsuitable for high-speed optical signal transmission systems.

In addition to the conventional offset compensation method, which differs from the method shown in Fig. 14 in which the DC component is fed back to compensate for the input offset, a configuration in which amplifiers with low gain are connected in multiple stages has been used up to now. . In this case, the disclosure of the invention _c had a problem that the current consumption and the circuit scale would increase.

Accordingly, an object of the present invention is to provide a reset required in the configuration shown in FIG. 14 described above, an offset improvement method that enables offset compensation of an amplifier that does not require offset reset control, and an application of the method. To provide an amplifier that does this.

It is a further object of the present invention to provide an offset improvement method that enables offset compensation of an amplifier that can reduce current consumption and circuit size.

It is still another object of the present invention to provide an offset improvement method that can be applied to burst signal transmission and that enables offset compensation of an amplifier to be advantageous, and an optical reception amplifier to which the method is applied.

To achieve the above object, the offset improvement method according to the present invention comprises: an amplifier circuit having a first input terminal to which an input signal is applied and a second input terminal to which a reference voltage is applied; And a series circuit of a current source and a trimming resistor capable of trimming a resistance value, wherein a voltage generated at the trimming resistor is configured as the reference voltage. An offset comparison unit that compares an output voltage and outputs a difference signal, and a trimming control unit that controls a trimming amount of the trimming resistor based on an output of the offset comparison unit. When the input signal is absent, the output of the offset comparing unit is controlled by the trimming control unit. The trimming amount of the resistance value of the trimming resistor is controlled to be zero.

Second, the offset improvement method according to the present invention provides an amplifier having an amplifier circuit having a first input terminal to which an input signal is applied and a second input terminal to which a reference voltage is applied, and a read address. Correspondingly, a ROM that outputs a digital signal and a D / A converter that converts the digital signal output of the ROM into an analog signal are provided, and the output of the D / A converter is used as the reference voltage.

Further, an offset comparator for comparing the reference voltage of the amplifier circuit with an output voltage and outputting the difference signal, and a read address corresponding to a digital signal to be read from the ROM based on the output of the offset comparator. A ROM control unit to be generated is provided externally, and the ROM control unit responds to a digital signal to be read from the ROM so that the output of the offset comparing unit becomes zero when the input signal is absent. A read address to be generated is generated.

Thirdly, in the offset improvement method according to the present invention, in the second aspect, the amplifier further includes a temperature detection unit, and shifts a read address of the ROM in accordance with an output of the temperature detection. The control is performed so that

Fourth, an amplifier according to the present invention includes an amplifier circuit having a first input terminal to which an input signal is applied and a second input terminal to which a reference voltage is applied, an up / down counter, and a count of the up / down counter. A DZA converter for converting a value into a corresponding analog value, wherein an output of the DZA converter is used as the reference voltage. An offset comparator for comparing a reference voltage of the amplifier circuit with an output voltage and outputting a difference signal; a step for controlling a step of the up / down counter based on an output of the offset comparator; An up / down counter control unit for generating a binary signal, wherein the ROM control unit steps up the count value of the up / down counter so that the output of the offset comparison unit becomes zero. It is characterized by generating signals.

Fifthly, an amplifier according to the present invention includes an amplifier circuit having a first input terminal to which an input signal is applied and a second input terminal to which a reference voltage is applied, and an output of the amplifier circuit and a reference to the amplifier circuit. Feedback control is applied to the second input terminal of the amplifier circuit so that the voltages match. An amplifier that adds a signal having a predetermined amplitude to the input signal; a first input terminal to which the input signal is applied; and an output circuit that outputs a predetermined amplitude to the input signal. The peak value and the bottom value of the signal to which the signal of the amplitude is added are obtained, the magnitude is divided by a predetermined resistance, and the difference from the reference voltage is fed back to the second input terminal of the amplifier circuit. And a circuit.

Sixthly, in the amplifier according to the present invention, in the fifth aspect, the signal having the predetermined amplitude to be added is a sine wave.

Seventh, in the amplifier according to the present invention, in any one of the fourth to sixth aspects, the amplifier circuit includes: a differential amplifier stage including a pair of two-input / one-output transistors; and a reference voltage output stage. The reference voltage output stage is configured by a series circuit of a constant current source having the same size as the differential amplifier stage, and a resistor having a resistance half as large as the collector resistance of the differential amplifier stage. It is characterized by that.

Eighth, in the amplifier according to the present invention, a plurality of amplifier circuits having the same configuration in which an input signal is input to one input terminal in common and different amplifier circuits connected to other input terminals of the plurality of amplifier circuits, respectively A voltage bias power source, and a resistor having the same magnitude connected to the output side of the plurality of amplifier circuits, and commonly output from the plurality of amplifier circuits through respective resistors connected to their output sides. Is obtained. Ninth, the amplifier according to the present invention includes a plurality of amplifier circuits having the same configuration in which an input signal is commonly input to one input terminal, and different voltages connected to the other input terminals of the plurality of amplifier circuits, respectively. And a voltage power supply having the same configuration connected to the output side of the plurality of amplifier circuits and the output current of each voltage / current converter connected to the output side of the plurality of amplifier circuits. Is characterized by having a resistor for converting the voltage into a voltage.

In a tenth aspect, an optical receiving amplifier according to the present invention includes an amplifier having any one of the fourth to ninth features, including an optical receiving element on an input side, and the amplifier includes an optical signal received by the optical receiving element. An electric signal converted into a current is input, and an identifier for identifying an output level of the amplifier at an output side; and a port for extracting a port of the optical signal from an output of the amplifier. And a clock extraction circuit. Further objects and features of the present invention will be described with reference to the accompanying drawings. It becomes clear from the form. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a block diagram of a configuration example of an amplifier for explaining a first embodiment to which the present invention is applied.

FIG. 2 is a diagram showing a specific example of an amplifier in each of the embodiments including the first embodiment to which the present invention is applied.

FIG. 3 is a block diagram of a configuration example of an amplifier illustrating a second embodiment to which the present invention is applied.

FIG. 4 is a block diagram of a configuration example of an amplifier for explaining a third embodiment to which the present invention is applied.

FIG. 5 is a block diagram of a configuration example of an amplifier for explaining a fourth embodiment to which the present invention is applied.

FIG. 6 is a block diagram of a configuration example of an amplifier for explaining a fifth embodiment to which the present invention is applied.

FIG. 7 is a diagram for explaining the operation of the fifth embodiment.

FIG. 8 is a block diagram of a configuration example of an amplifier for explaining a sixth embodiment to which the present invention is applied.

FIG. 9 is a diagram for explaining the operation of the sixth and seventh embodiments.

FIG. 10 is a block diagram of a configuration example of an amplifier for explaining a seventh embodiment to which the present invention is applied.

FIG. 11 is a block diagram showing a configuration example of an optical receiving amplifier to which any of the amplifiers of the above embodiments is applied.

FIG. 12 is a diagram illustrating an optical transmission system as an example of a burst signal transmission system.

FIG. 13 is a diagram illustrating an input offset in the amplifier.

FIG. 14 is a diagram illustrating one method of compensating for such an input offset in an amplifier. BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, the same or similar items will be described with the same reference numerals or reference symbols.

FIG. 1 is a block diagram of a configuration example of an amplifier for explaining a first embodiment to which the present invention is applied. FIG. 1 shows an amplifier 10 configured as one element including an amplifier circuit 1, a current source 2, and a trimming resistor 3.

The embodiment of FIG. 1 is an example in which the offset characteristic inherently given when the amplifier 10 is manufactured as one element is compensated.

The amplifier circuit 1 has a configuration shown in FIG. 2 as an embodiment. It has a differential amplifier stage composed of a pair of transistors each including a pair of FETs having two inputs and one output, and a reference voltage REF output stage. The reference voltage R E F output stage is composed of a series circuit of a constant current source having the same size as that of the differential amplifier stage and a resistor having a resistance half the collector resistance of the differential amplifier stage.

A signal is input to one of the two inputs of the differential amplification stage, and a reference voltage determined by the constant current of the current source 2 and the resistance value of the trimming resistor 3 is input to the other.

Returning to FIG. 1, as an embodiment of the present invention, an offset comparator 11 and a trimming controller 12 are provided externally to the amplifier 10. The offset comparator 11 detects a difference between the reference voltage R EF and the output voltage and outputs the difference.

When offset compensation is performed, the input signal a is set to the non-signal state. If there is no input offset, the output voltage of the amplifier circuit 1 and the reference voltage R EF are equal. Therefore, the trimming controller 12 adjusts the resistance value of the trimming resistor 3 so that the output voltage of the offset circuit 11 becomes zero so that the output voltage of the width circuit 1 matches the reference voltage REF. The trimming current is generated and output for the purpose.

Trimming control unit 1 2 The trimming current of the trimming resistor trims the resistance value of trimming resistor 3, and the input reference voltage is determined by the constant current of current source 2 and the trimmed resistance value of trimming resistor 3. Is determined. The input reference voltage at this time is a voltage whose offset at the time of manufacture has been adjusted.

FIG. 3 shows another embodiment in which the offset characteristic fixedly provided when the amplifier 10 is manufactured as one element is further adjusted. In this embodiment, ROM 4 and And a D / A converter 5. Accordingly, in response to this, a ROM control unit 13 is provided instead of the trimming control unit 12.

In comparison with the embodiment of FIG. 1, in the embodiment of FIG. 1, since the adjustment method for trimming the resistance value of the trimming resistor 3 is difficult, it is difficult to adjust in both directions. On the other hand, in the embodiment of FIG. 3, since the read address of the ROM 4 is only updated by the ROM control unit 13, the adjustment of the input offset in both directions is easy. That is, the output of the D / A converter 5 is set so that the output of the offset comparator 11 becomes a zero value. For this purpose, the ROM control unit 13 generates and outputs an address value for reading from the ROM 4 a digital value corresponding to the output of the D / A converter 5 to be set. In this way, it is possible to eliminate the input offset of the amplifier 10.

FIG. 4 shows a configuration in which the offset variation due to temperature is further compensated for in the embodiment of FIG. A temperature detecting element such as a thermistor is provided as a temperature detecting section 6 in the amplifier 10, and an A / D conversion circuit 7 for converting an analog value of the temperature detecting section 6 into a digital value is provided in response to the temperature detecting element. .

Therefore, similarly to the embodiment of FIG. 3, the ROM control unit 2 outputs the read address of the ROM 4 so that the output of the offset comparing unit 11 becomes zero. At the same time, control is performed such that the read address of ROM 4 is shifted by the digital output of the AZD conversion circuit 7 corresponding to the analog value of the temperature detection unit 6.

Thereby, in the embodiment of FIG. 4, it is possible to correct the correction value for the input offset fluctuation depending on the temperature.

FIG. 5 is a block diagram of a fourth embodiment of the present invention, in which an input offset during use is corrected. In this embodiment, as the configuration of the amplifier 10, an offset comparator 11, an up / down counter controller 13, and an up / down counter controlled by an up / down counter controller 13 are integrated with the amplifier circuit 1. It has a power counter 15.

In this embodiment, the offset comparator 11 compares the output of the amplifier circuit 1 with the reference voltage REF in a state where nothing is input as the signal input a. Then, the up-down counter control unit 13 sets the two inputs of the offset comparison unit 11 to the same potential. Control the up-down counter 14 as follows.

In other words, in the state where nothing is input as the signal input a, the offset value is initially set so that the offset is zero, so that the two inputs of the offset comparator 11 have the same potential.

The count value of the up / down counter 14 is controlled based on the initially set up / down counter 14 count value so that the two inputs of the offset comparator 11 always have the same potential. Controlled by unit 13 This makes it possible to cancel the input offset of the amplifier 10.

Here, the up / down counter control unit 13 is easily realized by a circuit having a function of generating a chirp signal every time the output of the offset comparison unit 11 exceeds the soil threshold.

FIG. 6 is a block diagram of an amplifier 10 showing a fifth embodiment of the present invention. In this embodiment, even when the offset is deep and the output of the amplifier circuit 1 is in the limiter operating state, the offset information can be left in the amplifier output.

That is, a sine wave is superimposed as an addition signal b in the adder 15 as an embodiment on the input signal a input to the amplification circuit 1. FIG. 7 shows an input signal waveform and an output signal in the embodiment in FIG.

Referring to FIG. 7, if there is only the input pulse signal a, the output signal exceeds the linearity region I of the amplifier and enters the limiter regions n and m as shown by A in FIG. Therefore, the peak or bottom potential of the original output signal cannot be detected.

On the other hand, in the present embodiment, the addition signal b is superimposed on the input signal a. Therefore, in FIG. 6, the output of the amplifier circuit 1 is guided to the filter 16 that passes the added signal b component. The output of the filter 16 is input to a peak detection circuit 17 and a bottom detection circuit 18.

The average value of the outputs of the peak detection circuit 17 and the bottom detection circuit 18 is obtained by the resistors R 1 and R 2, and is used as one input of the offset comparison unit 11. The potential input to one of the offset comparators 11 at this time is indicated by B in FIG. That is, since a sine wave is superimposed as the addition signal b, a peak or The potential information masked by the bottom potential can be detected.

In FIG. 6, the offset comparing section 11 further transfers the difference between the potential input to one of the offset comparing sections 11 and the reference voltage REF of the amplifier circuit 1 to the integrating circuit formed by the resistor R 3 and the capacitor C. The signal is fed back to the amplifier circuit 1 through the buffer circuit 19. Therefore, as in the previous embodiments, also in the present embodiment, feedback control is performed so that the inputs of the offset comparing section 11 become equal, so that the offset can be controlled to a predetermined value.

FIG. 8 is a block diagram showing the configuration of still another embodiment of the present invention. In FIG. 8, the amplifier 10 has a plurality of n amplifier circuits 101 to 10n having the same configuration. Furthermore, the corresponding amplifier circuits 101 to 10n are provided with corresponding different bias voltages Vb1 to Vbn .: The signal inputs are commonly applied to the amplifier circuits 101 to 10n. Configuration.

Therefore, as shown in FIG. 9, due to the input / output characteristics common to the amplifier circuits 101 to 10n, depending on the applied bias voltage, the respective outputs can be adjusted in the linearity (linear) region I, Or it becomes the limiter area Π or ΠΙ.

Therefore, in the embodiment of FIG. 8, the outputs of the plurality of amplifier circuits 101 to 10n are resistance-added through the corresponding resistors 201 to 20n. As a result, a summed and averaged output waveform (see FIG. 9, IV) is obtained. An output that amplifies the signal input a is obtained without being affected by the offset voltage due to the added output waveform.

FIG. 10 is a block diagram of an embodiment configuration obtained by further improving the embodiment of FIG. In the embodiment of FIG. 8, the outputs of the plurality of amplifying circuits 101 to 10n are resistance-added. However, in this case, voltage amplitude attenuation occurs due to the resistors 201 to 20n.

On the other hand, the embodiment of FIG. 10 includes voltage-to-current conversion circuits 401 to 40n for current-converting the respective outputs of the amplifiers 201 to 20n. Further, the outputs of the voltage-current conversion circuits 401 to 40n are added to current by the resistor 400.

As a result, as shown in FIG. 9, an output obtained by adding the outputs of the plurality of amplifiers 201 to 20n is obtained as in the embodiment of FIG. This embodiment has an advantage that the voltage amplitude can be prevented from attenuating due to the resistance as compared with the embodiment of FIG.

FIG. 11 is a block diagram showing an example of the configuration of an optical receiving amplifier as an application example of the amplifier according to the present invention. FIG. In FIG. 11, an optical receiving element 50 and an optical current corresponding to the received light of the optical receiving element 50 are amplified on the input side of the amplifier 10 having any one of the configurations of the above embodiments of the present invention. It has a preamplifier 51. Therefore, the amplifier 10 functions as a main amplifier, and the amplified output is guided to the discriminator 52 and the clock extraction circuit 53.

Such an optical receiving amplifier can amplify a received signal without distortion even for a burst signal by using it as an optical receiving unit 300 in the optical transmission system described with reference to FIG. Industrial applicability

As described above according to the embodiments, the present invention provides an amplifier that prevents an increase in current consumption and circuit scale and has improved input offset. The amplifier with improved input offset according to the invention can be applied in particular in burst transmission.

Claims

The scope of the claims

1. The amplifier has an amplifier circuit having a first input terminal to which an input signal is applied and a second input terminal to which a reference voltage is applied, and a series circuit of a current source and a trimming resistor capable of trimming a resistance value. A voltage generated at the trimming resistor is used as the reference voltage;

An offset comparing section that compares a reference voltage of the amplifier circuit with an output voltage and outputs a difference signal; and controls a trimming amount of a resistance value of the trimming resistor based on an output of the offset comparing section. A trimming control unit is provided externally,

The trimming control unit controls the amount of trimming of the trimming resistor so that the output of the offset comparing unit becomes zero when the input signal is absent. A method for improving the input offset of an amplifier, characterized in that:

2. An amplifier having a first input terminal to which an input signal is applied and a second input terminal to which a reference voltage is applied, a ROM that outputs a digital signal corresponding to a read address, and a ROM of the ROM. A D / A converter for converting a digital signal output to an analog signal, wherein the output of the DZA converter is used as the reference voltage, and further, a reference voltage of the amplifier circuit is compared with an output voltage An offset comparing unit that outputs the difference signal; and a ROM control unit that generates a read address corresponding to a digital signal to be read from the ROM based on the output of the offset comparing unit.

The ROM control unit generates a read address corresponding to a digital signal to be read from the ROM so that when the input signal is absent, the output of the offset comparison unit becomes zero. A method for improving the input offset of an amplifier.

3. The amplifier according to claim 2, further comprising a temperature detector, wherein the amplifier is controlled to shift a read address of the ROM in response to an output of the temperature detection. Input offset improvement method.

4. an amplifier circuit having a first input terminal to which an input signal is applied and a second input terminal to which a reference voltage is applied;

Up-down force counter, A DZA converter for converting the count value of the up-down counter into a corresponding analog value;

The output of the DZA converter is configured to be the reference voltage.

An offset comparator for comparing an output voltage with a reference voltage of the amplifier circuit and outputting a difference signal;

An up / down counter control unit that generates a step signal for controlling the step of the up / down counter based on the output of the offset comparison unit;

The ROM control unit generates a step signal so as to increment the count value of the up / down counter so that the output of the offset comparison unit becomes zero.

5. An amplifier circuit having a first input terminal to which an input signal is applied and a second input terminal to which a reference voltage is applied, and an output circuit of the amplification circuit and a reference voltage of the amplification circuit are matched with each other. In an amplifier that performs feedback control to a second input terminal of the amplifier circuit,

An adder circuit for adding a signal having a predetermined amplitude to the input signal on a first input end side to which the input signal is applied;

On the output side of the amplifying circuit, a peak value and a bottom value of a signal obtained by adding a signal of a predetermined amplitude to the input signal are obtained, the magnitudes thereof are divided by a predetermined resistance, and a difference between the reference voltage and the reference voltage is obtained. A feedback circuit that feeds back to the second input of the amplifier circuit

An amplifier, comprising:

0 6. In claim 5,

The signal of the predetermined amplitude to be added is a sine wave.

7. The amplifying circuit according to any one of claims 4 to 6, wherein the amplifying circuit includes a differential amplifier stage including a pair of two-input one-output transistors, and a reference voltage output stage. The amplifier is characterized in that the stage is constituted by a constant current source having the same size as the differential amplifier stage, and a series circuit of a resistor having a resistance value that is half the collector resistance of the differential amplifier stage.

8. A plurality of amplifier circuits having the same configuration in which an input signal is input to one input terminal in common, a bias power supply of a different voltage connected to each of the other input terminals of the plurality of amplifier circuits, The plurality of amplifier circuits have the same resistance connected to the output side thereof, and are configured to obtain common output from the plurality of amplifier circuits through respective resistors connected to their output sides. An amplifier, characterized in that:

9. A plurality of amplifying circuits having the same configuration in which an input signal is commonly input to one input terminal, a bias power supply of a different voltage connected to each of the other input terminals of the plurality of amplifying circuits,

A voltage / current converter of the same configuration connected to the output side of the plurality of amplifier circuits and a resistor for converting the output current of each voltage Z current converter connected to the output side of the plurality of amplifier circuits into a voltage. An amplifier, comprising:

10. An amplifier according to any one of claims 4 to 9, further comprising a light receiving element on an input side, wherein the amplifier inputs an electric signal obtained by converting a light signal received by the light receiving element into a current,

A discriminator for identifying the level of the output of the amplifier on the output side;

And a clock extracting circuit for extracting a clock of the optical signal from an output of the amplifier.