JPH06310967A - Amplifier circuit - Google Patents

Amplifier circuit

Info

Publication number
JPH06310967A
JPH06310967A JP5116483A JP11648393A JPH06310967A JP H06310967 A JPH06310967 A JP H06310967A JP 5116483 A JP5116483 A JP 5116483A JP 11648393 A JP11648393 A JP 11648393A JP H06310967 A JPH06310967 A JP H06310967A
Authority
JP
Japan
Prior art keywords
circuit
output
amplitude
signal
value
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5116483A
Other languages
Japanese (ja)
Other versions
JP3284506B2 (en
Inventor
Yukio Akazawa
Noboru Ishihara
Masayuki Ishikawa
Makoto Nakamura
誠 中村
昇 石原
正幸 石川
幸雄 赤沢
Original Assignee
Nippon Telegr & Teleph Corp <Ntt>
日本電信電話株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegr & Teleph Corp <Ntt>, 日本電信電話株式会社 filed Critical Nippon Telegr & Teleph Corp <Ntt>
Priority to JP11648393A priority Critical patent/JP3284506B2/en
Priority claimed from US08/227,886 external-priority patent/US5475342A/en
Publication of JPH06310967A publication Critical patent/JPH06310967A/en
Application granted granted Critical
Publication of JP3284506B2 publication Critical patent/JP3284506B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

(57) [Summary] [Purpose] Even if the input signal amplitude changes instantly, it follows this and performs instant offset compensation and gain compensation.
It is an object of the present invention to provide an amplifier circuit that can continue to output a signal with a constant amplitude and a small phase fluctuation. [Structure] A threshold value setting circuit that detects and holds the peak value and the bottom value of the input signal waveform and outputs the intermediate value as a threshold value, and the output amplitude while amplifying the input signal in the linear region around this threshold value. This is a combination with an amplitude limiting amplifier circuit that keeps it constant.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention instantaneously compensates an offset voltage and a gain when a signal input to a voltage amplifier circuit of an optical receiver circuit fluctuates in a wide level, and stably outputs a constant output amplitude. The present invention relates to a voltage amplifier circuit that can continue to operate.

[0002]

2. Description of the Related Art In an optical digital communication system, an amplifier circuit is used especially in an optical receiving circuit section for amplifying an attenuated signal and a timing extracting circuit section for extracting a timing signal from input data and stably outputting a constant clock signal. Is essential. The amplifier circuits used in these circuit parts are required to have a high gain and a wide dynamic range with respect to the input signal level, and further, the output amplitude needs to be always constant.

The optical receiving circuit section is required to have a function of converting an optical signal into a current signal by a photodiode, then converting this current signal into a voltage signal, and amplifying to a voltage amplitude at which logic can be identified. Even if the input signal level changes, the offset voltage and the gain must be compensated so that the voltage amplitude of the output signal is always constant. To realize such a function, conventionally, the function is realized by a combination of a variable gain amplifier circuit and a DC feedback circuit.

By the way, in recent years, an optical communication system using burst-shaped data signals having greatly different signal levels has been studied. As an optical receiving circuit unit, offset voltage and gain are instantly compensated to maintain a constant output amplitude. There is a strong demand for a configuration that can continue.

However, in the conventional example, since the feedback loop is used, there is a problem that the response speed is slow and the change of the input signal cannot be followed. This problem will be described in detail below based on an example of the conventional optical receiving circuit shown in FIG.

In this conventional example, the photodiode 1
The intensity signal of light is converted into a current by 01, the current signal is amplified by the preamplifier 102, and converted into a voltage signal,
The voltage amplification circuit 103 automatically performs offset compensation and gain control to always obtain an output waveform with a constant amplitude.

Here, the offset compensation function means that the threshold value for the input signal of the voltage amplification circuit 103 is always the waveform WF.
Is a function that allows the voltage amplification circuit 103 to operate in a linear region centered on the threshold value by offsetting the DC bias so that it becomes the middle point (the middle point is indicated by the dashed-dotted line). .

That is, the peak value of the output waveform WF of the preamplifier changes depending on the level of the optical digital signal input to the photodiode 101. If this is attempted to be amplified by the normal amplifier circuit as it is, the linear operation range of the amplifier circuit will be changed. Since it can be used only in a half area (one direction based on the bottom value of the waveform), it is not efficient for widening the dynamic range, and the output waveform is likely to be distorted or duty varied. Therefore, an offset is applied to the DC bias to change the threshold so that the threshold for the input signal of the voltage amplifying circuit 103 is always at the midpoint of the waveform WF, and the voltage amplifying circuit 103 has a linear region centered on the changed threshold. To be able to work.

The gain control function is a function of controlling the gain in order to keep the output amplitude constant when the input signal level changes. Note that To is an output terminal of the optical receiving circuit.

Further, the peak value of the output voltage of the variable gain amplifying circuit 110 is detected by the offset automatic compensation control circuit 120 which is a combination of the peak holding capacitance 121 and the voltage amplifying circuit 122, and this detected component is detected by the variable gain amplifying circuit. By feeding back to the offset control terminal d of 110, the peak value of the waveform of the variable gain amplifier circuit 110 is controlled to be a constant level.

Peak holding capacitor 131 and voltage amplifier circuit 13
By the gain control circuit 130 in combination with 2,
By detecting the peak value of the output voltage of the variable gain amplifier circuit 110 and feeding back the component to the gain control terminal c of the variable gain amplifier circuit 110, the output amplitude is controlled to be constant.

By combining these two feedback configurations, offset compensation and gain compensation can be realized at the same time. The automatic offset compensation control circuit 120 and the gain control circuit 130 are each composed of an amplifier circuit and a capacitance, and form a peak detection circuit. The peak detection circuit charges the capacitance when the input is high, When the input is low, the output impedance of the amplifier circuit is increased to interrupt the discharge path and detect and maintain the peak level of the waveform.

[0013]

FIG. 13 is a diagram schematically showing the response characteristic of the input / output waveform of the conventional voltage amplifier circuit described above.

The input waveform of the amplifier circuit 110 is shown in FIG.
As shown in (1), when the small amplitude is instantaneously changed to the large amplitude, the offset compensation and the gain compensation operations are not performed instantaneously. Therefore, the output waveform is changed under the conditions of the gain and the offset voltage during the small amplitude operation. Occur. For this reason, FIG. 13 (2)
The response characteristics are shown in. In this case, in order to settle to the desired output amplitude, it is necessary to wait until the effect of feedback is sufficiently obtained, and the response time at this time is the peak detection circuit (offset automatic compensation control circuit 120, gain control circuit 13).
0) of the capacitance units 121 and 131 and the delay time of the amplification circuit of the negative feedback circuit unit.

In order to set the circuit so that the output waveform has a desired output amplitude as instantaneously as possible, the time constants of the capacitance sections 121 and 131 of the peak detection circuit may be made as small as possible. No response characteristic can be obtained. Further, the time constants of the automatic gain control circuit 130 and the automatic offset compensation circuit 120 are conventionally set with different time constants in order to obtain stable operation. The time constant of is inevitably close, which affects the two feedback loops to each other,
The system may become unstable. The reason why the system becomes unstable in this way is that the relationship between the offset and the gain of the voltage amplification circuit is generally not independent.

As described above, in the voltage amplifying circuit used in the conventional optical receiving circuit, when the input signal level changes instantly, the output waveform fluctuates greatly and it takes a long time to settle to a constant amplitude. Since it takes time, it is difficult to apply as a receiving circuit of a system in which the optical receiving level changes instantly and must respond. That is, the above-mentioned conventional voltage amplifier circuit has a problem that when the input signal level changes instantaneously, the feedback circuit does not respond instantaneously and the amplitude and duty of the output waveform are not stable.

According to the present invention, even if the amplitude of the input signal changes greatly in a moment, offset compensation and gain compensation are performed instantaneously following this, and a signal with a constant amplitude and a small phase fluctuation can be continuously output. It is intended to provide an amplifier circuit.

[0018]

According to the present invention, there is provided a threshold value setting circuit which detects and holds a peak value and a bottom value of an input signal waveform and outputs an intermediate value between them as a threshold value, and an input signal centered around this threshold value. Is combined with an amplitude limiting amplifier circuit that keeps the output amplitude constant while amplifying in the linear region.

[0019]

The present invention detects a threshold value and a bottom value of an input signal waveform and holds them, and outputs an intermediate value as a threshold value, and a threshold setting circuit that amplifies the input signal in a linear region around this threshold value. However, because it is combined with an amplitude limiting amplifier circuit that keeps the output amplitude constant, offset compensation and gain compensation can be performed instantly even if the input signal level fluctuates greatly, and the output signal amplitude remains constant with low phase fluctuations. It is possible to keep on. Further, by increasing the number of stages of the basic circuit in which the threshold value setting circuit and the amplitude limiting amplifier circuit are combined, a wide dynamic range can be achieved, and the offset variation generated at the time of manufacturing the integrated circuit can be reduced.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a basic circuit B which is an embodiment of the present invention.
It is a circuit diagram which shows C1.

The basic circuit BC1 is an automatic threshold setting circuit (A
A TC (Automatic Threshold Controll) 10 and an amplitude limiting amplifier circuit 40, and has an input terminal Ti and an output terminal To.

The automatic threshold value setting circuit 10 is an example of a threshold value setting circuit that detects and holds the peak value and the bottom value of the input waveform, and outputs a value approximately halfway between the peak value and the bottom value as the threshold value. The value detecting / holding circuit 20, the bottom value detecting / holding circuit 30, and the resistors R1 and R2 connected in series between the output terminal of the peak value detecting / holding circuit 20 and the output terminal of the bottom value detecting / holding circuit 30. Have and. The peak value detection / holding circuit 20 includes a holding capacitor 21 and an amplifier circuit 22.
Is a circuit for detecting and holding the peak value of the waveform of the input signal at the input terminal Ti, and the bottom value detecting / holding circuit 30 has a holding capacitor 31 and an amplifying circuit 32. It is a circuit that detects and holds the bottom value of the waveform of the input signal.

The peak value detecting / holding circuit 20 charges the holding capacitor 21 when its input signal is high, and raises the output impedance of the amplifier circuit 22 when its input signal is low. By doing so, the discharge path is cut off and the peak value of the waveform is detected and held. On the other hand, the bottom value detecting / holding circuit 30 conversely charges the holding capacitor 31 when the input signal is low, and increases the output impedance of the amplifier circuit 32 when the input signal is high. By this, the discharge path is cut off, and the bottom value of the waveform is detected and held.

The amplitude limiting amplification circuit 40 receives an input signal from the input terminal Ti and a threshold value for operating the input signal in a linear region, and outputs an output limiting amplitude within a predetermined input signal level range. This is an example of a circuit and has an input terminal a, an output terminal b, and a threshold (offset voltage) setting terminal d.

The input terminal Ti of the basic circuit BC1 is connected to the input terminal of the amplitude limiting amplification circuit 40 and the input terminal of the automatic threshold setting circuit 10, and the output terminal of the automatic threshold setting circuit 10 is the output terminal of the amplitude limiting amplification circuit 40. The basic circuit BC is connected to the threshold control terminal d and is connected to the output terminal b of the amplitude limiting amplifier circuit 40.
The output terminal To of No. 1 is connected.

Next, the operation of the above embodiment will be described.

First, the peak value detection / holding circuit 20 and the bottom value detection / holding circuit 30 respectively extract the peak value and the bottom value of the input signal waveform, and the potential at the midpoint between the peak value and the bottom value is the resistance R1. , R2 obtained by resistance division, and by applying the potential at this midpoint as a threshold value (offset voltage value) of the amplitude limiting amplifier circuit 40, offset compensation operation is performed.

A gain compensation operation is realized by limiting the output amplitude within a certain input signal level range using the amplitude limiting amplifier circuit 40.

Compared with the conventional example shown in FIG. 12, the above-mentioned embodiment does not use a negative feedback loop, so that the response time of offset compensation and gain compensation due to the delay of loop response is not limited. In the above embodiment, the response time is limited to the time constants of the peak value detecting / holding circuit 20 and the bottom value detecting / holding circuit 30, but even if the time constants are set to be somewhat small, the conventional example shown in FIG. The whole circuit does not become unstable like. Therefore, in the above embodiment, the offset compensation and the gain compensation can be realized at the same time within the time within 1 bit of the signal.

FIG. 2 is a diagram showing the result of input / output waveform simulation in the above embodiment. 0.8μ
Simulation was performed assuming the MOS integrated circuit technology of m, and the code rate of the signal given as an input signal is 32 Mb.
/ S.

In FIG. 2A, the signal waveform 51 at the input terminal Ti, the output signal waveform 52 of the peak value detecting / holding circuit 20, the output signal waveform 53 of the bottom value detecting / holding circuit 30, and the automatic threshold setting. Output signal waveform 5 of circuit 10
4 is described. In FIG. 2 (2), the output signal waveform 55 of the amplitude limiting amplifier circuit 40 is shown. The output signal waveform 54 of the automatic threshold setting circuit 10 is the waveform of the signal applied to the threshold control terminal d of the amplitude limiting amplification circuit 40, and the output signal waveform 55 of the amplitude limiting amplification circuit 40.
Is the waveform of the output signal of the basic circuit BC1.

In the above embodiment, the input signal level transits from the small amplitude to the large amplitude, and at the same time, the output signal waveform 52 of the peak value detecting / holding circuit 20 and the output signal waveform 53 of the bottom value detecting / holding circuit 30 follow each other. However, it can be seen that the threshold value which is the output signal waveform 54 of the automatic threshold value setting circuit 10 is instantly set within 1 bit of the data.

The amplitude limiting amplifier circuit 40 receives the input signal and the threshold voltage and performs an amplifying operation for limiting the output amplitude.
In this case, since the threshold value is set at the midpoint of the input signal waveform 41, the output signal waveform 55 of the amplitude limiting amplifier circuit 40
As shown in FIG. 2B, the output waveform of the basic circuit BC1 can continue to output a signal having a constant amplitude with almost no waveform distortion or duty fluctuation.

As described above, in the above embodiment, the offset compensation and the gain compensation are instantaneously performed with respect to the fluctuation of the input signal level, and the signal of the constant amplitude is continuously output without causing the waveform distortion and the duty fluctuation. You can

FIG. 3 is a circuit diagram showing another embodiment of the present invention, which is the same basic circuit B as the basic circuit BC1 shown in FIG.
FIG. 7 is a circuit diagram showing a case where C2, ..., BCn are cascade-connected in n stages.

By serially connecting the basic circuits BC1, BC2, ..., BCn in multiple stages, it is possible to amplify the input signal in a wide dynamic range, and at the same time, the amplifying circuit 22 caused by element variation at the time of manufacturing the integrated circuit. ,
It is possible to allow threshold variations of the resistors 32 and 40, the resistors R1 and R2, the storage capacitors 21 and 31, and the like. These will be described below.

FIG. 4 schematically shows a level diagram in the embodiment shown in FIG.

In FIG. 4, when the input signal level of the basic circuit BC1 is x, the output amplitude is limited by the second-stage basic circuit BC2, and when the input signal level of the basic circuit BC1 is y. When the output amplitude is limited by the third-stage basic circuit BC3 and the input signal level of the basic circuit BC1 is z, which is even smaller, the output amplitude is limited by the n-th basic circuit BCn. It can be seen that if the number of stages of the basic circuit is increased in this way, the minimum input level of the basic circuit BC1 (basic circuit of the first stage) can be reduced and the dynamic range can be expanded as the number of stages increases.

FIG. 5 is a diagram for explaining the offset compensating operation at each stage in the multi-stage configuration shown in FIG.

In FIG. 5, the output of the automatic threshold setting circuit 10 in the first stage (basic circuit BC1) is the center of the input signal in consideration of element variations (transistor performance, resistance value, and capacitance value variations) at the time of manufacturing the integrated circuit. It shows how the amount deviating from the value changes as the number of stages increases.

Thick arrows 51a, 51b, 51c indicate the input signal amplitude of each amplification stage, P1, P2, P3 indicate the output level of the peak value detection / holding circuit 20 in each stage, and B1, B2, B3. Is the bottom value detection at each stage.
Indicates the output level of the holding circuit 30, which is Vtl, Vt2, V
t3 indicates the output level of the automatic threshold setting circuit 10 in each stage.

It is assumed that the peak value detection / holding circuit 20 follows and holds the change from the low level to the high level during the circuit operation, but does not follow the opposite change. On the other hand, it is assumed that the bottom value detection / holding circuit 30 follows and holds the change from the high level to the low level, but does not follow the opposite change. This is the detection of peak value and bottom value.
Since the holding operation generally detects and holds the peak value and bottom value by accumulating electric charge in the capacitor,
This is because, in principle, only one direction can be followed.

In FIG. 5, the threshold value at the first stage is not set at the center of the amplitude of the input signal, but the peak value / bottom value detection / holding operation is repeated along with the amplification operation (reverse amplification operation), and the amplitude at the third stage is repeated. It is set at the center of the signal amplitude at the input of the limiting amplifier circuit 40.

By thus increasing the number of stages, variations in elements (variations in transistor performance, resistance value, and capacitance value) at the time of manufacturing an integrated circuit can be allowed. This is because the resistors are divided by the resistors R1 and R2 when setting the threshold value, and the gain of the threshold value setting of each stage and the gain of the signal amplification are different by 6 dB (2 times). Due to the multi-stage structure, variations at the time of manufacturing can be allowed.

Here, the relationship between the number of stages n and the allowable offset voltage Voff is analytically obtained. From FIG. 5, it is assumed that the voltage gain of the amplifier 40 is Av and the minimum amplitude of the input signal is V
s, the offset voltage is more than the amplified voltage,
Since the condition that the optimum threshold value can be set is that the amplified voltage of the signal exceeds, this conditional expression is given as follows.

Voff · (Av / 2) n · 2 <Vs
· Av n ... (1) Equation When organizing this equation, the Voff <Vs · 2 n-1 ... (2) expression. Here, it should be noted that the allowable offset voltage Voff is determined by the number of stages of the amplifier, regardless of the gain of the amplifier.

FIG. 6 shows a permissible value of the offset voltage (caused by the first stage circuit) generated due to element variations during manufacturing when the minimum amplitude Vs of the input signal is assumed to be 10 mV in the multi-stage configuration shown in FIG. It is the figure which calculated and showed the relationship of the allowable value of the offset voltage) and the number of stages of a circuit based on Formula (2).

From FIG. 6, it can be seen that the allowable value of the offset voltage increases as the number of stages of the basic circuit increases.

FIG. 7 shows a configuration of the multistage configuration shown in FIG.
It is a figure which shows the simulation result of the operation waveform in the case of a stage structure.

In FIG. 7, the amplitude limiting amplifier circuit 4 of each stage is shown.
Input signal waveforms 51-1, 51- at the 0 input terminal
2, 51-3, output waveform 5 of the peak detection circuit 20 of each stage
2-1, 52-2, 52-3, output waveforms 53-1, 53-2, 53-3 of the bottom detection holding circuit 30 of each stage, output waveforms 54-1, 54-2 of the automatic threshold setting circuit 10 , 54
-3, the output waveform 55 of the final stage is shown. The number after the hyphen in the code indicating the waveform indicates the number of stages. For example, the input signal waveform 51-1 indicates the input signal waveform of the first-stage basic circuit BC1 and the output waveform 52-3.
Shows the output signal waveform of the basic circuit BC3 in the third stage.

The input waveform 51-1 in the first stage has a time of 400
The amplitude is 0.0065 V up to ns, 0.065 V up to 700 ns, and 0.65 V thereafter, and the final stage output amplitude is 3.2 V. When the minimum input signal amplitude is 0.0065V, amplitude limitation is applied at the third stage, when the input signal amplitude is 0.065V, amplitude limitation is performed at the second stage, and when the input signal amplitude is 0.65V, the first stage is applied. Amplitude is restricted at. Further, by setting the optimum threshold value, 0.0065V ~
An output waveform with a constant output amplitude and a small duty variation is obtained for a dynamic range of the input signal amplitude of 40 dB at 0.65V.

FIG. 8 is a circuit diagram showing an embodiment in which a reset function is added to the embodiment shown in FIG.

The basic circuit BCa1 shown in FIG. 8 is basically the same as the basic circuit BC1 shown in FIG. 1, except that an automatic threshold setting circuit 10a is provided instead of the automatic threshold setting circuit 10 shown in FIG. The basic circuit BC1 differs from the basic circuit BC1 in that the reset signal terminal 71t is connected to the basic circuit BCa1 via the reset signal buffer amplifier circuit 71. That is, the threshold setting circuit 10a of the basic circuit BCa1
Has a reset signal terminal 71t on the outside thereof, and is provided with the function of making the input signal and the output signal have the same potential by the signal applied to the reset signal terminal 71t.

The automatic threshold value setting circuit 10a is basically the same as the automatic threshold value setting circuit 10, except that a peak value detecting / holding circuit 20a is provided instead of the peak value detecting / holding circuit 20 to detect a bottom value. The difference is that a bottom value detection / holding circuit 30a is provided instead of the holding circuit 30. The peak value detecting / holding circuit 20a is basically the same as the peak value detecting / holding circuit 20, except that an amplifier circuit 22a having a reset signal terminal r is provided instead of the amplifier circuit 22. The bottom value detection / holding circuit 30a is basically the same as the bottom value detection / holding circuit 30, but an amplifier circuit 32 having a reset signal terminal r.
The difference is that a is provided instead of the amplifier circuit 32.

In the embodiment shown in FIG. 1, the peak value detecting / holding circuit 20 and the bottom value detecting / holding circuit 30 follow only the level change in one direction, so that as shown in FIG. A response can be made instantaneously when changing from a small amplitude to a large amplitude, but it does not follow in the opposite case. However, the embodiment shown in FIG. 8 can respond even when the signal amplitude is reduced.

That is, in the embodiment shown in FIG. 8, the charges charged in the hold capacitors 21 and 31 in the peak value detecting / holding circuit 20a and the bottom value detecting / holding circuit 30a are instantaneously discharged by the reset signal. By returning to the initial state when the signal changes from the large amplitude to the small amplitude, the signal can be instantly responded to when the signal changes from the large amplitude to the small amplitude. The reset function of the peak value detection / holding circuit 20a and the bottom value detection / holding circuit 30a is a function of instantly discharging the electric charge charged in the hold capacitors 21 and 31 and returning it to the initial state.

FIG. 9 is a diagram showing the result of simulating the reset operation in the embodiment shown in FIG.

In FIG. 9, an input signal waveform 51 at the input terminal Ti, an output signal waveform 52 of the peak value detecting / holding circuit 20a, an output signal waveform 53 of the bottom value detecting / holding circuit 30a, an automatic threshold (offset voltage) setting circuit. 10a
Output signal waveform 54, the output signal waveform 55 of the amplitude limiting amplifier circuit 40 of FIG. 8, and the reset signal waveform 56 at the reset signal terminal 71t. The setting circuit 10
The output signal waveform 54 of a is the waveform of the signal applied to the threshold control terminal d of the amplitude limiting amplification circuit 40, and the output signal waveform 55 of the amplitude limiting amplification circuit 40 is the waveform of the output signal of the basic circuit BCa1. .

FIG. 9 shows a case where a reset signal is applied after the state where the input signal waveform 51 has a large amplitude is finished, and then the operation is switched to the operation where the input signal waveform 51 has a small amplitude. In FIG. 9, by applying a reset signal, the peak value detecting / holding circuit 20
a output signal (52), bottom value detection / holding circuit 30a
Output signal (53) and the output signal (54) of the automatic threshold setting circuit 10a are returned to the initial state where they have substantially the same potential,
After that, it can be seen that the input signal of small amplitude is followed.

FIG. 10 is a circuit diagram showing another embodiment of the present invention, in which the basic circuit BCa1 shown in FIG. 8 is multistaged.

In this case, the same basic circuit BCa2, ..., BCan as the basic circuit BCa1 are cascaded to form the basic circuit BCa.
Each of the threshold value setting circuits 10a in Ca1, BCa2, ..., BCan has a reset signal terminal outside thereof, and a function applied to the reset signal terminal causes the input signal and the output signal to have the same potential. , And basic circuits BCa1, BCa2, ..., B connected in cascade in multiple stages
The delay circuits 81, 82, ... Are respectively added between the reset signal terminals of the Can, and the basic circuits BCa1, BCa2 ,. Signal terminal 71t
Is set to the entire reset signal terminal.

That is, the reset signal of each stage is delayed by the delay circuits 81, 82, ... And the reset operation becomes stable. That is, when all the stages are reset at the same time, the outputs of the circuits in the respective stages also change, so that the circuits in the second and subsequent stages may be affected by the response characteristics of the output of the previous stage and may not be reset correctly. For this reason, delay circuits 81, 82, ... Are inserted so that the reset operation is sequentially performed from the first stage and each stage can be properly reset to the initial state. .., 7n are provided between the delay circuits 81, 82, ..

FIG. 11 is a diagram showing the result of simulation performed in the embodiment of FIG. 10 when three stages are connected in cascade.

In FIG. 11, the input signal waveforms 51-1 and 51-2 at the input terminals of the amplitude limiting amplifier circuit 40 of each stage,
51-3, output waveform 52 of the peak detection circuit 20a of each stage
-1, 52-2, 52-3, output waveforms 53-1, 53-2, 53-3 of the bottom detection holding circuit 30a of each stage, output waveforms 54-1 and 54-2 of the automatic threshold setting circuit 10a, 5
4-3, the output waveform 55 of the final stage is shown.

As a result of this simulation, a large amplitude signal of 0.65 V is given as the input waveform 51-1 of the first stage, the signal is once set to zero, and then the reset signal is given.
After that, an analysis result when a small amplitude signal of 0.0065 V is given as an input signal of the first stage is shown.

The circuit of each stage receives the delayed reset signal,
The initial states are sequentially set (states in which the outputs of the peak detection / holding circuit 20a, the bottom detection / holding circuit 30a, and the automatic threshold value setting circuit 10a are substantially the same), and then, when a signal with a small amplitude is input, it is instantaneous It can be seen that the response characteristics are obtained. Since this embodiment can tolerate offset variations, it is extremely suitable for integration into an integrated circuit.

In each of the above embodiments, the threshold setting circuit 1
0, 10a outputs a potential intermediate between the detected peak value and the bottom value as a threshold value, but is not limited to the potential intermediate between the detected peak value and the bottom value, and the peak value and the bottom value. It is also possible to output a potential approximately in the middle between and as the threshold value.

In addition to being used for the optical receiving circuit, the above-described embodiment can be used as a high-gain, wide-dynamic-range, low-jitter amplitude limiting amplifier circuit required for a wireless communication system, a measurement system and the like. it can.

[0069]

According to the first aspect of the present invention, the threshold value setting circuit for detecting the peak value and the bottom value of the input signal waveform and outputting the almost midpoint as the threshold value, and the output using this threshold value Since it is combined with an amplitude limiting amplifier circuit that keeps the amplitude constant, offset compensation and gain compensation are performed instantaneously for fluctuations in the input signal level, and signals of constant amplitude are generated with almost no waveform distortion or duty fluctuation. The effect that the output can be continued is achieved. Further, by providing the basic circuit in multiple stages, it is possible to achieve a wide dynamic range, and it is possible to reduce an offset variation that occurs when an integrated circuit is manufactured.

According to the second aspect of the present invention, since the reset function is added to the basic circuit, the peak value and the bottom value of the input signal waveform are instantly returned to the initial state by this reset function. The effect of being able to respond instantly when the input signal changes from a large amplitude to a small large amplitude is obtained.

According to the third aspect of the present invention, a delay circuit is added between the reset signal terminals of the basic circuits cascade-connected in multiple stages, and the reset signal terminals of the first-stage basic circuit are entirely Since it is used as the reset signal terminal, the reset operation is sequentially performed from the first stage, and each stage can be correctly reset to the initial state.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a basic circuit BC1 which is an embodiment of the present invention.

FIG. 2 is a diagram showing an input / output waveform simulation result in the above embodiment.

FIG. 3 is a circuit diagram showing another embodiment of the present invention, which is a circuit diagram showing a case where the basic circuit BC1 shown in FIG. 1 is cascade-connected in n stages.

FIG. 4 is a diagram schematically showing a level diagram in the embodiment shown in FIG.

5 is a diagram illustrating an offset compensation operation at each stage in the multi-stage configuration shown in FIG.

FIG. 6 is a graph showing the relationship between the allowable value of the offset voltage and the number of stages of the circuit, which are generated due to element variations during manufacturing, when the minimum amplitude Vs of the input signal is assumed to be 10 mV in the multi-stage configuration shown in FIG. It is the figure shown.

7 is a diagram showing a simulation result of operation waveforms in a case where the multi-stage configuration shown in FIG. 3 has a three-stage configuration.

8 is a circuit diagram showing an embodiment in which a reset function is added to the embodiment shown in FIG.

9 is a diagram showing a result of simulating a reset operation in the embodiment shown in FIG.

FIG. 10 is a circuit diagram showing another embodiment of the present invention,
The basic circuit BCa1 shown in FIG. 8 has multiple stages.

FIG. 11 is a diagram showing a result of simulation when three stages are cascade-connected in the embodiment of FIG.

FIG. 12 is a circuit diagram showing an example of a conventional optical receiving circuit.

FIG. 13 is a diagram schematically showing response characteristics of input / output waveforms in the conventional voltage amplifier circuit.

[Explanation of symbols]

BC1 to BCn, BCa1 to BCan ... Basic circuit, Ti ... Input terminal, To ... Output terminal, 10, 10a ... Automatic threshold setting circuit, 20, 20a ... Peak value detection / holding circuit, 21, 21a ... Holding capacity, 22, 22a ... Amplification circuit, 30, 30a ... Bottom value detection / holding circuit, 31, 31a ... Holding capacity, 32, 32a ... Amplification circuit, 40 ... Amplitude limiting amplification circuit, 51 ... Input signal waveform at input terminal Ti, 52 ... Peak Output signal waveform of the value detection / holding circuit 20, 53 ... Output signal waveform of the bottom value detection / holding circuit 30, 54 ... Output signal waveform of the automatic threshold setting circuit 55 ... Output signal waveform of the amplitude limiting amplification circuit 40, 51 -1, 51-2, 51-3 ... Amplitude limiting amplifier circuit 40
Input signal waveform of 52-1, 52-2, 52-3 ... Output waveform of peak detection / holding circuit 20, 20a, 53-1, 53-2, 53-3 ... Bottom detection / holding circuit 30, 30a Output waveform, 54-1, 54-2, 54-3 ... Automatic threshold setting circuit 1
Output waveforms of 0 and 10a, 55 ... Final stage output waveform, 71 to 7n ... Reset signal buffer amplifier circuit, 71t ... Reset signal terminal, 81, 82 ... Delay circuit.

Front page continuation (51) Int.Cl. 5 Identification number Office reference number FI Technical indication location H04B 10/06 (72) Inventor Yukio Akazawa 1-1-6 Uchisaiwaicho, Chiyoda-ku, Tokyo Nihon Telegraph and Telephone Corporation Within

Claims (3)

[Claims]
1. A threshold setting circuit which detects and holds a peak value and a bottom value of an input signal waveform and outputs a value approximately intermediate between the peak value and the bottom value as a threshold value; the input signal; An amplitude limiting amplifier circuit that receives an input signal and the threshold value for operating in a linear region and outputs a constant output amplitude in a predetermined input signal level range; And the input terminal of the threshold setting circuit is connected to the input terminal of the basic circuit, the output terminal of the threshold setting circuit is connected to the threshold control terminal of the amplitude limiting amplifier circuit, the output terminal of the amplitude limiting amplifier circuit An amplifier circuit connected to an output terminal of the basic circuit, the basic circuit being configured in one stage, or being composed of a plurality of the basic circuits cascaded to each other.
2. The threshold value setting circuit according to claim 1, wherein the threshold value setting circuit has a reset signal terminal outside thereof, and a signal applied to the reset signal terminal causes:
An amplifier circuit, wherein the output signal of the circuit for detecting / holding the peak value, the output signal of the circuit 30a for detecting / holding the bottom value, and the output signal of the threshold value setting circuit have substantially the same potential.
3. The delay circuit according to claim 2, wherein a delay circuit is added between the reset signal terminals of the basic circuits which are cascade-connected to each other, and a reset signal terminal of the basic circuit of the first stage in the basic circuit is provided. An amplifier circuit characterized by using the entire reset signal terminal.
JP11648393A 1993-04-20 1993-04-20 Amplifier circuit Expired - Lifetime JP3284506B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11648393A JP3284506B2 (en) 1993-04-20 1993-04-20 Amplifier circuit

Applications Claiming Priority (8)

Application Number Priority Date Filing Date Title
JP11648393A JP3284506B2 (en) 1993-04-20 1993-04-20 Amplifier circuit
US08/227,886 US5475342A (en) 1993-04-19 1994-04-15 Amplifier for stably maintaining a constant output
EP98118027A EP0891042B1 (en) 1993-04-19 1994-04-18 Amplifier
EP19940105968 EP0621686B1 (en) 1993-04-19 1994-04-18 Amplifier
DE1994634482 DE69434482D1 (en) 1993-04-19 1994-04-18 Amplifier
DE1994620447 DE69420447T2 (en) 1993-04-19 1994-04-18 Amplifier
DE1994620447 DE69420447D1 (en) 1993-04-19 1994-04-18 Amplifier
DE1994634482 DE69434482T2 (en) 1993-04-19 1994-04-18 Amplifier

Publications (2)

Publication Number Publication Date
JPH06310967A true JPH06310967A (en) 1994-11-04
JP3284506B2 JP3284506B2 (en) 2002-05-20

Family

ID=14688235

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11648393A Expired - Lifetime JP3284506B2 (en) 1993-04-20 1993-04-20 Amplifier circuit

Country Status (1)

Country Link
JP (1) JP3284506B2 (en)

Cited By (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3924757A1 (en) * 1988-07-27 1990-02-08 Ricoh Kk Document reading device
EP0792012A3 (en) * 1996-02-23 1998-05-27 Matsushita Electric Industrial Co., Ltd. Amplifier for burst signal and optical receiving circuit
US5955921A (en) * 1996-12-11 1999-09-21 Fujitsu Limited Signal amplifier circuit
US6018407A (en) * 1996-05-20 2000-01-25 Nec Corporation Optical receiving circuit
JP2000101125A (en) * 1998-09-21 2000-04-07 Fujitsu Ltd Optical communication device and waveform forming circuit
EP1006653A2 (en) * 1998-12-02 2000-06-07 Fujitsu Limited Signal amplifying circuit
WO2000057546A1 (en) * 1999-03-19 2000-09-28 Fujitsu Limited Method of improving amplifier input offset, and amplifier
US6225835B1 (en) 1999-03-18 2001-05-01 Fujitsu Limited Amplifier free from duty-ratio error
US6271690B1 (en) 1999-03-26 2001-08-07 Matsushita Electric Industrial Co., Ltd. Discriminator
US6812787B2 (en) 2002-03-26 2004-11-02 Matsushita Electric Industrial Co., Ltd. Reference voltage generating circuit and voltage amplifier using the same
US6882944B2 (en) 2002-06-10 2005-04-19 Oki Electric Industry Co., Ltd. Threshold setting apparatus for adjustably setting a threshold for use in identifying serial data from a baseband signal
JP2005274642A (en) * 2004-03-23 2005-10-06 Sony Corp Display apparatus and driving method for same
JP2006229541A (en) * 2005-02-17 2006-08-31 Sigma-Links Inc Burst signal receiving device
JP2008141271A (en) * 2006-11-30 2008-06-19 Fujitsu Ltd Receiver
JP2008211376A (en) * 2007-02-23 2008-09-11 Eudyna Devices Inc Electronic circuit and communication system
JP2008211808A (en) * 2008-03-07 2008-09-11 Matsushita Electric Ind Co Ltd Reference voltage generation circuit and voltage amplifier using same
JP2008263563A (en) * 2007-04-16 2008-10-30 Nippon Telegr & Teleph Corp <Ntt> Amplitude limit amplifying circuit
JP2009060415A (en) * 2007-08-31 2009-03-19 Sony Corp Communication apparatus, communication method, and program
US7720394B2 (en) 2006-08-04 2010-05-18 Fujitsu Limited Optical reception circuit and identification level controlling method for the same
JP2010219651A (en) * 2009-03-13 2010-09-30 Nec Corp Optical receiver, signal reproducing method and program
JP2013030991A (en) * 2011-07-28 2013-02-07 Sumitomo Electric Ind Ltd Binarization circuit
JP2013205086A (en) * 2012-03-27 2013-10-07 Toyota Central R&D Labs Inc Bottom detection circuit

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015186013A (en) 2014-03-24 2015-10-22 住友電気工業株式会社 transimpedance amplifier

Cited By (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3924757A1 (en) * 1988-07-27 1990-02-08 Ricoh Kk Document reading device
EP0792012A3 (en) * 1996-02-23 1998-05-27 Matsushita Electric Industrial Co., Ltd. Amplifier for burst signal and optical receiving circuit
US5875049A (en) * 1996-02-23 1999-02-23 Matsushita Electric Industrial Co., Ltd. Amplifier for burst signal and optical receiving circuit
US6018407A (en) * 1996-05-20 2000-01-25 Nec Corporation Optical receiving circuit
US5955921A (en) * 1996-12-11 1999-09-21 Fujitsu Limited Signal amplifier circuit
JP2000101125A (en) * 1998-09-21 2000-04-07 Fujitsu Ltd Optical communication device and waveform forming circuit
JP4518443B2 (en) * 1998-09-21 2010-08-04 富士通セミコンダクター株式会社 Optical communication device
EP1006653A3 (en) * 1998-12-02 2004-06-30 Fujitsu Limited Signal amplifying circuit
EP1006653A2 (en) * 1998-12-02 2000-06-07 Fujitsu Limited Signal amplifying circuit
EP1746725A1 (en) * 1998-12-02 2007-01-24 Fujitsu Limited Signal amplifying circuit
US6292058B1 (en) 1998-12-02 2001-09-18 Fujitsu Limited Signal amplifying circuit connected to a transfer circuit having a known non-linear transfer characteristic
US6225835B1 (en) 1999-03-18 2001-05-01 Fujitsu Limited Amplifier free from duty-ratio error
WO2000057546A1 (en) * 1999-03-19 2000-09-28 Fujitsu Limited Method of improving amplifier input offset, and amplifier
US6271690B1 (en) 1999-03-26 2001-08-07 Matsushita Electric Industrial Co., Ltd. Discriminator
US6812787B2 (en) 2002-03-26 2004-11-02 Matsushita Electric Industrial Co., Ltd. Reference voltage generating circuit and voltage amplifier using the same
CN1303757C (en) * 2002-03-26 2007-03-07 松下电器产业株式会社 Reference voltage generating circuit and voltage amplifier adopting same
US6882944B2 (en) 2002-06-10 2005-04-19 Oki Electric Industry Co., Ltd. Threshold setting apparatus for adjustably setting a threshold for use in identifying serial data from a baseband signal
JP2005274642A (en) * 2004-03-23 2005-10-06 Sony Corp Display apparatus and driving method for same
JP2006229541A (en) * 2005-02-17 2006-08-31 Sigma-Links Inc Burst signal receiving device
US7720394B2 (en) 2006-08-04 2010-05-18 Fujitsu Limited Optical reception circuit and identification level controlling method for the same
US8064779B2 (en) 2006-11-30 2011-11-22 Fujitsu Limited Receiving apparatus
JP2008141271A (en) * 2006-11-30 2008-06-19 Fujitsu Ltd Receiver
JP2008211376A (en) * 2007-02-23 2008-09-11 Eudyna Devices Inc Electronic circuit and communication system
JP2008263563A (en) * 2007-04-16 2008-10-30 Nippon Telegr & Teleph Corp <Ntt> Amplitude limit amplifying circuit
JP2009060415A (en) * 2007-08-31 2009-03-19 Sony Corp Communication apparatus, communication method, and program
JP2008211808A (en) * 2008-03-07 2008-09-11 Matsushita Electric Ind Co Ltd Reference voltage generation circuit and voltage amplifier using same
JP2010219651A (en) * 2009-03-13 2010-09-30 Nec Corp Optical receiver, signal reproducing method and program
JP2013030991A (en) * 2011-07-28 2013-02-07 Sumitomo Electric Ind Ltd Binarization circuit
JP2013205086A (en) * 2012-03-27 2013-10-07 Toyota Central R&D Labs Inc Bottom detection circuit

Also Published As

Publication number Publication date
JP3284506B2 (en) 2002-05-20

Similar Documents

Publication Publication Date Title
JP6073401B2 (en) High linearity fast peak detector
DE10302128B3 (en) Buffer amplifier system for buffer storage of signals runs several DRAM chips in parallel and has two output buffer amplifiers in parallel feeding reference and signal networks with capacitors and DRAMs
US5818288A (en) Charge pump circuit having non-uniform stage capacitance for providing increased rise time and reduced area
US7279951B2 (en) DC offset cancellation circuit, differential amplification circuit with DC offset cancellation circuit, photo-electric pulse conversion circuit, pulse shaping circuit, and pulse generation circuit
US20140320713A1 (en) Solid-state imaging device
US6587004B2 (en) Signal amplifier and optical signal receiver using the same
US7944196B2 (en) RF detector with crest factor measurement
US6486808B1 (en) Data signal amplifier with automatically controllable dynamic signal range
EP0844736B1 (en) Waveform-Shaping circuit and a data-transmitting apparatus using such a circuit
US6765517B1 (en) Variable order sigma-delta modulator
EP1400013B1 (en) Method and apparatus for a transceiver having a constant power output
US6417728B1 (en) Switched-capacitor, fully-differential operational amplifier with high switching frequency
US6441357B2 (en) Using cascaded gain stages for high-gain and high-speed readout of pixel sensor data
US6600374B2 (en) Collective automatic gain control
US6906586B2 (en) Differential amplifier circuit used in solid-state image pickup apparatus, and arrangement that avoids influence of variations of integrated circuits in manufacture and the like
US7212041B2 (en) Weighted multi-input variable gain amplifier
JP3144398B2 (en) Variable delay circuit
KR101285218B1 (en) Duty cycle correction circuit and duty cycle correction method
TWI459769B (en) Adaptive equalizer and adaptive equalizing method
US5430765A (en) Digital data receiver having DC offset cancelling preamplifier and dual-mode transimpedance amplifier
US5345185A (en) Logarithmic amplifier gain stage
US5175452A (en) Programmable compensated digital delay circuit
US6885249B2 (en) Optical signal receiving circuit and optical signal receiving semiconductor device
JP4077813B2 (en) Peak and bottom detectors for burst mode optical receivers.
EP0381371A2 (en) A burst mode digital data receiver

Legal Events

Date Code Title Description
FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090308

Year of fee payment: 7

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090308

Year of fee payment: 7

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100308

Year of fee payment: 8

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110308

Year of fee payment: 9

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110308

Year of fee payment: 9

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120308

Year of fee payment: 10

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130308

Year of fee payment: 11

EXPY Cancellation because of completion of term