JP2008211808A - Reference voltage generation circuit and voltage amplifier using same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a voltage amplifier capable of amplifying input signals having a variety of signal amplitudes to have a certain amplitude by using a reference voltage circuit having an excellent response performance. <P>SOLUTION: In a reference voltage generation circuit 7, only a switch SW1 is turned off in a first period and a maximum peak value Vmax of an input signal In is kept at a node A of a first capacitor 1. In the next second period, switches SW2 and SW3 are released and a voltage difference of the maximum peak value V max and a minimum peak value Vmin is held at a node C of a capacitor array 4. At this time, a holding voltage of a second capacitor 2 in the capacitor array 4 is added to a holding voltage of a first capacitor 1, and a voltage of a node B is outputted as a reference voltage Vref. The input signal In is given to one input terminal of a differential amplification circuit 6, and the reference voltage Vref is given to the other input terminal. The reference voltage Vref is generated at a point of time when the holding voltages of the nodes A and C are stabilized. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  In an optical communication system such as a PDS (Passive Double Star) optical subscriber system, the present invention has various signal amplitudes such as a signal obtained by converting an output current from a photodiode receiving an optical signal from an optical fiber into a current-voltage converter. The present invention relates to a voltage amplifier that amplifies an input signal to a certain amplitude.

  In recent years, research on optical subscriber systems has been actively conducted for future FTTH (Fiber To The Home). However, the introduction of an optical fiber having a huge transmission capacity into a general household is a problem in terms of economy as compared with a conventional metal line. Under such circumstances, a PDS optical subscriber system that enables a two-way communication service to a plurality of subscribers by branching a single optical fiber from the station side is promising from the viewpoint of economy.

  In such an optical communication system, since the distance from each home to the station is different, the transmission distance by the optical fiber is also different. The amount of attenuation of light is also different, and the signal that has been photoelectrically converted by the optical link unit of the optical receiver becomes a voltage signal having various amplitudes from a minute amplitude signal to a large amplitude signal. In order to extract the clock and data from the voltage signal, it is necessary to amplify the voltage signal to a voltage signal having a constant amplitude at a level that allows digital processing.

  However, if the gain is set to a high value when the amplitude of the input signal is small when amplifying with a normal amplifier, the output is saturated when the output is saturated due to an offset or a signal with a large amplitude is input. Since the waveform is greatly distorted, the clock and data cannot be extracted.

Therefore, an amplifier circuit disclosed in Patent Document 1 has been proposed. In this amplifier circuit, the peak value and the bottom value of the input signal are detected and held, respectively, and the intermediate value of these voltages and the input signal are input to the amplitude limiting amplifier.
JP-A-6-310967

  However, the amplifier circuit proposed in Patent Document 1 requires two peak detection circuits, that is, a peak value detection holding circuit and a bottom value detection holding circuit, so that power consumption increases. Furthermore, a circuit for dividing the output voltage of these circuits is required. In order to increase the response speed of the voltage dividing circuit, it is necessary to reduce the value of the voltage dividing resistor, and further increase the power consumption. To encourage.

  Also, the time until the intermediate voltage between the peak value and the bottom value is generated and stabilized is the time until each output of the peak value detection holding circuit and the bottom value detection holding circuit is stabilized, and the output of the voltage dividing circuit There is a problem that a large time delay occurs because it is the sum of the time until the time becomes stable.

  The present invention has been made in view of the above-mentioned problems, and its object is to provide a reference voltage circuit with low power consumption and excellent high-speed response, and to input signals having various signal amplitudes using the reference voltage circuit. It is an object to provide a voltage amplifier that amplifies the amplitude.

  In order to achieve the above object, according to the present invention, when the maximum peak value and the minimum peak value of the input signal are detected, a reference voltage between these peak values is automatically generated at the same time.

That is, the reference voltage generating circuit according to the first aspect of the present invention includes a current supply means for supplying a voltage and outputting a current corresponding to the voltage from the output terminal, the first capacitor, the second capacitor, and the third capacitor. Are connected in series, one end of the first capacitor is connected to a fixed voltage, and one end of the third capacitor is connected to the output terminal of the current supply means , and A first switch that is connected to both ends of the terminal pair and is turned on / off by a signal supplied from the outside, and a first switch that is connected to and cut off by a signal supplied from the outside that is connected to both ends of the second capacitor. And a third switch connected to both ends of the third capacitor and connected and cut off by a signal applied from the outside, and the one end of the third capacitor is supplied with the current. means Connected to the first terminal, it provides a signal from the outside to the second terminal, and wherein the extracting signals from the common connection of the third capacitor and the second capacitor.

  According to a second aspect of the present invention, in the reference voltage generating circuit according to the first aspect, the first to third switches are turned on in a first period, and the first switch is turned off in a subsequent second period. In addition, the second and third switches are turned on, and the first to third switches are cut off in the subsequent third period.

  According to a third aspect of the present invention, in the reference voltage generating circuit according to the first aspect, the capacitance value of the second capacitor is equal to the capacitance value of the third capacitor.

According to a fourth aspect of the present invention, in the reference voltage generating circuit according to the first aspect, a current is conducted only in one direction to a path in which the one end of the third capacitor is connected to the output terminal of the current supply unit. A unidirectional conducting element is provided.

According to a fifth aspect of the present invention, there is provided a reference voltage generating circuit, comprising: a current supply means for applying a voltage and outputting a current corresponding to the voltage from an output terminal; a voltage generating circuit for generating a predetermined voltage; A cascade connection capacitor circuit in which two capacitors are connected, the predetermined voltage is applied to one end of the first capacitor, and one end of the second capacitor is connected to the output terminal of the current supply means ; A first switch that is connected to and cut off by a signal applied from the outside with each terminal pair connected to both ends of the capacitor; and connected to and cut off by a signal applied from the outside connected to each terminal pair at both ends of the second capacitor. A second switch for shutting off, connecting the one end of the second capacitor to the first terminal of the current supply means, applying a signal from the outside to the second terminal, Common for the second capacity Wherein the extracting signals from the connection part.

  According to a sixth aspect of the present invention, in the reference voltage generating circuit according to the fifth aspect, the capacitance values of the two capacitors constituting the capacitor string are equal to each other.

According to a seventh aspect of the present invention, in the reference voltage generating circuit according to the fifth aspect, current is conducted only in one direction to a path connecting the one end of the second capacitor to the output terminal of the current supply means. A unidirectional conducting element is provided.

  According to an eighth aspect of the present invention, there is provided a voltage amplifier according to the first aspect or the fifth aspect, wherein the reference voltage generating circuit outputs a difference between the two input voltages input to the two input terminals and outputs an output voltage corresponding to the difference voltage. An input signal is applied to one input terminal of the reference voltage generating circuit and the differential amplifier circuit, and a reference voltage output from the reference voltage generating circuit is the other of the differential amplifier circuit. It is given to an input terminal.

  A voltage amplifier according to a ninth aspect of the present invention includes the voltage amplifier according to the eighth aspect as a first voltage amplification circuit, and at least one second voltage amplification circuit, and the second voltage amplification circuit includes: A sample hold circuit and a differential amplifier circuit, and an input voltage to the second voltage amplifier circuit is applied to one input terminal of the sample hold circuit and the differential amplifier circuit, The output voltage is supplied to the other input terminal of the differential amplifier circuit.

  According to a tenth aspect of the present invention, in the voltage amplifier according to the ninth aspect, the one second voltage amplifying circuit or a plurality of second voltage amplifying circuits connected in cascade is provided at a subsequent stage of the first voltage amplifying circuit. The circuits are connected in cascade.

  The invention described in claim 11 is the voltage amplifier according to claim 8, 9 or 10, further comprising an offset correction circuit, wherein the offset correction circuit is cascade-connected to the final stage.

  According to a twelfth aspect of the present invention, in the voltage amplifier according to the eleventh aspect, the offset correction circuit includes a differential amplifier circuit having first and second differential input terminals, and first and second peak detection circuits. And the first and second signals are input, the peak value of the first input signal is detected and held by the first peak detection circuit, and the first input signal and its peak value are detected. Is input to the first differential input terminal of the differential amplifier circuit as a first differential signal, and the peak value of the second input signal is detected and held by the second peak detection circuit, The second input signal and its peak value are input as a second differential signal to the second differential input terminal of the differential amplifier circuit.

  According to a thirteenth aspect of the present invention, in the voltage amplifier according to the eleventh aspect, the offset correction circuit includes a differential amplifier circuit having first and second differential input terminals, and a first and second peak detection circuit. The first and second signals are input, and the first and second input signals are input as first differential signals to the first differential input terminal of the differential amplifier circuit. The peak values of the first and second input signals are detected and held by the first and second peak detection circuits, respectively, and the output signals of the first and second peak detection circuits are a second differential signal. A signal is input to a second differential input terminal of the differential amplifier circuit as a signal.

  According to a fourteenth aspect of the present invention, in the voltage amplifier according to the twelfth or thirteenth aspect, the first and second peak detection circuits of the offset correction circuit include peak values of the first and second input signals. A response delay circuit for delaying detection and holding of the signal is connected.

  A fifteenth aspect of the present invention is the voltage amplifier according to the eighth, ninth, tenth, or eleventh aspect, further comprising a comparator that amplifies the differential voltage input to the comparator to a voltage having a constant amplitude. In addition, the output voltage value can be fixed by receiving a control signal.

  The invention described in claim 16 is the voltage amplifier according to claim 8, 9, 10, 12 or 13, wherein the output of the differential amplifier circuit is limited in amplitude.

  According to a seventeenth aspect of the present invention, in the voltage amplifier according to the ninth or tenth aspect, a delay circuit is provided, and the delay circuit includes a reset signal to a reference voltage generating circuit of the first voltage amplifying circuit, and the second A time delay is given to the control signal of the sample hold circuit of the voltage amplifier circuit.

  According to an eighteenth aspect of the present invention, in the voltage amplifier according to the twelfth or thirteenth aspect, a delay circuit is provided, and the delay circuit includes control signals for the first and second sample and hold circuits of the second voltage amplifier circuit. A time delay is given to the reset signals of the first and second peak detection circuits of the offset correction circuit.

  According to a nineteenth aspect of the present invention, in the voltage amplifier according to the fifteenth aspect, a delay circuit is provided, and the delay circuit controls the reset signals of the first and second peak detection circuits of the offset correction circuit and the control of the comparator. A time delay is given to the signal.

  As described above, in the first to fourth aspects of the present invention, the reference voltage is automatically generated when the output of the reference voltage generating circuit is set. Compared to the configuration in which the voltage is divided by the voltage divider and the reference voltage is generated, the reference voltage can be generated at high speed. In addition, since the peak detection circuit has only one scale, the power consumption can be reduced.

  In particular, in the invention described in claim 2, the first and second peak values are provided by the configuration having three capacitors of the first, second and third, and switching which of these capacitors holds the voltage. The reference voltage is easily generated with a simple configuration.

  According to the third aspect of the present invention, since the capacitance values of the second capacitor and the third capacitor are equal to each other, an intermediate voltage between the first peak value and the second peak value is generated as the reference voltage. Become.

  According to the fifth to seventh aspects of the present invention, when the input signal has a constant value in the first period, the constant voltage can be generated by the voltage generating circuit. And a reset signal for charge discharge of this capacitor is not required, and a reference voltage can be generated at a high speed and with low power consumption with a simpler configuration.

  In particular, in the invention of claim 6, since the capacitance values are set to be equal between the second capacitor and the third capacitor, an intermediate voltage between the output voltage of the voltage generation circuit and the peak held voltage is used as the reference voltage. Generated.

  In the invention according to claim 8, since the input signal and the reference voltage which is the center voltage of the amplitude of the input signal are given to the two input terminals of the differential amplifier circuit, the input signal is amplified with low distortion. Will be.

  According to the ninth aspect of the present invention, in the second voltage amplifier circuit, the voltage before the signal input is held as the reference voltage in the sample hold circuit, so that the subsequent input signal is amplified with low distortion in the differential amplifier circuit. .

  In the invention described in claim 10, since one second voltage amplifier circuit or a plurality of second voltage amplifier circuits connected in cascade are further connected in the subsequent stage of the first voltage amplifier circuit, the input signal is Amplified with low power consumption and high gain.

  According to the eleventh aspect of the present invention, since the offset correction circuit is cascaded in the final stage of the voltage amplifier, the offset can be effectively deleted, and the duty deterioration due to the offset can be suppressed to a small level.

  In the inventions according to the twelfth and thirteenth aspects, the offset can be easily corrected with a simple configuration.

  In the invention described in claim 14, since a response delay circuit is added to the peak detection circuit of the offset correction circuit, even if there is an abnormal peak rise in the first bit, this peak abnormality is not detected and is normal A simple peak value can be detected.

  In the invention according to claim 15, since the input differential voltage is amplified to a voltage having a constant amplitude by the comparator, a digital output signal having a logic level amplitude can be obtained, and the fluctuation of the output signal due to noise or the like can be obtained. Variations can be suppressed.

  According to the sixteenth aspect of the present invention, since the output of the differential amplifier circuit is limited in amplitude, it is not saturated even with an input signal having a large amplitude, and an output with little duty deterioration can be obtained.

  In the seventeenth to nineteenth aspects of the present invention, the reset operation is performed first by the reference voltage generation circuit of the first voltage amplification circuit in the previous stage, the sample hold circuit of the second voltage amplification circuit, and then the offset correction circuit. Since the operation is performed in the order of the peak detection circuit and then the comparator, a stable operation is realized, and a highly accurate output can be obtained.

  As described above, according to the first to fourth aspects of the present invention, since the reference voltage is automatically generated when the output of the reference voltage generating circuit is set, it is possible to generate the reference voltage at high speed. In addition, since only one peak detection circuit is required, power consumption can be reduced.

  In particular, according to the second aspect of the present invention, the first and second peak values and the reference voltage are generated by the switching configuration of the three capacitors and which of these capacitors holds the voltage. The reference voltage can be easily generated with a simple configuration.

  According to the third aspect of the present invention, an intermediate voltage between the first peak value and the second peak value can be generated as the reference voltage.

  According to the fifth to seventh aspects of the invention, the reference voltage can be generated at a high speed and with low power consumption with a simpler configuration than that of the first aspect of the invention.

  In particular, according to the sixth aspect of the present invention, it is possible to generate a voltage that is exactly intermediate between the output voltage of the voltage generation circuit and the peak-held voltage as the reference voltage.

  According to the invention described in claim 8, since the input signal and the reference voltage which is the center voltage of the amplitude of the input signal are given to the two input terminals of the differential amplifier circuit, the input signal is amplified with low distortion. Is possible.

  According to the ninth aspect of the invention, since the voltage before the signal input is held as the reference voltage in the sample hold circuit of the second voltage amplifier circuit, the subsequent input signal can be amplified with low distortion.

  According to the tenth aspect of the present invention, since one or more second voltage amplification circuits are further connected in cascade after the first voltage amplification circuit, the input signal can be amplified with low power consumption and high gain.

  According to the eleventh aspect of the present invention, since the offset correction circuit is cascade-connected to the final stage of the voltage amplifier, the offset can be effectively deleted and the duty deterioration due to the offset can be suppressed small.

  According to the twelfth and thirteenth aspects of the invention, the offset can be easily corrected with a simple configuration.

  According to the fourteenth aspect of the present invention, since the response delay circuit is added to the peak detection circuit of the offset correction circuit, it is possible to detect a normal peak value without detecting the peak abnormality of the first bit.

  According to the fifteenth aspect of the present invention, a digital output signal having a logic level amplitude can be obtained by the comparator, and fluctuations and fluctuations of the output signal due to noise or the like can be suppressed.

  According to the sixteenth aspect of the present invention, since the amplitude of the output of the differential amplifier circuit is limited, saturation with respect to an input signal having a large amplitude can be prevented, and an output with less duty deterioration can be obtained.

  According to the seventeenth to nineteenth aspects of the present invention, the reset operation is sequentially performed from the circuit located in the preceding stage, so that a stable operation can be realized and a highly accurate output can be obtained.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 shows a reference voltage generation circuit according to the first embodiment of the present invention.

  In the figure, one end of a capacitor 1 is grounded (here, it is assumed that the voltage is a predetermined voltage VDD and works as a minimum hold circuit), and the other end is cascade-connected to a capacitor string 4 consisting of cascade connections of capacitors 2 and 3. Has been. Switches SW1, SW2, and SW3 are connected in parallel to the capacitors 1, 2, and 3, respectively. These switches SW1 to SW3 work to short-circuit both ends of each of the capacitors 1 to 3 to extract charges. The VIC is a voltage-current conversion circuit, and an input voltage signal Vin is input to the input side thereof, and a circuit in which the capacitor 1 and the capacitor string 4 are connected in cascade is connected to the output side thereof. And the capacitors 1 to 3 are charged (or discharged) until the output voltage becomes equal.

  The detailed operation of the reference voltage generating circuit of FIG. 1 will be described below with reference to FIG. In the following description, as shown in FIG. 1, the connection point of the capacitors 1 and 2 is the node A, the connection point of the capacitors 2 and 3 is the node B, and the connection point of the capacitor 3 and the voltage-current conversion circuit VIC is the node. This will be described as C.

  (1) Reset period T1: During this period, all the switches SW1 to SW3 are turned on, and the charges of all the capacitors 1 to 3 are discharged. Thereby, all of the node A, the node B, and the node C are fixed to the potential VDD.

  (2) First period T2: During this period, only the switch SW1 is turned OFF, and the capacitor 1 functions as a hold capacitor. As a result, the voltage (first peak value) Vmax on the high potential side of the input signal Vin is held in the capacitor 1, that is, the node A. Since the switches SW2 and SW3 remain ON, the nodes A, B, and C are all at the high potential side voltage Vmax.

  (3) Second period T3: During this period following the first period T2, the switches SW2 and SW3 are also opened, and the cascade connection of the capacitors 1, 2, and 3 serves as a hold capacitor. When the input signal Vin swings to the low potential side during this period, the peak value (second peak value) Vmin is held at the node C, and the capacitance string 4 has a difference voltage (Vmax−) between the two peak values Vmax and Vmin. Vmin) is maintained.

  At this time, the potential of the reference voltage Vref generated at the node B is considered. First, in the first period T2, the output voltage Vmax at the time of no input signal is detected, and this voltage Vmax is held in the capacitor 1. At this time, the capacitors 2 and 3 are discharged. Therefore, when the capacitance values of the capacitors 1, 2, and 3 are C1, C2, and C3, the held voltages are V1, V2, and V3, and the stored charge amounts are Q1, Q2, and Q3, the following equation is established.

Q1 = C1 · V1 = C1 · Vmax
Q2 = C2 · V2 = 0
Q3 = C3 · V3 = 0
Next, in the second period T3, the output voltage Vmin at the time of the maximum input signal is sampled and held under the serial connection state of the capacitors 1 to 3. At this time, when the mobile charge is represented by q, the following equation is established.

(Q1 + q) / C1 + q / C2 + q / C3 = Vmin
Ｑ q = (Vmin-Q1 / C1) · C4
where 1 / C4 = (1 / C1 + 1 / C2 + 1 / C3)
Therefore, the reference voltage Vref is as follows.

Vref = Vmin- (C4 / C3) (Vmin-Vmax)
Here, if C2 = C3 and C1 = K · C2 (k is a natural number),
Vref = Vmin− (1 / (2 + 1 / K)) (Vmin−Vmax)
= (Vmin + Vmax) / 2 + (1 / 4K) (Vmin-Vmax)
= (Vmin + Vmax) / 2 + ΔV
where ΔV = (1 / 4K) (Vmin−Vmax)
It becomes. From the above equation, by setting K >> 1, the voltage obtained by adding the holding voltage ((Vmax−Vmin) / 2) of the capacitor 2 to the holding voltage Vmax on the high potential side as the reference voltage Vref, that is, two peaks It can be seen that an intermediate voltage (Vmin + Vmax) / 2 between the values Vmin and Vmax is obtained.

  As described above, in this embodiment, the reference voltage Vref is automatically generated when the output of the reference voltage generation circuit is set, so that the peak detected voltage as in the conventional case is used as the voltage of the next stage. The reference voltage Vref can be generated at a higher speed than the configuration in which the voltage is divided by the voltage divider and the reference voltage is generated. In addition, since the peak detection circuit needs only one scale, it is effective to reduce power consumption.

(Second embodiment)
FIG. 2 shows a reference voltage generating circuit according to the second embodiment of the present invention.

  The reference voltage generation circuit in FIG. 2 includes the capacitor 1, the capacitor 2, and the capacitor string 4 formed by cascading the capacitors 3 and the voltage-current conversion circuit C shown in FIG. Further, m5 is a cascode transistor as a unidirectional conducting element that allows current to flow only in one direction, m6 is an NMOS source follower transistor as a buffer circuit, and m8 is a PMOS transistor as a first reset circuit connected in parallel to the capacitor 1. , M9 and m10 are PMOS transistors as second reset circuits connected in parallel to the capacitors 2 and 3, respectively.

  The voltage-current conversion circuit C includes a PMOS transistor pair m1, m2 biased by a bias current source Io and coupled at its source, and a current mirror circuit composed of NMOS transistors m3, m4. The two PMOS transistors m1 , M2 gate terminals are two input terminals. The output terminal out of the voltage-current conversion circuit C is connected to one end of a cascode transistor m5, and the other end of the cascode transistor m5 is connected to one end of the capacitor string 4 and a gate which is an input terminal of the NMOS source follower transistor m6. Has been. The other end of the capacitor string 4 and the capacitor 1 are connected at a node A, and the other end of the capacitor 1 is given a predetermined voltage VDD.

  Further, the source which is the output terminal of the NMOS source follower transistor m6 is connected to one input terminal of the voltage / current converter circuit C (that is, the gate of the PMOS transistor m2). The input signal Vin is input to the gate of the PMOS transistor m1 which is the input terminal of the input terminal. The PMOS transistor m8 as the first reset circuit discharges the charge of the capacitor 1, and the PMOS transistors m9 and m10 as the second reset circuit discharge the charge of the capacitors 2 and 3. The voltage at the node B, which is the connection point between the capacitors 2 and 3 in the capacitor string 4, is taken out as a reference voltage Vref through the NMOS source follower transistor M7.

  The reference voltage generation circuit according to the present embodiment operates as follows. First, in the first reset period, all of the reset signals SW1, SW2, and SW3 are LOW, the charges of the capacitors 1, 2, and 3 are all discharged, and the nodes A, B, and C are set to the voltage VDD. . Next, in the first period, the reset signal SW1 becomes HIGH, and the capacitor 1 is charged until the gate voltages of the two PMOS transistors m1 and m2 of the voltage-current conversion circuit C become equal to each other. The maximum value Vmax in the period is detected and held. Next, in the second period, the reset signals SW2 and SW3 are also HIGH, and the node C detects and holds the minimum value Vmin of the input signal Vin in the second period. At this time, the voltage of the node B is stable, and a reference voltage Vref (= (Vmax + Vmin) / 2) corresponding to the voltage of the node B is taken out.

  Thus, in the present embodiment, the intermediate voltage of the signal amplitude of the input signal Vin is generated very easily as the reference voltage Vref. In addition, this circuit configuration does not require a voltage divider by resistance voltage division as in the prior art, so that the reference voltage Vref can be generated at high speed and with low power consumption.

  Although the present embodiment is configured based on the minimum hold circuit, the present invention is not limited to this configuration, and includes a configuration using a circuit based on the maximum hold circuit. In this case, the power supply voltage VDD and the ground VSS may be reversed by switching the polarities of all the transistors.

(Third embodiment)
FIG. 3 shows a reference voltage generating circuit according to the third embodiment of the present invention. In the present embodiment, a voltage generation circuit 5 is provided, and the voltage generation circuit 5 is configured to substitute the capacitor 1 and the switch SW1 of the first embodiment.

  That is, in the reference voltage generating circuit of the figure, a capacitor string 4 comprising two capacitors 2 and 3 connected in cascade, two switches SW2 and SW3 connected in parallel with the capacitors 2 and 3, and a voltage-current converter circuit VIC. In addition, a voltage generation circuit 5 that generates a predetermined voltage is prepared. An output terminal of the voltage generation circuit 5 is given to one end of one capacitor 2 of the capacitor row 4. The voltage at the connection node B of the two capacitors 2 and 3 in the capacitor row 4 is output as the reference voltage Vref. Also in the present embodiment, as in the first embodiment, the capacitance values of the two capacitors 2 and 3 constituting the capacitor row 4 are set to be equal to each other.

  The reference voltage generation circuit of this embodiment is effective when the input signal Vin is a constant value in the first period, and the constant voltage is generated by the voltage generation circuit 5 and is always applied to one end of the capacitor 2. . As a result, the capacitor 1 and the reset signal for the capacitor 1 are not required, and the same effect can be obtained with a simpler configuration. Further, since the capacitance values of the two capacitors 2 and 3 constituting the capacitor row 4 are set to be equal to each other, a voltage just between the output voltage of the voltage generation circuit 5 and the voltage detected and held at the peak is the reference voltage. It will be generated as Vref.

  The reference voltage generation circuit of the present embodiment can also be applied to FIG. 2, similarly to the configuration shown in FIG. That is, in FIG. 2, the capacitor 1, the reset transistor m8, and the reset signal SW1 may be removed, and the output voltage of the voltage generation circuit 5 may be applied to the node A.

(Fourth embodiment)
FIG. 4 shows an inventive voltage amplifier according to a fourth embodiment of the present invention.

  The voltage amplifier shown in FIG. 1 includes a first voltage amplifier circuit 8. The first voltage amplifier circuit 8 includes a reference voltage generation circuit 7 having the same circuit configuration as that shown in FIG. 1 and a differential amplifier circuit 6. The input signal In is input to one input terminal of the differential amplifier circuit 6 and the input terminal of the reference voltage generation circuit 7 (that is, the voltage / current conversion circuit VIC). The reference voltage Vref from the reference voltage generation circuit 7 is applied to the other input terminal of the differential amplifier circuit 6.

  With the above-described configuration, the input signal In and the center voltage (reference voltage Vref) of the amplitude of the input signal In are given to the two input terminals of the differential amplifier circuit 6. Can be amplified by distortion. In addition, since one peak detection circuit and a voltage dividing circuit are reduced as compared with the conventional configuration, low power consumption and high-speed operation are possible.

  In the present embodiment, the reference voltage generating circuit 7 has the circuit configuration shown in FIG. 1, but it is needless to say that the circuit configuration shown in FIG. 3 may be used.

(Fifth embodiment)
FIG. 5 shows an inventive voltage amplifier according to a fifth embodiment of the present invention.

  The voltage amplifier 9 shown in the figure includes the first voltage amplifier circuit 8 shown in FIG. 4 and two second voltage amplifier circuits 11 and 11 connected in cascade. Each of the second voltage amplifying circuits 11 and 11 includes a sample and hold circuit 10 and a differential amplifying circuit 6. An input signal to each second voltage amplifier circuit 11 is supplied to one input terminal of the differential amplifier circuit 6 and the sample hold circuit 10, and an output of the sample hold circuit 10 is supplied to the differential amplifier circuit 6. It is given to the other input terminal.

  Here, the output voltage of the first voltage amplifier circuit 8 is considered. When an input signal whose waveform is shown as the input signal In in FIG. 4 is input, the output voltage Vref of the reference voltage generation circuit 7 is accurately shifted by a voltage that is ½ of the amplitude of the input signal In. The output signal of the voltage amplifying circuit 8 has a waveform as shown in the output signal Out of FIG. That is, the voltage before signal input becomes the amplitude center at the time of signal input. Utilizing this property, the second voltage amplifier circuit 11 samples and holds the voltage by the sample and hold circuit 10 before the signal is input, and uses the voltage as a reference voltage Vref for the differential amplifier circuit 6. I use it.

  In FIG. 5, the differential amplifier circuit 6 has a single configuration having one differential input terminal. However, as shown in FIG. 6, the differential amplifier circuit has two differential inputs. 12 can be configured in a differential manner, and noise resistance and voltage gain can be improved.

  In the present embodiment, two second voltage amplification circuits 11 are connected in cascade, but three or more second voltage amplification circuits 11 are connected in cascade, or one second voltage amplification circuit is connected. 11 may be provided.

(Sixth embodiment)
FIG. 7 shows a voltage amplifier according to a sixth embodiment of the present invention. The feature point of this embodiment is a configuration in which an offset correction circuit is provided in the final stage.

  That is, the input signal is amplified to some extent by the first voltage amplification circuit 8 and the second voltage amplification circuit 11 constituting the voltage amplifier 9 of FIG. Since it exists between differential input signals, if this signal is used as it is and amplified to the logic level at once, duty deterioration may occur as shown in FIG. Therefore, in the present embodiment, as shown in FIG. 7, a configuration in which the offset correction circuit 14 is cascade-connected to the final stage, which is the subsequent stage of the second voltage amplification circuit 11, is employed.

  The offset correction circuit 14 includes a differential amplifier circuit 12 having first and second differential input terminals, and first and second peak detection circuits 13a and 13b. As shown in FIG. 7, the differential signal of the differential amplifier circuit 12 of the second voltage amplifier circuit 11 is input to the offset correction circuit 14, and one signal (first signal) constituting this differential input signal. And the peak value of the first signal detected and held by inputting the first signal to the first peak detection circuit 13a is one of the differential amplifier circuits 12 (the first differential signal). 1) is input to the non-inverting input terminal and the inverting input terminal of the differential input terminal. Similarly, the other signal (second signal) from the differential amplifier circuit 12 of the second voltage amplifier circuit 11 and the second signal are input to the second peak detection circuit 13b and detected and held. The peak value of the second signal is input as a second differential signal to the non-inverting input terminal and the inverting input terminal of the other (second) differential input terminal of the differential amplifier circuit 12.

  Therefore, in the present embodiment, with the above configuration, the offset can be effectively deleted and the duty deterioration can be suppressed.

  In the present embodiment, a configuration in which the offset correction circuit 14 is further arranged in the configuration in which one second voltage amplification circuit 11 is connected in cascade after the first voltage amplification circuit 8 is employed. Needless to say, the present invention may be applied to a configuration including two or more voltage amplification circuits 11 or to a configuration including only the first voltage amplification circuit 8 without including the second voltage amplification circuit.

(Seventh embodiment)
FIG. 8 shows an inventive voltage amplifier according to a seventh embodiment of the present invention.

  In the present embodiment, as in the sixth embodiment shown in FIG. 7, the offset correction circuit 14 is arranged at the final stage, but the two peak detection circuits 13 a included in the offset correction circuit 14, The arrangement position of 13b is changed to a position different from that in FIG.

  That is, in FIG. 8, the differential signal of the differential amplifier circuit 12 of the second voltage amplifier circuit 11 is converted into one differential input terminal (first differential input terminal) of the differential amplifier circuit 12 of the offset correction circuit 14. ) As it is as a first differential signal and also input to the first and second peak detection circuits 13a and 13b to detect and hold the respective peak values. The other differential input terminal (second differential input terminal) of 12 is input as a second differential signal.

  Therefore, also in this embodiment, the offset can be easily canceled by the above configuration, similarly to the sixth embodiment.

  The outputs of the differential amplifier circuit 6 of the first voltage amplifier circuit 8, the differential amplifier circuit 12 of the second voltage amplifier circuit 11, and the differential amplifier circuit 12 of the offset correction circuit 14 are limited in amplitude. ing. Accordingly, since saturation with respect to an input signal having a large amplitude can be prevented, an output with little duty deterioration can be obtained. The amplitude limitation may be applied to the differential amplifier circuits 6 and 12 shown in FIGS.

(Eighth embodiment)
FIG. 9 shows an inventive voltage amplifier according to an eighth embodiment of the present invention.

  In order for the offset correction circuit 14 in the sixth and seventh embodiments to operate normally, the peak values of the two input signals must be accurately detected and held, but the actual waveforms are shown in FIG. As indicated by symbol A in FIG. 13, the peak value of the first bit is larger than the peak value when it is normal. This is because the peak value of the first bit increases in the amplifier circuit up to the previous stage because of a time delay until the reference voltage Vref is generated. In this case, since the offset is not normally canceled, if the signal is used as it is and is converted to the logic level at once by a comparator or the like, there is a case where a large duty deterioration occurs.

  Therefore, in this embodiment, the response delay circuit 15 is arranged so as to eliminate the influence of the abnormal peak value of the first bit. The response delay circuit 15 monitors an input differential signal from the differential amplifier circuit 12 of the second voltage amplifier circuit 11 to the offset correction circuit 14, and the two peak detection circuits 13a and 13b of the offset correction circuit 14 The function of delaying the detection and holding operations of these peak detection circuits 13a and 13b is achieved so that the peak value is detected and held in the second bit and thereafter of the input signal.

  Therefore, in the present embodiment, even when an abnormal peak rises in the first bit, the response delay circuit 15 detects a normal peak value after the second bit as shown by symbol B in FIG. Is possible.

(Ninth embodiment)
FIG. 10 shows an inventive voltage amplifier according to a ninth embodiment of the present invention. The feature of this embodiment is that the comparator 16 is arranged at the last stage.

  In the present embodiment, the output signal of the differential amplifier circuit 12 of the offset correction circuit 14 is an analog signal and the amplitude thereof is not constant. However, the comparator 16 disposed in the subsequent stage includes the offset correction circuit 14. The differential voltage of the differential amplifier circuit 12 is amplified and converted into a digital signal having an amplitude of a constant logic level and output from the output terminals Out and Outb.

  Further, the comparator 16 is configured to receive a control signal and to fix the output voltage value from the output terminals Out and Outb by this control signal. In this configuration, it is possible to prevent the output signals from the output terminals Out and Outb from amplifying in the reset period or the like.

(Tenth embodiment)
FIG. 11 shows an inventive voltage amplifier according to a tenth embodiment of the present invention.

  In the figure, the reset signal is input to the reference voltage generation circuit 7 of the first voltage amplification circuit 8, and this reset signal is delayed by a set time by the delay circuit 17a, and then the reset signal is converted to the second voltage amplification. A control signal is input to the sample hold circuit 10 of the circuit 11. Further, the reset signal delayed by the delay circuit 17a is further delayed by a set time by another delay circuit 17b, and then input to the first and second peak detection circuits 13a and 13b of the offset correction circuit 14. The signal is further delayed by a set time by a delay circuit 17c arranged at the subsequent stage of the delay circuit 17b and then input to the comparator 16 as a control signal.

  Therefore, in this embodiment, after the reset operation of the previous stage is completely completed, the subsequent stage can be reset, so that a stable operation can be realized.

  In the present embodiment, the example applied to the voltage amplifier shown in FIG. 10 is shown, but it is needless to say that the present invention may be applied to the voltage amplifier shown in FIGS. .

It is a figure which shows the reference voltage generation circuit of the 1st Embodiment of this invention. It is a figure which shows the reference voltage generation circuit of the 2nd Embodiment of this invention. It is a figure which shows the reference voltage generation circuit of the 3rd Embodiment of this invention. It is a figure which shows the voltage amplifier of the 4th Embodiment of this invention. It is a figure which shows the voltage amplifier of the 5th Embodiment of this invention. It is a figure which shows the modification of the same voltage amplifier. It is a figure which shows the voltage amplifier of the 6th Embodiment of this invention. It is a figure which shows the voltage amplifier of the 7th Embodiment of this invention. It is a figure which shows the voltage amplifier of the 8th Embodiment of this invention. It is a figure which shows the voltage amplifier of the 9th Embodiment of this invention. It is a figure which shows the voltage amplifier of the 10th Embodiment of this invention. It is a figure explaining operation | movement of the reference voltage generation circuit of the 1st Embodiment of this invention. It is a figure which shows the malfunctioning by the peak abnormality of the head bit of an input signal. It is a figure which shows the effect based on the operation | movement of the response delay circuit of the voltage amplifier of the 8th Embodiment of this invention.

Explanation of symbols

1 Capacitor 2 Capacitor 3 Capacitor 4 Capacitor string A, B, C Node C Voltage-current conversion circuit m5 Cascode transistor (unidirectional conducting element)
m6 source follower transistor (buffer circuit)
m8 PMOS transistor (first reset circuit)
m9, m10 PMOS transistors (second reset circuit)
DESCRIPTION OF SYMBOLS 5 Voltage generator circuit 6 Differential amplifier circuit 7 Reference voltage generator circuit 8 1st voltage amplifier circuit 9 Voltage amplifier 10 Sample hold circuit 11 2nd voltage amplifier circuit 12 Differential amplifier circuit 13a 2nd with two differential input terminals 1 peak detection circuit 13b second peak detection circuit 14 offset correction circuit 15 response delay circuit 16 comparator 17a, 17b, 17c delay circuit

Claims (19)

A voltage-current conversion circuit in which a current corresponding to a voltage difference applied between the first and second terminals is output from the output terminal;
A first capacitor, a second capacitor, and a third capacitor are sequentially connected, one end of the first capacitor is connected to a fixed voltage, and one end of the third capacitor is connected to the output terminal of the voltage-current conversion circuit. A cascade connection capacitance circuit connected to
A first switch that is connected to and cut off by a signal applied from the outside by connecting each terminal pair to both ends of the first capacitor;
A second switch in which each of the terminal pair is connected to both ends of the second capacitor and is turned on and off by a signal applied from the outside;
Each of the terminal pair is connected to both ends of the third capacitor, and a third switch is connected and cut off by a signal given from the outside,
The one end of the third capacitor is connected to the first terminal of the voltage-current converter circuit, a signal is externally applied to the second terminal, and the second capacitor and the third capacitor are connected in common. A reference voltage generation circuit characterized in that a signal is taken out from the section. The first to third switches are turned on in a first period, the first switch is turned off in a subsequent second period, and the second and third switches are turned on, and in a subsequent third period. The reference voltage generation circuit according to claim 1, wherein the first to third switches are cut off. The reference voltage generation circuit according to claim 1, wherein a capacitance value of the second capacitor is equal to a capacitance value of the third capacitor. The reference according to claim 1, further comprising a unidirectional conducting element that conducts current only in one direction in a path connecting the one end of the third capacitor to the output terminal of the voltage-current converter. Voltage generation circuit. A voltage-current conversion circuit in which a current corresponding to a voltage difference applied between the first and second terminals is output from the output terminal;
A voltage generation circuit for generating a predetermined voltage;
A cascade connection in which a first capacitor and a second capacitor are connected, the predetermined voltage is applied to one end of the first capacitor, and one end of the second capacitor is connected to the output terminal of the voltage-current converter circuit A capacitive circuit;
A first switch that is connected to and cut off by a signal applied from the outside by connecting each terminal pair to both ends of the first capacitor;
Each of the terminal pair is connected to both ends of the second capacitor and includes a second switch that is turned on / off by a signal applied from the outside,
The one end of the second capacitor is connected to the first terminal of the voltage-current conversion circuit, a signal is externally applied to the second terminal, and the first capacitor and the second capacitor are connected in common. A reference voltage generation circuit characterized in that a signal is taken out from the section. The reference voltage generation circuit according to claim 5, wherein the capacitance values of the two capacitors constituting the capacitor string are equal to each other. The reference according to claim 5, further comprising a unidirectional conducting element that conducts current only in one direction in a path connecting the one end of the second capacitor to the output terminal of the voltage-current converter circuit. Voltage generation circuit. A reference voltage generation circuit according to claim 1 or 5,
A differential amplifier circuit that outputs an output voltage corresponding to a difference voltage between two input voltages input to two input terminals;
An input signal is provided to one input terminal of the reference voltage generation circuit and the differential amplifier circuit,
A voltage amplifier characterized in that the reference voltage output from the reference voltage generation circuit is applied to the other input terminal of the differential amplifier circuit. The voltage amplifier according to claim 8 as a first voltage amplification circuit;
At least one second voltage amplification circuit;
The second voltage amplifier circuit includes a sample hold circuit and a differential amplifier circuit,
The input voltage to the second voltage amplifier circuit is supplied to one input terminal of the sample hold circuit and the differential amplifier circuit,
An output voltage of the sample and hold circuit is supplied to the other input terminal of the differential amplifier circuit. 10. The voltage according to claim 9, wherein the one second voltage amplifying circuit or a plurality of second voltage amplifying circuits connected in cascade is connected in cascade after the first voltage amplifying circuit. 11. amplifier. Further comprising an offset correction circuit;
The voltage amplifier according to claim 8, 9 or 10, wherein the offset correction circuit is cascade-connected to a final stage. The offset correction circuit is
A differential amplifier circuit having first and second differential input terminals;
And first and second peak detection circuits,
First and second signals are input;
A peak value of the first input signal is detected and held by the first peak detection circuit, and the first input signal and its peak value are used as a first differential signal in the first of the differential amplifier circuit. Input to the differential input terminal,
The peak value of the second input signal is detected and held by the second peak detection circuit, and the second input signal and its peak value are used as a second differential signal in the second of the differential amplifier circuit. The voltage amplifier according to claim 11, wherein the voltage amplifier is input to a differential input terminal. The offset correction circuit is
A differential amplifier circuit having first and second differential input terminals;
And first and second peak detection circuits,
First and second signals are input;
The first and second input signals are input to a first differential input terminal of the differential amplifier circuit as a first differential signal;
Peak values of the first and second input signals are detected and held by the first and second peak detection circuits, respectively, and an output signal of the first and second peak detection circuits is a second differential signal. The voltage amplifier according to claim 11, wherein the voltage amplifier is input to a second differential input terminal of the differential amplifier circuit. The first and second peak detection circuits of the offset correction circuit include
14. The voltage amplifier according to claim 12, further comprising a response delay circuit that delays detection and holding of peak values of the first and second input signals. Further comprising a comparator;
The said comparator is comprised so that it can amplify the differential voltage input into this comparator to the voltage of fixed amplitude, and can fix the output voltage value in response to a control signal. The voltage amplifier according to 9, 10, or 11. The voltage amplifier according to claim 8, 9, 10, 12 or 13, wherein the output of the differential amplifier circuit is limited in amplitude. With a delay circuit,
The delay circuit is
The time delay is given between the reset signal to the reference voltage generation circuit of the first voltage amplification circuit and the control signal of the sample hold circuit of the second voltage amplification circuit. The voltage amplifier described. With a delay circuit,
The delay circuit is
A time delay is provided between the control signals of the first and second sample and hold circuits of the second voltage amplification circuit and the reset signals of the first and second peak detection circuits of the offset correction circuit. The voltage amplifier according to claim 12 or 13. With a delay circuit,
The delay circuit is
The voltage amplifier according to claim 15, wherein a time delay is provided between a reset signal of the first and second peak detection circuits of the offset correction circuit and a control signal of the comparator.

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