JP2005274642A - Display apparatus and driving method for same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that when a level converting circuit is incorporated in a display panel and a power voltage of the level converting circuit is used as the power voltage of the display panel, the level converting circuit itself must be changed every time an amplitude of an entered driving signal is changed. <P>SOLUTION: While the power voltage VCC2 of a driving IC 16 is applied to the display panel 15 by a power line 31, on the basis of the power voltage VCC2 given from the driving IC 16 in the level converting circuits 141 to 144, a decision reference voltage Vref which is a reference for deciding a logic level (H level or L level) of a vertical start pulse VST, a vertical clock pulse VCK, a horizontal start pulse HST and a horizontal clock pulse HCK is generated. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a display device and a display device driving method, and more particularly to a display device in which pixels including electro-optic elements are two-dimensionally arranged in a matrix and a method for driving the display device.

  In a display device in which pixels including electro-optical elements are two-dimensionally arranged in a matrix, for example, a liquid crystal display device using a liquid crystal cell as an electro-optical element of a pixel, a display panel in which pixels are arranged in a matrix is driven from the outside In recent years, the drive IC has been lowered in accordance with the reduction of the design rule. Specifically, the power supply voltage drops to 5 [V], 3.3 [V], 2.5 [V], and further 1.8 [V], and low voltage drive ICs are often used. ing. On the other hand, in a liquid crystal display device, since a contrast is obtained by applying a voltage of about ± 5 [V] to the liquid crystal, when a drive signal from an external drive IC is used in the display panel, the display panel In general, the voltage is boosted to a power supply voltage of 10 [V] or more.

  As one method of boosting the drive signal to the power supply voltage in the display panel, a level conversion circuit is mounted in the external drive IC, and display is performed using the drive signal boosted to the power supply voltage in the display panel on the drive IC side. There is a way to drive the panel. In particular, the external driver IC includes a sample driver IC that drives a video signal line that determines the contrast of the display device, and a level conversion circuit is mounted in the sample driver IC. Thus, when the method of boosting the drive signal in the sample driver IC is employed, there are the following problems.

1. Since the sample driver IC obtains the contrast of the liquid crystal using a very small voltage difference, if a level conversion circuit (boost circuit) is mounted in the same IC, the level conversion circuit becomes a noise source, and it is difficult to control a minute voltage. Become.
2. Although the sample driver IC is made of a silicon substrate, a large through current flows when boosting because the voltage handled by the level conversion circuit is large.
3. The drive signal line for transmitting the drive signal from the sample driver IC to the display panel is wired together with the video signal line. However, since the drive signal has already been boosted, noise due to capacitive coupling of the drive signal is directly imaged. Since it is easy to get on the signal line, it is necessary to increase the wiring distance between the drive signal line and the video signal line or to insert a shield line.
4). When the level conversion circuit is mounted in the sample driver IC, the area of the IC increases and the cost increases.

  In order to solve such problems, conventionally, a level conversion circuit is mounted in a display panel, and a drive signal having a low voltage amplitude provided from a drive IC is converted into a drive signal having a power supply voltage amplitude used in the display panel. The voltage is increased (see, for example, Patent Documents 1 and 2). Thus, by boosting the drive signal in the display panel, the voltage amplitude of 5 [V] or less is the same as the output level of the external drive IC up to the input stage of the display panel. Low current consumption. Therefore, by mounting the level conversion circuit in the display panel, it is possible to solve the problems described above when the level conversion circuit is mounted in the sample driver IC.

JP-A-11-143435 JP-A-11-242204

  However, since the circuit in the display panel is often formed of polysilicon, when mounting the level conversion circuit in the display panel, the circuit must be formed with a transistor having low electron mobility and low driving ability. There is a restriction that it must be done. When a level conversion circuit is provided in the display panel, it is necessary to determine the logical level (H level / L level) of the input drive signal.

The following three methods can be considered as this determination method.
1. The level conversion circuit itself has a determination reference voltage.
2. Input the judgment reference voltage from outside.
3. The drive signal is changed to a two-phase signal having opposite phases, and the logic level is determined at the cross point of the two-phase signal.

  However, in the above method 1, since the power supply voltage of the level conversion circuit itself is the power supply voltage of the display panel, only one type of determination reference voltage can be set. Therefore, whenever the power supply voltage used in the external drive IC is changed and the amplitude of the drive signal input from the drive IC to the display panel is changed accordingly, the level conversion circuit itself must be changed. There are challenges.

  The method 2 has a problem that since it is necessary to generate a determination reference voltage externally, the number of elements on the external drive board increases, and the cost increases accordingly. Further, in the above method 3, since one input pin of the display panel is added per one drive signal, the number of input pins is increased by the number of drive signals, and two-phase signals having opposite phases are externally connected. Therefore, there is a problem that the number of elements and the wiring area on the external drive board increase.

  The present invention has been made in view of the above problems, and the object of the present invention is to mount a level conversion circuit in the display panel and to provide a judgment reference voltage to the level conversion circuit itself. An object of the present invention is to provide a display device capable of setting a determination reference voltage corresponding to the amplitude of a drive signal input from a power supply voltage of a drive IC, and a method for driving the display device.

  In order to achieve the above object, according to the present invention, a pixel array unit in which pixels including electro-optic elements are two-dimensionally arranged in a matrix on a substrate, and each pixel of the pixel array unit is driven from outside the substrate. Drive means for inputting a drive signal for performing the operation into the substrate, and level conversion means provided in the substrate for converting the level of the drive signal input from the drive means into a first power supply voltage in the substrate And generating a reference voltage for determining the logic level based on the second power supply voltage supplied from the driving unit, and supplying the determination reference voltage to the level converting unit. To do.

  In the display device having the above-described configuration, the determination reference voltage for determining the logic level of the driving signal input from the driving unit into the substrate by the level converting unit is not the first power supply voltage in the substrate but the driving unit. Even if the second power supply voltage used in the external driving means is changed by generating based on the given second power supply voltage, a determination criterion corresponding to the amplitude of the drive signal input from the drive means The voltage can be set.

  According to the present invention, by generating the determination reference voltage based on the power supply voltage supplied from the external drive unit, the determination reference voltage can be set according to the amplitude of the drive signal input from the drive unit. Even if the power supply voltage of the external drive means is changed and the amplitude of the drive signal is changed accordingly, there is no need to change the circuit that generates the determination reference voltage, and it depends on the power supply voltage of the drive means. Therefore, a stable level conversion operation can be performed.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram showing an outline of the configuration of a display device according to an embodiment of the present invention. Here, as an example, a dot sequential drive type active matrix liquid crystal display device using a liquid crystal cell as an electro-optical element of a pixel will be described as an example. As is apparent from FIG. 1, the active matrix type liquid crystal display device according to this embodiment includes a pixel array unit 11, a vertical drive circuit 12, a horizontal drive circuit 13, and a level conversion circuit unit 14 on the same substrate (hereinafter referred to as a display panel). And a driving IC 16 which is provided on the display 15 and serves as a driving means for displaying and driving each pixel of the pixel array section 11 is arranged outside the display panel 15.

  In the pixel array unit 11, pixels 20 including liquid crystal cells as electro-optical elements are two-dimensionally arranged in a matrix on a transparent insulating substrate, for example, a first glass substrate (not shown), and m rows of the pixels 20 are arranged. The scanning lines 17-1 to 17-m are wired for every row in the arrangement of n columns, and the signal lines 18-1 to 18-n are wired for every column. The first glass substrate is disposed opposite to the second glass substrate with a predetermined gap, and a liquid crystal material is sealed between the second glass substrate to constitute the display panel 15. Yes.

  FIG. 2 is a circuit diagram illustrating an example of a circuit configuration of the pixel (pixel circuit) 20. As apparent from FIG. 2, the pixel 20 includes a pixel transistor, for example, a TFT (Thin Film Transistor) 21, a liquid crystal cell 22 in which the pixel electrode is connected to the drain electrode of the TFT 21, and one of the drain electrode of the TFT 21. And a storage capacitor 23 to which the electrodes are connected. Here, the liquid crystal cell 22 means a liquid crystal capacitance Clc generated between the pixel electrode and a counter electrode formed opposite to the pixel electrode.

  The TFT 21 has a gate electrode connected to the scanning line 17 (17-1 to 17-m) and a source electrode connected to the signal line 18 (18-1 to 18-n). Further, for example, the counter electrode of the liquid crystal cell 22 and the other electrode of the storage capacitor 23 are connected to the common line 24 in common for each pixel. A common voltage (counter electrode voltage) Vcom is applied to the common electrode of the liquid crystal cell 22 via the common line 24.

  The vertical drive circuit 12 is disposed, for example, on the left side of the pixel array unit 11. Here, the configuration in which the vertical drive circuit 12 is disposed on the left side of the pixel array unit 11 is described as an example, but the vertical drive circuit 12 is disposed on the right side of the pixel array unit 11 or on both the left and right sides of the pixel array unit 11. It is also possible to adopt a configuration in which The vertical drive circuit 12 is configured by a shift register, a buffer circuit, and the like, and is synchronized with a vertical clock pulse VCK (generally, vertical clock pulses VCK and VCKX having phases opposite to each other) by receiving a vertical start pulse VST. Thus, the vertical scanning pulses φV1 to φVm are sequentially output and applied to the scanning lines 17-1 to 17-m of the pixel array unit 11 to sequentially select the pixels 20 in units of rows.

  The horizontal drive circuit 13 is configured to include, for example, a horizontal scanning circuit 131 and horizontal sampling switches 132-1 to 132-n. The horizontal scanning circuit 131 includes a shift register and starts a shift operation in response to a horizontal start pulse HST. The horizontal start pulse HST is converted into a horizontal clock pulse HCK (generally, horizontal clock pulses HCK having opposite phases to each other). , HCKX) and sequentially shifting the transfer pulses of each transfer stage as horizontal sampling pulses φH1 to φHn.

  One end of each of the horizontal sampling switches 132-1 to 132-n is commonly connected to the video signal line 19, and the other end is respectively connected to one end of each of the signal lines 18-1 to 18-n of the pixel array unit 11. ing. These horizontal sampling switches 132-1 to 132-n are turned on in response to horizontal sampling pulses φH1 to φHn sequentially output from the horizontal scanning circuit 131, so that the video signal lines 19 are connected from the outside of the display panel 15. The analog video signal Vsig input via the signal is sequentially sampled and supplied to the signal lines 18-1 to 18-n.

  The drive IC 16 performs various drive signals for driving the display panel 15, for example, a vertical start pulse VST and a vertical clock pulse VCK for driving the vertical drive circuit 12, and a horizontal start for driving the horizontal drive circuit 13. A pulse HST and a horizontal clock pulse HCK are input into the display panel 15.

  Here, in the display panel 15, a voltage of about ± 5 [V] is applied to the liquid crystal to obtain contrast, so that the power supply voltage VCC1 is 10 [V] or more, for example, 15.5 [V] or 13.5. On the other hand, in the drive IC 16, the power supply voltage VCC2 is being lowered in recent years as the design rule is reduced. For example, 5 [V], 3.3 [ V], 2.5 [V], or 1.8 [V]. Therefore, taking the case of VCC2 = 5 [V] as an example, the voltage amplitudes of the vertical start pulse VST, the vertical clock pulse VCK, the horizontal start pulse HST, and the horizontal clock pulse HCK input from the drive IC 16 into the display panel 15 are as follows. It is about 0-5 [V].

  Accordingly, the voltage amplitude of the vertical start pulse VST, the vertical clock pulse VCK, the horizontal start pulse HST and the horizontal clock pulse HCK input into the display panel 15 is determined from the voltage amplitude corresponding to the power supply voltage VCC2 of the driving IC 16. 15 is required to be level-converted to a voltage amplitude corresponding to the power supply voltage VCC1 in FIG. These level conversions are executed in, for example, four level conversion circuits 141 to 144 of the level conversion circuit unit 14.

  The present invention is characterized by the configuration of these level conversion circuits 141-144. Specifically, the power supply voltage VCC2 of the drive IC 16 is input into the display panel 15 through the power supply line 31, while the level conversion circuits 141 to 144 use the vertical start pulse VST and the vertical based on the power supply voltage VCC2 applied from the drive IC 16. It is characterized in that a determination reference voltage Vref that is a reference for determining the logic level (H level / L level) of the clock pulse VCK, the horizontal start pulse HST, and the horizontal clock pulse HCK is generated.

  As described above, the drive signals input from the external drive IC 16 into the display panel 15, in this example, the logical levels of the vertical start pulse VST, the vertical clock pulse VCK, the horizontal start pulse HST, and the horizontal clock pulse HCK are determined. By generating the determination reference voltage Vref based on the power supply voltage VCC2 of the drive IC 16 instead of the power supply voltage VCC1 in the display panel 15, the determination reference voltage Vref corresponds to the amplitude of the drive signal input from the drive IC 16. Can be set. As a result, even if the power supply voltage VCC2 of the drive IC 16 is changed and the amplitude of the drive signal is changed accordingly, there is no need to change the circuit that generates the determination reference voltage Vref, and the level conversion circuit 141 In ~ 144, a stable level conversion operation can be performed regardless of the power supply voltage VCC2 of the drive IC 16.

  Further, since it is not necessary to provide a level conversion circuit on an external drive board (not shown) or on the drive IC 16, noise at the time of level conversion to a high voltage on the drive board (not shown) or the drive IC 16 In addition, it is possible to reduce the coupling noise caused by the high amplitude drive signal and the video signal Vsig being input to the display panel 15 in parallel. As a result, it is possible to prevent deterioration in image quality due to potential fluctuation of the video signal line 19 caused by noise, and it is possible to widen the operation margin of the liquid crystal display device.

  Specific examples of the level conversion circuits 141 to 144 will be described below. Since the level conversion circuits 141 to 144 basically have the same circuit configuration, the level conversion circuit 141 that performs level conversion for one of them, for example, the vertical start pulse VST, will be described below as an example. And

[First embodiment]
FIG. 3 is a circuit diagram showing a configuration example of the level conversion circuit 141A according to the first embodiment of the present invention. In FIG. 3, the power supply voltage VCC2 used in the drive IC 16 is input into the display panel 15 through the power supply line 31, and is given to the level conversion circuit 141A. The drive IC 16 has a buffer 161 operating at the power supply voltage VCC2 at its output stage. As a result, a vertical start pulse vst having a voltage amplitude corresponding to the power supply voltage VCC2 is output from the drive IC 16 and input to the level conversion circuit 141A in the display panel 15.

  The level conversion circuit 141A includes a determination circuit unit (level conversion unit) 41, a reference voltage generation circuit unit 42, and an inverter 43. A buffer may be used instead of the inverter 43.

  The determination circuit unit 41 includes Pch transistors Qp11 and Qp12 whose sources are connected to the power supply line 32 of the power supply voltage VCC1, Nch transistors Qn11 whose drains are connected to each other, and whose sources are connected in common. , Qn12, and an Nch transistor Qn13 connected between a source common connection node of these transistors Qn11, Qn12 and a reference potential node, for example, a ground potential (GND) node, and having a gate applied with a bias voltage Vbias. A latch type amplifier structure in which the gate of the transistor Qp11 is connected to the drain common connection node of the transistors Qp12 and Qn12, and the gate of the transistor Qp12 is connected to the drain common connection node of the transistors Qp11 and Qn11. It has become.

  The reference voltage generation circuit unit 42 includes Nch transistors Qn21 and Qn22 that are connected in series between the power supply line 31 of the power supply voltage VCC2 and the ground potential node, and have the gate applied with the power supply voltage VCC1. These transistors Qn21, The determination reference voltage Vref1 corresponding to the power supply voltage VCC2 is generated by the division by the on-resistance ratio of Qn22. Here, the determination reference voltage Vref1 is generated by the on-resistance ratio of the Nch transistors Qn21 and Qn22. However, a Pch transistor is used instead of the Nch transistors Qn21 and Qn22, and the determination reference voltage Vref1 is generated by the on-resistance ratio of these Pch transistors. It is also possible to do.

  The reference voltage generation circuit unit 42 further includes an impedance conversion circuit 421 connected between the output node NA of the determination reference voltage Vref1 and the determination circuit unit 41. The impedance conversion circuit 421 has a non-inverting (+) input terminal connected to the output node NA, an inverting (−) input terminal connected in common with the output terminal, and the gate of the Pch transistor Qp12 in the determination circuit unit 41. It is configured by a connected operational amplifier OP. Thus, the determination reference voltage Vref1 generated by the reference voltage generation unit 42 is impedance-converted by the impedance conversion circuit 421 to become the determination reference voltage Vref2, and is supplied to the determination circuit unit 41 as its reference input.

  The determination circuit unit 41 uses a vertical start pulse vst having a voltage amplitude corresponding to the power supply voltage VCC2 as a comparison input, that is, the gate input of the Pch transistor Qn11, and a determination reference voltage Vref2 corresponding to the power supply voltage VCC2 as a reference input, that is, the Pch transistor Qn12. As a gate input, the logical level of the vertical start pulse vst is determined based on the determination reference voltage Vref2. When the logical level of the vertical start pulse vst is H level equal to or higher than the determination reference voltage Vref2, the ground potential GND is set to L level, and when the logical level of the vertical start pulse vst is lower than the determination reference voltage Vref2, the power supply voltage VCC1 is determined to be H level. Output a pulse. This determination pulse is inverted by the inverter 43 to become a vertical start pulse VST having an amplitude voltage of GND (0 [V]) − VCC1.

  As described above, in the level conversion circuit 141A according to the first embodiment, the determination reference voltage Vrfe1 is determined by the on-resistance ratio of the transistors Qn21 and Qn22 connected in series between the power supply line 31 of the power supply voltage VCC2 and the ground potential node. Since the transistors Qn21 and Qn22 can be formed by the same process as other circuit portions, a highly accurate circuit can be configured at low cost. Further, the impedance conversion circuit 421 is connected between the output node NA of the determination reference voltage Vref1 and the determination circuit unit 41, and the impedance of the determination reference voltage Vref1 is converted and applied to the determination circuit unit 41. Since the operational amplifier OP can compensate for gate coupling noise or the like from the determination circuit unit 41, a level conversion circuit 141A resistant to noise can be configured.

[Second Embodiment]
FIG. 4 is a circuit diagram showing a configuration example of the level conversion circuit 141B according to the second embodiment of the present invention. In the figure, the same parts as those in FIG. In FIG. 4, the power supply voltage VCC2 used in the drive IC 16 is input into the display panel 15 via the power supply line 31 and applied to the level conversion circuit 141B, and the drive IC 16 operates at the output stage with the power supply voltage VCC2. The point having the buffer 161 is the same as in the first embodiment.

  The level conversion circuit 141B includes a determination circuit unit (level conversion unit) 51, a reference voltage generation circuit unit 52, and an inverter 53. A buffer may be used in place of the inverter 53.

  The determination circuit 51 includes a Pch transistor Qp21 having a source connected to the power supply line 32 of the power supply voltage VCC1, a gate and a drain connected in common, a source connected to the power supply line 32, and a gate connected to the gate / drain of the transistor Qp21. Pch transistor Qp22 connected to each other, Nch transistors Qn21 and Qn22 whose drains are connected to each other and whose sources are connected in common, and the source common connection node of these transistors Qn21 and Qn22 and the reference potential For example, it has a mirror amplifier configuration having an Nch transistor Qn23 connected to a node, for example, a ground potential (GND) node, and having a bias voltage Vbias applied to the gate.

  The reference voltage generation circuit unit 52 includes resistance elements R21 and R22 connected in series between the power supply line 31 of the power supply voltage VCC2 and the ground potential node, and the power supply is generated by dividing the resistance elements R21 and R22 by the resistance ratio. A determination reference voltage Vref corresponding to the voltage VCC2 is generated. The reference voltage generation circuit unit 52 further includes a compensation capacitor C connected between the output node NB of the determination reference voltage Vref and the ground potential node.

  The determination circuit unit 51 uses the vertical start pulse vst having a voltage amplitude corresponding to the power supply voltage VCC2 as a comparison input, that is, the gate input of the Pch transistor Qn21, and the determination reference voltage Vref corresponding to the power supply voltage VCC2 as a reference input, that is, the Pch transistor Qn22. As a gate input, the logical level of the vertical start pulse vst is determined based on the determination reference voltage Vref. When the logical level of the vertical start pulse vst is H level equal to or higher than the determination reference voltage Vref, the ground potential GND is set to L level, and when the logic level is lower than the determination reference voltage Vref, the power supply voltage VCC1 is determined to be H level. Output a pulse. This determination pulse is inverted by the inverter 53 to become a vertical start pulse VST having an amplitude voltage of GND (0 [V]) − VCC1.

  As described above, in the level conversion circuit 141B according to the second embodiment, the determination reference voltage Vrfe is determined by the resistance ratio of the resistance elements R21 and R22 connected in series between the power supply line 31 of the power supply voltage VCC2 and the ground potential node. The determination reference voltage Vrfe can be generated with a simple circuit configuration. Further, since the compensation capacitor C is connected between the output node NB of the judgment reference voltage Vref and the ground potential node, the compensation capacitor C compensates for the gate coupling noise or the like from the judgment circuit unit 51. Therefore, the level conversion circuit 141B resistant to noise can be configured.

  In each of the above embodiments, the level conversion circuit 141 that handles the vertical start pulse VST has been described as an example. However, the level conversion circuits 142 to 144 that handle other drive signals are exactly the same as the level conversion circuit 141. I can say that. Further, the number of level conversion circuits is not limited to four, and the drive signal is not limited to the vertical start pulse VST, the vertical clock pulse VCK, the horizontal start pulse HST, and the horizontal clock pulse HCK.

  As an example, in the case of a liquid crystal display device having a configuration in which a timing generator for generating a vertical start pulse VST, a vertical clock pulse VCK, a horizontal start pulse HST, and a horizontal clock pulse HCK is mounted in the display panel 15, the timing generator includes On the other hand, the master clock MCK, the horizontal synchronization signal Hsync, and the vertical synchronization signal Vsync are input as drive signals from the outside of the panel, and the level conversion of these drive signals is performed. Therefore, the present invention is applied to this level conversion. You can do that.

(Application examples)
FIG. 5 is a block diagram showing an example of the configuration of the level conversion circuit unit 14 'according to the application example of the present invention. Here, a case where the level conversion circuit unit 14 ′ includes, for example, four level conversion circuits 141 to 144 corresponding to FIG. 1 will be described as an example.

  In the level conversion circuit unit 14 ′ according to this application example, a reference voltage generation circuit 145 (the reference voltage generation circuit unit 42 in FIG. 3 and the reference voltage generation circuit 42 in FIG. 4) that generates the determination reference voltage Vref based on the power supply voltage VCC2 of the external drive IC 16 is used. The reference voltage generation circuit unit 52) is provided in common for the four level conversion circuits 141 to 144. That is, the determination reference voltage Vref generated by the reference voltage generation circuit 145 is commonly applied to the four level conversion circuits 141 to 144.

  Here, a case where the reference voltage generation circuit unit 52 of FIG. 4 is used as the reference voltage generation circuit 145 is shown as an example. In this case, the compensation capacitor C can also be provided in common for the four level conversion circuits 141 to 144. That is, it is only necessary to connect the compensation capacitor C between the output node of the reference voltage generation circuit 145 and the reference potential node. When the reference voltage generation circuit unit 42 of FIG. 3 is used as the reference voltage generation circuit 145, an impedance conversion circuit 421 (see FIG. 3) is provided between the output node of the reference voltage generation circuit 145 and the level conversion circuits 141 to 144. One reference) may be connected in common.

  Thus, by adopting a configuration in which the reference voltage generation circuit 145 that generates the determination reference voltage Vref is provided in common to the four level conversion circuits 141 to 144, the reference voltage generation circuit 145 is converted into four levels. The circuit configuration can be greatly simplified as compared with the case where each of the circuits 141 to 144 is provided, and the wiring of the power supply line 31 that tends to be thicker than the signal line needs to be routed between the four level conversion circuits 141 to 144. Therefore, it is possible to reduce the area of a region (so-called frame) that forms a circuit portion on the display panel 15.

  In the above embodiment, the case where the present invention is applied to a liquid crystal display device using a liquid crystal cell as an electro-optical element of the pixel has been described as an example. However, the present invention is not limited to this application example, and the electric For display devices in which level conversion circuits are mounted on a display panel in which pixels including electro-optical elements are arranged in a two-dimensional array, such as organic EL display devices using organic EL (electro luminescence) elements as optical elements Applicable.

1 is a block diagram illustrating an outline of a configuration of a dot sequential drive type active matrix liquid crystal display device according to an embodiment of the present invention. FIG. It is a circuit diagram which shows an example of a circuit structure of a pixel (pixel circuit). 1 is a circuit diagram illustrating a configuration example of a level conversion circuit according to a first embodiment of the present invention. FIG. It is a circuit diagram which shows the structural example of the level conversion circuit which concerns on 2nd Example of this invention. It is a block diagram which shows an example of a structure of the level conversion circuit part which concerns on the application example of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11 ... Pixel array part, 12 ... Vertical drive circuit, 13 ... Horizontal drive circuit, 14, 14 '... Level conversion circuit part, 15 ... Display panel, 16 ... Drive IC, 20 ... Pixel (pixel circuit), 21 ... TFT ( Pixel transistor), 22 ... liquid crystal cell (liquid crystal capacitor), 23 ... holding capacitor, 31 ... power supply line of VCC2, 32 ... power supply line of VCC1, 41, 51 ... determination circuit unit (level conversion unit), 42, 52 ... reference Voltage generation circuit unit, 43, 53... Inverter, 141 to 144, 141A, 142B... Level conversion circuit

Claims (7)

A pixel array unit in which pixels including electro-optic elements are two-dimensionally arranged in a matrix on a substrate;
Driving means for inputting a driving signal for driving each pixel of the pixel array unit from the outside of the substrate into the substrate;
Level conversion means provided in the substrate and converting the level of the drive signal input from the drive means to a first power supply voltage in the substrate;
A reference voltage generator provided in the substrate and generating a determination reference voltage for determining a logic level based on a second power supply voltage supplied from the driving unit and supplying the determination reference voltage to the level conversion unit And a display device. The reference voltage generation unit generates the determination reference voltage according to an on-resistance ratio of a transistor connected in series between a power supply line of the second power supply voltage and a reference potential node. The display device described. The display device according to claim 2, wherein the reference voltage generation unit includes an impedance conversion circuit connected between an output node of the determination reference voltage and the level conversion unit. The reference voltage generation unit generates the determination reference voltage according to a resistance ratio of a resistance element connected in series between a power supply line of the second power supply voltage and a reference potential node. The display device described. The display device according to claim 4, wherein the reference voltage generation unit includes a compensation capacitor connected between an output node of the determination reference voltage and the reference potential node. A plurality of the level conversion means are provided in the substrate,
The display device according to claim 1, wherein the reference voltage generation unit applies the determination reference voltage to the plurality of level conversion units in common. A pixel array unit in which pixels including electro-optic elements are two-dimensionally arranged in a matrix on a substrate;
Driving means for inputting a driving signal for driving each pixel of the pixel array unit from the outside of the substrate into the substrate;
Level conversion means provided in the substrate and converting the level of the drive signal input from the drive means into a first power supply voltage in the substrate, comprising:
A method for driving a display device, comprising: generating a determination reference voltage for determining a logic level based on a second power supply voltage supplied from the driving unit; and supplying the determination reference voltage to the level conversion unit. .

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