JP2001282208A - Liquid crystal drive assembly and drive method for the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain an optimum drive assembly of a display device by using a power supply oscillation method and a drive method for the same. SOLUTION: The plural power supplies of part of the plural power supplies of the display device consisting of the power supplies, a drive signal processing device, an output device for signal electrodes, an output device for scanning electrodes and a matrix electrode composed of the signal electrodes and the scanning electrodes are formed as DC power supplies having approximately the specified potential with the time and the plural power supplies of another part of the plural power supplies are formed as oscillation power supplies having the periods changing in the potential with respect to the time. The signal electrodes are driven by processing the DC power supplies to signal electrode drive waveforms by the output device for the signal electrodes and the scanning electrodes are driven by processing the oscillation power supplies and the DC power supplies to signal electrode drive waveforms by the output device for the scanning electrodes. The signals obtained from the DC power supplies are converted into the signals obtained from the oscillation power supplies by the constitution to insert at least one level shifter assembly to the fore stage of the drive signal processing circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device having a matrix type pixel arrangement (hereinafter, referred to as a display device), and more particularly to a scan electrode driving device for a pixel and a driving method thereof.

[0002]

2. Description of the Related Art In recent years, with the progress of the information society, matrix type display devices include, for example, an EL (electroluminescence) display device, a passive address type liquid crystal display device represented by a liquid crystal display device, and an active address type liquid crystal display device. (TFT, MIM, DFT) The liquid crystal display device is a television, a monitor for a personal computer, a navigation display device, a projector display device, a head-up display device,
It is used in a wide range of fields such as game display devices, telephone display devices, and pachinko game machine display devices. In particular, liquid crystal display devices are small, thin, light, and small in size because of their low power consumption. It has been widely used. Since EL display devices have problems such as high power consumption and short lifetime, many liquid crystal display devices are currently commercialized in various display device application fields.

As described above, a display device using a liquid crystal or EL (electroluminescence) has advantages of being small, thin, light, and low in current consumption. The display device does not fully utilize this advantage as described below. Hereinafter, the present invention will be described using a liquid crystal display device, but the present invention can also be used for a matrix display device such as an EL device. Conventional example 1. FIG. 14 shows a block diagram of one circuit configuration system in the prior art. In FIG.
The drive circuit of the liquid crystal display device 30 includes a signal electrode drive circuit 35 for driving the signal electrodes of the liquid crystal display device 30 and a scan electrode drive circuit 34 for driving the scan electrodes provided in a direction orthogonal to the signal electrodes. You. The scan electrode drive circuit 34 receives a scan electrode drive high voltage DC and logic circuit low voltage DC power supply 39 and a scan electrode drive circuit timing signal 38 which is a signal from the LCD controller 40. Drive signals for driving the scan electrodes are output to the scan electrodes by these power supplies and timing signals. The scanning electrode is also called a common electrode or a common electrode. The signal electrode drive circuit 35 receives a signal electrode DC power supply 37, a timing signal as a signal from the LCD controller 40, and a signal electrode drive circuit data signal 36. A drive signal for driving the signal electrode is output to the signal electrode by the power supply and the timing signal. The signal electrode is also called a segment electrode. On the other hand, as shown in FIG. 14, the LCD panel 31 schematically includes a display area 32 and a peripheral area 33 in this specification.
Is divided. Conventional example 2. For example, because portability is especially important,
While miniaturization is required, a larger screen is required for visibility. Therefore, there is a strong demand for expanding the display area of the liquid crystal display device within a limited area, while the peripheral area is becoming increasingly narrower. For example,
As shown in FIG. 14, in a chip-on-glass structure (hereinafter, referred to as COG) in which an IC that is an integrated circuit is mounted on a substrate in an IC chip state in a peripheral region, the IC needs to be smaller in order to reduce the peripheral region. There is. If the IC becomes smaller, TAB (tape automatic bonding) or TCP (tape carrier package), which is a mounting method similar to that of COG, can be made smaller, and the peripheral area can be narrowed.

One of the measures to cope with such narrowing of the frame is to make the scanning electrode driving device (integrated circuit) and the signal electrode driving device (integrated circuit) slim and downsized. One of the methods for slimming and miniaturizing the signal electrode driving device is to reduce the size of the element by lowering the withstand voltage.

In the conventional method, as shown in FIG. 15, the potential is changed during the liquid crystal alternating current operation, and the scan electrode driving device outputs a combination of V1 and V2 and V3 and V4. The electrode driving device is also V5 and V4, V1
And V6. Therefore, both the scanning electrode driving device and the signal electrode driving device require a withstand voltage equal to or higher than the potential difference between V1 and V4, and thus require a high withstand voltage electrode driving device. Therefore, a semiconductor switching circuit with a high withstand voltage is required, and an integrated circuit with a high withstand voltage is required.

In this method, the signal electrode driving device must also be constituted by a device having a high withstand voltage, and the size and the density have not been sufficiently obtained. In addition, there is a problem that it is not possible to obtain a high-speed operation of the signal electrode driving device due to an increase in the number of data signals accompanying an increase in the number of pixels. In addition, with respect to power consumption, since high voltage must be operated at high speed, low power consumption cannot be sufficiently obtained.

As one of the solutions to these problems,
Japanese Patent Application Laid-Open No. 60-249191 (U.S. Pat. No. 4,843,252) previously filed by the present applicant,
A driving method using the power supply swinging method disclosed in, for example, Japanese Patent No. 788 (US Pat. No. 5,101,116) is exemplified. That is, although the EL and the liquid crystal display are driven by an alternating current,
The DC power supply before AC conversion needs to have an output of √2 (route 2) or more times the AC drive effective value. Further, in an n-digit matrix having n timing electrode lines having different timing phases, the amplitude of the pixel selection drive voltage applied when driving the target pixel is approximately equal to the amplitude of the pixel bias drive voltage of √n ( It is well known to those skilled in the art that the contrast is best at the time of root n) times. This means that the liquid crystal performance cannot be sufficiently brought out unless the driving voltage is increased as the number of digits n of the matrix increases.

[0008] As in recent years, the pixel voltage of a liquid crystal display device has become finer and the number of electrode patterns has increased, so that the driving voltage has been increasing. A high AC voltage or AC amplitude is required to increase the contrast, increase the transmission brightness, and to adjust the display gradation appropriately. For this reason, a push-pull drive is used as an output circuit to drive the liquid crystal. Is used. A driving example using this push-pull driving method is described in Society of Display Journal Vol. 26/1, '85,
It is disclosed on pages 9-15. In this push-pull drive, two voltage generating circuits having AC polarities opposite to each other are prepared, and a liquid crystal element, which is an element, is driven by a difference between the two voltages, so that a driving voltage of up to twice the power supply voltage is output. Is obtained. When the drive voltage of the push-pull circuit increases, a large amount of through current flows due to a shift in the switching timing of the transistors in the push-pull configuration, and the current consumption of the liquid crystal drive circuit increases. When a drive circuit is integrated, that is, when designing for making into an IC, if a circuit with a high withstand voltage is integrated into the IC, the degree of integration of the IC decreases and the operation of the circuit is slowed down. There is a problem that is opposite to the direction of obtaining a small display device.

Therefore, a second pulse signal having a different reference voltage level is generated from the pulse generation signal using a clamp circuit, and the two are combined to have a drive output having a potential difference greater than the power supply voltage. High withstand voltage IC using a technology called a swing power supply that does not have a potential difference greater than the voltage
The applicant has previously proposed a circuit which does not require the above. Here, the power supply swing method proposed by the applicant will be described with reference to the drawings. As shown in FIG. 16 showing the state of the power supply potential in the power supply swing method, the ground potential is changed from VA to VB. As for the switched potential and the high voltage potential in synchronism therewith, by inputting the potential switched from VC to VD to the scan electrode device, the withstand voltage of the signal electrode drive device can be greatly increased without increasing the withstand voltage of the scan electrode drive device. As a result, it is possible to increase the speed of operation, increase the density, and reduce the power consumption of the signal electrode driving device due to the increase in data signals.

However, when a signal is input to the scan electrode driving device from an external system using the power supply swing method (also referred to as a swing power supply), the power supply potential is in the period A as shown in FIG. Sometimes, in the scan electrode driving device,
When the input signal is at the VB level, the input is a low level (low potential) input. When the input signal is at the VD level, the input is at a high level (high potential). When the power supply potential is in the period B,
In the scan electrode driving device, when the input signal is at the VA level, the input is at the low level, and when the input signal is at the VC level, the input is at the high level.

Therefore, when a signal is input from an external system, VD level or VC level input is required when a high level is input, and VB level is input when a low level is input, depending on the state of the power supply potential. Level or VA level input is required. Therefore, the potential of the input signal must be changed from the outside, and an external circuit for converting the potential of the input signal is required.

[0012]

However, in the past proposals, although there is a principle disclosure of the oscillating power supply itself, when the above-described principle is used in a display device, a circuit that maximizes the effect, and a display device Was not disclosed. For this reason, even if the drive power supply can be downsized to some extent,
In the oscillating power supply device and its peripheral circuits, sufficient miniaturization, low power consumption, and high display quality (for example, appearance and display unevenness) have not been obtained. In view of such a conventionally disclosed technology, an object of the present invention is to provide a display device that solves the further problems of the conventional technology and improves the performance of the basic technology. This is because of the advantages of the small, thin, lightweight, and low current consumption of the liquid crystal, the small, thin, light, and low current consumption of the display device. A driving device and a driving method are obtained.

[0013]

In order to solve the above-mentioned problems, the present invention provides a plurality of power supplies for generating a plurality of potentials, and a plurality of drive signal processing devices for processing a display driving signal using the plurality of power supplies. A signal electrode output device for driving a signal electrode with a signal from some of the drive signal processing devices, and a scan electrode output device for driving a scan electrode with a signal from another some of the drive signal processing devices, and the signal In a liquid crystal driving device including a matrix electrode composed of electrodes and the scanning electrodes, and a driving method thereof, a part of the plurality of power sources is a DC power source having a substantially constant potential with respect to time, The other part of the plurality of power supplies is an oscillating power supply having a period in which the potential changes with time, and the signal electrode processes the DC power supply into a signal electrode driving waveform by the signal electrode output device. This drives the signal electrode,
The scan electrode drives the scan electrode by processing the oscillating power supply and the DC power supply into a scan electrode drive waveform by the scan electrode output device, and at least one level shifter is provided upstream of the drive signal processing circuit. A signal obtained from a DC power supply is converted into a signal obtained from a swing power supply by a configuration in which the device is inserted.

The oscillating power source is a specified pulse shaping device for generating a specified pulse, a first power supply device for generating a potential which is a source of the oscillating power source, and the first power source based on a signal from the specified pulse shaping device. A pulse amplifying device for switching a power supply supplied from the device to generate a pulse which is a source of the oscillating power supply; and a level clamp device. The power supply of the amplification device is connected to the first power supply device, and the output of the pulse amplification device is connected to the level clamp device.

The oscillating power supply has at least a oscillating high power supply and an oscillating low power supply supplied to the scan electrode output device, and at least a oscillating power supply supplied to a level shifter device and a signal processing device. I do.

It is characterized in that the first power supply device is constituted by a switching power supply device.

It is characterized in that the prescribed pulse shaping device is an integrated circuit device constituted by bipolar transistors.

The pulse amplifying device comprises a first transistor and a second transistor, a source or an emitter of the first transistor is connected to a first power supply, and a drain or a collector of the first transistor is a second transistor. And a source or an emitter of the second transistor has a push-pull circuit connection connected to a second power supply.

The first transistor in the pulse amplifying device is a P-type field-effect transistor, the second transistor is an NPN transistor, the first power supply is a high DC power supply, and the second power supply is a low DC power supply. There is a feature.

[0020] The level clamp device is characterized in that the level clamp device comprises a capacitor and a diode, and the level clamp device comprises a capacitor and a transistor.

The level clamp period of the transistor is controlled by connecting the output of the prescribed pulse shaping device to the gate or base of the transistor of the level clamp device comprising a capacitor and a transistor.

Preferably, the level clamp device is at least a first
, A second capacitor and a third capacitor, one terminal of each of the capacitors being connected to the output of the pulse amplifier, and the other terminal of the first capacitor being connected to a first diode. The other terminal of the first diode is connected to a DC power supply for determining a level clamp potential, and the output of the oscillating power supply is obtained from a connection portion where the first capacitor and the first diode are connected. The other terminal of the second capacitor is connected to a second diode, and the other terminal of the second diode is connected to a DC power supply that determines a level clamp potential. And the other terminal of the third capacitor is connected to the drain of a transistor. Other features a connected to each output of the specified pulse shaper to the gate or base of said transistor is connected to a DC power supply source or drain of said transistor being connected to the collector to determine the level clamp potential.

A plurality of power supplies for generating a plurality of potentials, a plurality of drive signal processing devices for processing display driving signals using the power supplies, and signal electrodes driven by signals from some of the drive signal processing devices. A scanning electrode output device for driving a scanning electrode with a signal from the signal electrode output device and a signal from the other part of the drive signal processing device, a liquid crystal driving device including a matrix electrode composed of the signal electrode and the scanning electrode, and In the driving method, a part of the plurality of power supplies is a DC power supply having a substantially constant potential with respect to time, and the other part of the plurality of power supplies has a potential with respect to time with respect to time. A swinging power supply having a period that varies according to the frequency of the swinging power supply, wherein the swinging power supply generates a specified pulse, a first power supply device that generates a potential that is a source of the swinging power supply, and the specified pulse forming apparatus. A pulse amplifying device that switches a power supply supplied from the first power supply device to generate a pulse serving as an oscillating power supply, a level clamp device including a capacitor and a diode, and a level including a capacitor and a transistor. A level clamp device having both a clamp device and an input of the pulse amplifying device connected to an output of a prescribed pulse shaping device; a power supply of the pulse amplifying device connected to the first power supply device; Is connected to a level clamp device.

A plurality of power supplies for generating a plurality of potentials, a plurality of drive signal processing devices for processing display drive signals using the power supply, and signal electrodes driven by signals from some of the drive signal processing devices. A signal electrode output device and a scan electrode output device for driving a scan electrode with a signal from another part of the drive signal processing device, a liquid crystal drive device including a matrix electrode composed of the signal electrode and the scan electrode, and In the driving method, a part of the plurality of power supplies is a DC power supply having a substantially constant potential with respect to time, and the other part of the plurality of power supplies has a potential with respect to time with respect to time. A swing power supply having a changing period, wherein the swing power supply includes a specified pulse forming device that generates a specified pulse, a first power supply device that generates a potential that is a source of the swing power source, and a specified pulse forming device. A pulse amplifying device that switches a power supply supplied from the first power supply device by a signal to generate a pulse that is a source of the oscillating power supply; a level clamp device including a capacitor and a diode; and a level clamp device including a capacitor and a transistor. Wherein the input of the pulse amplifying device is connected to the output of the prescribed pulse shaping device, the power supply of the pulse amplifying device is connected to the first power supply device, and the output of the pulse amplifying device is A level clamp period of the transistor is controlled by connecting an output of the prescribed pulse shaping device to a gate or a base of the transistor of a level clamp device connected to a clamp device and comprising a capacitor and a transistor.

A plurality of power supplies for generating a plurality of potentials, a plurality of drive signal processing devices for processing display drive signals using the power supplies, and signal electrodes driven by signals from some of the drive signal processing devices. A scanning electrode output device for driving a scanning electrode with a signal from the signal electrode output device and a signal from the other part of the drive signal processing device, a liquid crystal driving device including a matrix electrode composed of the signal electrode and the scanning electrode, and In the driving method, a part of the plurality of power supplies is a DC power supply having a substantially constant potential with respect to time, and the other plurality of power supplies has a potential with respect to time with respect to time. The signal electrode is driven by processing the DC power supply into a signal electrode drive waveform by an output device, and the scanning electrode is connected to the swing power supply and the DC power supply. Is processed by the output device into a scan electrode drive waveform, the scan electrode is driven, and the output of the oscillating power supply device for generating the oscillating power source is output from the output of the oscillating power supply between the wiring of the scan electrode output device for driving the scan electrode. Has at least a first level shifter, a second level shifter, a drive signal processing circuit, a third level shifter, and an output circuit, and is connected in the above-described order to perform optimal signal transmission to form electrodes. It is characterized by being driven.

A plurality of power supplies for generating a plurality of potentials, a plurality of drive signal processing devices for processing display drive signals using the power supplies, and signal electrodes driven by signals from some of the drive signal processing devices. A scanning electrode output device for driving a scanning electrode with a signal from the signal electrode output device and a signal from the other part of the drive signal processing device, a liquid crystal driving device including a matrix electrode composed of the signal electrode and the scanning electrode, and In the driving method, a part of the plurality of power supplies is a DC power supply having a substantially constant potential with respect to time, and the other plurality of power supplies has a potential with respect to time with respect to time. The signal electrode is driven by processing the DC power supply into a signal electrode drive waveform by an output device, and the scanning electrode is connected to the swing power supply and the DC power supply. The scanning electrode is driven by processing the scan electrode into a scan electrode driving waveform by an output device, and the wiring of a scan electrode output device for driving the scan electrode from a swing power supply device for generating the power of the swing power source. Has at least a first level shifter, a second level shifter, a drive signal processing circuit, a third level shifter, and an output circuit, and has the above-described order-connected configuration and is housed in one integrated circuit. I do.

At least a first level shifter and a second level shifter are provided between the oscillation power supply device for generating the power of the oscillation power source and the wiring of the scan electrode output device for driving the scan electrode.
Optimum signal transmission by having a level shifter, a first inverter, a drive signal processing circuit, a third level shifter, and an output circuit in which a plurality of other inverters are connected to an input stage and connected in the order described above. And driving the electrodes.

At least a first level shifter, a second level shifter, a first inverter and a drive are provided between a swing power supply device for generating the power of the swing power source and a scan electrode output device for driving the scan electrodes. Driving electrodes with optimal signal transmission by having a signal processing circuit, a third level shifter, and an output circuit in which a plurality of other inverters are connected to the input stage and connected in the order described above. It is characterized by.

The first level shifter has a gate connected to the input means, a first PMOS transistor having a source and a back gate connected to a high DC power supply, and a gate connected to a low DC power supply and a source connected to the input means. A second PMOS transistor having a back gate connected to the DC high power supply; a drain connected to the drain of the first PMOS transistor; a gate connected to the DC high power supply; and a back gate connected to the oscillating low power supply A fourth NMOS transistor 518 having a drain connected to the drain of the second PMOS transistor 516, a gate connected to the DC high power supply, and a back gate connected to the oscillating low power supply; , Having a drain connected to the source of the third NMOS transistor and having a gate connected to the second PMOS transistor. A fifth NMOS transistor whose source and back gate are connected to the oscillating low power supply, a drain connected to the source of the fourth NMOS transistor, and a gate connected to the drain of the first PMOS transistor 515 A sixth NMOS transistor 520 having a source and a back gate connected to an oscillating low power supply, and further comprising an output of the first level shifter, together with a first output obtained from a drain of the first PMOS transistor. 2 PMOS transistors 51
6 having the second output obtained from the drain.

The second level shifter has a seventh NMOS transistor 558 having a gate connected to the output of the first level shifter, a source and a back gate connected to a low swing power supply, and a drain connected to the drain of the NMOS transistor. A ninth PMOS transistor having a source and a back gate connected to a power supply during oscillation, and an eighth NMOS transistor having a gate connected to another output of the first level shifter and having a source and a back gate connected to a power oscillation low power supply A tenth PMOS transistor 557 whose drain is connected to the drain of the eighth NMOS transistor and whose source and back gate are connected to the power supply during swinging;
The gate of the MOS transistor is connected to the drain of the eighth NMOS transistor, the gate of the tenth PMOS transistor is connected to the drain of the seventh NMOS transistor 558, and the output of the second level shifter is It is characterized by a configuration obtained from the drain of an NMOS transistor.

The first inverter includes an eleventh NMOS transistor having a gate serving as an input terminal and a source and a back gate connected to a oscillating low power supply, and a gate serving as an input terminal and a source and a back gate serving as a oscillating power supply. The twelfth PMOS transistor 581 is connected to the drain of the eleventh NMOS transistor and connected to the drain of the eleventh NMOS transistor.

The third level shifter is a thirteenth PMOS transistor having a gate connected to the input means, a source and a back gate connected to the oscillating high power supply, a gate connected to another input means, a source and a back gate. Is the fourteenth PMOS transistor connected to the oscillating high power supply,
A first transistor having a drain connected to the drain of the PMOS transistor, and a back gate connected to the oscillating high power supply.
The fifth PMOS transistor has a drain connected to the drain of the fourteenth PMOS transistor, the back gate is connected to the oscillating high power supply, and the sources of the sixteenth PMOS transistor, the fifteenth PMOS transistor, and the sixteenth PMOS transistor are connected.
A PMOS transistor having a drain connected to the gate thereof, a gate connected to the input means, a source and a back gate connected to an oscillating low power supply, and a seventeenth NMOS.
A transistor having a drain connected to a source of the sixteenth PMOS transistor and a gate of the fifteenth PMOS transistor, a gate connected to the other input means of the signal, and a source and a back gate connected to an oscillating low power supply , And an eighteenth NMOS transistor, and an output of the third level shifter is obtained from a drain of the eighteenth NMOS transistor.

The output circuit has a configuration in which the source of a twenty-first PMOS transistor is connected to the source of a twenty-second NMOS transistor, and the source is connected to the drain of a nineteenth PMOS transistor and the drain of a twentieth NMOS transistor. The drain of the twenty-first NMOS transistor and the drain of the twenty-second NMOS transistor are connected to a DC intermediate power supply, and the gate of the twenty-first PMOS transistor is connected to the drain of the twenty-first PMOS transistor. A back gate connected to the output of at least one inverter connected to the input means, a back gate connected to the oscillating high power supply, and a gate of the twenty-second PMOS transistor connected to the input means; Is connected to the input of And having a connected configuration to the low power supply.

The source of the nineteenth PMOS transistor on the high potential side is connected to the oscillating high power supply in the circuit at the final stage of the scan electrode output device for driving the liquid crystal. The source terminal of the twentieth NMOS transistor on the potential side is connected to the oscillating low power supply, and the drain of the nineteenth PMOS transistor is connected to the twentieth NM transistor.
Connected to the drain of the OS transistor.
Drain of PMOS transistor and 20th NMOS
A DC intermediate power supply V is connected to the connection point with the transistor drain.
The 22nd N connected in parallel to control the supply of M
The source of the MOS transistor and the source of the twenty-first PMOS transistor are connected, and at this connection point, at least one scanning electrode is connected. The drain of the twenty-second NMOS transistor connected in parallel and the twenty-first NMOS transistor are connected to each other. The connection point to which the PMOS transistor is connected is
A DC intermediate power supply VM is connected, and
The gate of the NMOS transistor is connected to a two-input NOR circuit output, one input terminal of the NOR circuit is connected to the first input means, and the other input terminal has at least n (positive integer) of the second input means. , The gate of the nineteenth PMOS transistor is connected to a two-input NAND circuit output, one input terminal of the NAND circuit is connected to the first input means, and the other input terminal is connected to the other input terminal. The two input means are connected via at least n ± 1 (positive integer) inverters.

[0035]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a schematic block diagram of the present invention, and mainly shows an oscillating power supply and a scanning-side drive circuit connected to the output of the oscillating power supply and driving a liquid crystal using the oscillating power supply. It is the system block diagram which was done. FIG. 4 is a system block diagram mainly showing an LCD panel and a swing power generation circuit in the display device shown in FIG. 3 shown below. FIG. 2 is a diagram showing the potential of the power supply swing method (oscillation power supply) according to the embodiment of the present invention, and a diagram showing an example of the voltage level of the input signal with respect to the potential of the power supply oscillation method (oscillation power supply). It is. FIG. 3 is a block diagram showing a configuration of a specific example of a driving circuit of a liquid crystal display device according to the present invention when the present invention is used in a liquid crystal display device. FIG. 4 is a system block diagram showing the system block diagram in FIG. 1 in detail. FIG. 5 is a circuit diagram of an embodiment of the second power supply circuit 170 in the system block diagram 4. FIG. 6 is a circuit diagram of an embodiment of the first power supply circuit 150 in the system block diagram 4. FIG. 7 is a circuit diagram of an embodiment of the prescribed pulse shaping circuit 230 in the system block diagram 4. FIG.
Is a pulse amplification circuit 25 in the system block diagram 4.
FIG. 7 is a circuit diagram in an example of Example 0. FIG. 9 is a circuit diagram of an embodiment of the level clamp circuit 270 in the system block diagram 4. Here, the swing power generation circuit 102 in FIG. 3 mainly includes a first power supply circuit 150, a pulse amplification circuit 250 to which a prescribed pulse is input, and a level clamp circuit 270. FIG. 10 is a diagram showing blocks after the first level shifter (level shift circuit) in FIG. 1, and is a configuration diagram showing in detail the configuration after the first level shifter in FIG. FIG. 11 is a diagram showing a driving waveform when the liquid crystal is driven in FIG. FIG. 12 is a circuit diagram of an embodiment of the first level shifter 510 and the next-stage second level shifter 550 in the system block diagram 4 and the inverter 580 in FIG. FIG. 13 is a block diagram showing the third system block diagram in FIG.
FIG. 9 is a circuit diagram of an embodiment of a level shifter 610.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a schematic configuration diagram of the present invention, in which a first power supply circuit 150a receives DC power from a battery, an AC adapter, a car adapter and the like and outputs the received power as a stabilized DC power. The first power supply circuit 15
A pulse amplifier 250a for using the output of the first power supply circuit as a pulsed power supply using the output of the first power supply circuit 0a; A pulse power supply, which is an output of the pulse amplifier 250a, is level-clamped and outputs a waveform as shown in FIG. 2 in which the high-potential VDD and the low-potential VSS form pulse shapes, respectively. 270a. These blocks are shown in FIG.
As in the first power supply circuit 150a, the pulse amplifier 250a
And a swing power supply 270a for use as a reference potential for the level clamp. Further, the output of the pulse amplifier 250a is
a, and the pulse potential is level clamped as described above. In the above description, a level clamp circuit has been mainly described as the oscillation power supply circuit 270a, but the oscillation power supply circuit including the pulse amplifier 250a may be referred to as the oscillation power supply circuit 270a, and is not limited to the above description. The swing power supply output of VDD and VSS is obtained from the swing power supply circuit 270a. In FIG. 1, the swing power supply circuit 270a has a logic circuit output in the scan electrode drive circuit 105 (see FIG. 3) for driving the liquid crystal panel. The swing power supply VCC, which is the swing power supply output, is also output. VCC is synchronized with VDD and VSS, and if the swing potential swings upward, VDD, VCC,
The potential of both VSS changes upward. Further, a logic signal is input to the scan electrode driving circuit 105. The VDL on the high potential (H signal) side and the VSL on the low potential (L signal) side, which are DC power supplies for logic at this time, are oscillated as described above. Dynamic power supply VD
D, VCC, VSS and the scan electrode drive circuit 105 are supplied together.

The signals having the potentials of the DC power supplies VDL and VSL are supplied to the level shifter 500a (FIG. 1) by the swing power supply VDL.
The level is shifted to a signal having a potential of CC and VSS,
The signal is processed by the drive signal processing circuit 603a (FIG. 1).
Oscillating power supply V output from the drive signal processing circuit
A signal having CC and VSS is supplied to a third level shifter 610a.
And the level is shifted to the swing power supplies VDD and VSS. The signals shifted to the potentials of the swing power supplies VDD and VSS by the third level shifter are input to the next-stage output circuit 670a, which outputs the swing power supplies VDD and VS.
Since VSS is used as the power supply, the input potential of the output circuit and the power supply potential of the output circuit have a potential relationship substantially matching potential, and the output circuit is optimally driven. The liquid crystal in the liquid crystal panel 800a is driven by the scanning side drive signal generated in this manner.

Next, the gist of the swing power supply (power supply swing method) will be described with reference to FIG. FIG. 2 is a diagram showing the potential of the power supply swing method in the embodiment of the present invention, and is a diagram showing an example of the potential level of the input signal with respect to the potential of the power supply swing method. FIG. 2 shows the power supply potential input to the scan electrode drive circuit 105 (FIG. 3) shown in FIG. 2, VDD is a swing high power inside the scan electrode drive circuit 105, VCC is a swing power inside the scan electrode drive circuit 105, and VSS is a scan inside the scan electrode drive device 105. VDL is the DC high potential corresponding to the high level potential of the input signal of the external system, and VSL is the DC low potential corresponding to the low level potential of the input signal of the external system, or the ground potential in the external system. Is shown. The oscillating high potential VDD and the oscillating low power supply VSS are mainly used as scan electrode side power supplies applied to liquid crystal. The swinging power supply VCC is mainly used as a logic power supply in the scan electrode driving circuit 105. FIG.
, When VDD is L, VDD>VDL> VS
L>VCC> VSS. On the other hand, VDD
Is H, VDD>VCC>VDL>VSL> VS
It has the relationship of S. The above inequality relation is:
It is not always necessary to satisfy the condition, and it is preferable to do so. The potential relationship in the actual embodiment with respect to FIG. 2 is as follows. a. (When VDD is L) VDD, VDL>VSL>
VCC> VSS. b. (When VDD is H) VDD> VCC, VDL>
VSL> VSS. VSL ≧ VSS−VF (where VF is a forward voltage (forward breakdown) voltage of the diode). As an example of each of the above voltages, VDDmax is 21.7.
V, VSSmin: -21.7V, VDL: 1.7
V and VSL are -1.7 V, VM is 0 V (or an intermediate potential between the VDDmax and VSSmin, or
(An intermediate potential between VDL and VSL). As shown in FIG.
When D goes high, VCC and VSS also go high at the same time. That is, when VDD is at the H level, VDD
The potential difference between D and VSS, and VDD when VDD is at L level
And VSS are substantially the same. As described above, the potential of VDD or VSS itself changes, but VDD and V
The potential difference of SS is constant. Since the power supply is configured in this manner, it is called a swing power supply. In the prior art, VDD
H level and VSS L level appear at the same time, the potential difference between VDD and VSS increases, and a high-withstand-voltage IC must be manufactured, which causes problems such as an increase in the external shape of the IC and an increase in current consumption. However, as described above, the invention of the present application, namely, the phase of the VDD pulse power supply and VSS
Since the phase of the pulse power supply is matched, it is sufficient to manufacture an IC that can withstand the potential difference between VDDmax and VSSmax. By using the swing power supply of the present invention, a great improvement can be obtained in lowering the withstand voltage of the IC. Can be

Next, referring to FIG. 3, which is a block diagram showing the configuration of a specific example of the driving device 100 according to the present invention in the liquid crystal display device according to the present invention when the present invention is applied to the liquid crystal display device. The general description of the driving device in the display device of the invention will be given. The driving device 100 of the liquid crystal display device of the present invention corresponds to, for example, the signal electrode driving circuit 106 for driving a plurality of signal electrodes and the scanning electrode driving circuit IC including the level shifter and the output circuit 670a shown in FIG. , An oscillating power source generating circuit 102 substantially corresponding to the oscillating power source circuit 270a of FIG.
Power supply consisting of DC converter and LCD controller 17
The liquid crystal panel 800 has a main configuration in which liquid crystal is sealed in a gap of several μm between pattern electrodes in which 0, scanning electrodes, and signal electrodes are arranged in a matrix. A data signal and a control signal are input from the LCD controller 101 to the signal electrode drive circuit 106 and the scan electrode drive circuit 105.
Some signals, for example, a clock signal and some control signals, constitute a signal generation or signal shaping circuit outside the LCD controller, and are input as input signals 103 to the respective electrode driving circuits. Further, the scan electrode driving circuit 10
5 includes a swing power supply VD from the swing power generation circuit 102.
D, VCC, and VSS are supplied, and a DC high power supply VDL and a DC low power supply VSL are input from other power supplies. Further, a DC intermediate potential VM which is a substantially intermediate potential between the VDDmax potential and VSSmin is input from another power supply. The data signal is input to the signal electrode drive circuit 106 as described above, and the high potential VD2 for signal electrodes, the DC potential VSL, and the DC intermediate potential VM are input (not shown). As described above, the driving device 100 in FIG. 3 uses the LCD controller 101 and other logic circuits and a power source to transmit data signals, control signals, and DC power to the signal electrode driving circuit 106.
And a function of driving the signal electrode by obtaining the output of the signal electrode drive circuit by supplying the signal electrode to the circuit. In addition, the control signal, the DC power supply, and the oscillating power supply are supplied to the scan electrode drive circuit 105 by the LCD controller 101 and other logic circuits and power supplies to obtain the output of the scan electrode drive circuit and drive the scan electrodes. Has functions. In the display of the liquid crystal panel 800, the extending direction of the scanning electrode and the signal electrode is arranged orthogonally, and the liquid crystal is driven at the intersection of the orthogonal electrodes to obtain an image display.

The configuration of FIG. 1 will be further described with reference to FIG. First, when comparing the configuration of FIG. 1 with a part of the configuration of FIG. 4, the pulse amplifier 250a of FIG.
The pulse signal is input to the pulse amplifier 250, which means that the output of the prescribed pulse shaping circuit 230 in FIG. The swing power supply circuit 270a of FIG.
In FIG. 4, it substantially corresponds to a level clamp circuit. FIG.
The first power supply circuit 150a and the pulse amplifier circuit 250a may be included in the swing power supply circuit 270a and may be referred to as a swing power supply circuit. The first level shifter 510 and the second level shifter 550 in FIG. 4 correspond to the level shifter 500a in FIG. 1, and the third level shifter 610 in FIG.
The third level shifter 610 in FIG. 4 corresponds to a, and the output circuit 670 in FIG. 1 corresponds to the output circuit 670a in FIG.

In FIG. 4, a high DC potential VDL and a low DC potential VSL (ground potential) provided in the display device are input to a second power supply circuit 170, and are converted into DC-DC (DC-DC) voltages. The second power supply circuit 170 is DC-DC
The voltage-converted DC potential is output.
60 and a resistor 161 to obtain a DC intermediate potential VM which is a target potential. At this time, the resistors 160 and 16
In No. 1, a resistor having an extremely accurate resistance value of 0.5% was used. Further, a capacitor 16 is connected in parallel with the resistor 161.
2 are connected to provide a function as a power supply. As a result, the VM can be set with high accuracy and a more stable power supply can be taken out, so that the fluctuation of the display image can be suppressed and the display quality can be improved. The VM thus produced is supplied to the output circuit 670 at the subsequent stage and also supplied to the signal electrode drive circuit 106 shown in FIG.

The high DC potential VDL and the low DC potential VSL (ground potential) provided in the display device are further input to the first power supply circuit 150 and are converted into DC-DC voltages. The DC potential obtained by the DC-DC voltage conversion in the second power supply circuit is used as a power supply for the next-stage pulse amplifier 250.

On the other hand, a signal from the LCD controller 101 which outputs a control signal for displaying an image by the specified pulse shaping circuit 230, a display data signal, a timing signal, and the like, which is included in the display device, is used for a swing power supply. The pulse is shaped into a prescribed pulse and output to the pulse amplifier 250 at the next stage.
The prescribed pulse shaping circuit 230 mainly includes a counter. The pulse waveform supplied from the prescribed pulse shaping circuit 230 is pulse-amplified by the pulse amplifier 250 using the power supplied from the first power supply circuit 150, and the pulse-amplified signal is output to the next level clamp circuit 270. The level clamp circuit 270 includes the pulse amplifier 250
Are pulse-clamped, and the oscillating high potential VDD, the oscillating potential VCC, and the oscillating low potential V as shown in FIG.
Generate SS. As will be described later, the clamp voltage of the swing high potential VDD uses the signal electrode high potential VD2 and VS
The S clamp voltage uses VSL (ground).
During the swing, the clamp voltage of the power supply VCC is clamped at the DC high potential VDL when the potential increases toward the VDDmax potential (high potential side of the VDD pulse), and clamped at the VDDmin potential (low potential side of the VDD pulse). Therefore, the waveform of the swing power supply shown in FIG. 2A is obtained.

By supplying the oscillating power supplies VDD, VSS, and VCC output from the level clamp circuit 270 to the subsequent first, second, and third level shifters, the circuit operation of the output circuit 670 is optimally started. Signal potential is obtained, and the push-pull circuit 1
It is also supplied to an output circuit composed of stages. With this configuration, the input potential of the output circuit becomes VDD and VSS, which is substantially the same as VDD and VSS which are the power supplies of the output circuit, and the operation of the output circuit can be optimized. Therefore, an output for driving the liquid crystal with one stage of the push-pull circuit is obtained. Can be The optimal behavior is, for example,
That is, the transistor constituting the push-pull circuit can be completely turned on and off, and unnecessary power consumption of the transistor can be reduced.

Next, transmission of a signal such as a clock signal will be described. The output of the level clamp circuit, VDD, V
CC and VSS are input to the scan electrode driving circuit 105 shown in FIG.
DL and VSL are input to the scan electrode drive circuit 105 together with a clock signal and various liquid crystal drive signals, for example, DFcom (liquid crystal drive pulse timing signal). VDL which is a DC power supply input to the scan electrode driving circuit 105,
VSL and clock signal and various liquid crystal drive signals DFcom
Enters the first level shifter 510, and the low potential side is VS.
The potential level higher than the S potential is shifted to the potential having the potential of VDL, and is output to the second level shifter 550 in the subsequent stage. The second level shifter 550 receives the level-shifted signal of the first level shifter 510, and after the low potential side is level-shifted to a potential having the potential of the swing power supply VCC and the high potential side to the potential having the potential of the swinging power supply VCC, Signal processing is performed by a drive signal processing circuit 603a (FIG. 1) which is a signal processing logic circuit in the scan electrode drive circuit 105. The signal processed by the logic circuit is supplied to a third level shifter 610.
The low potential side is made to have the potential of the oscillating low power supply VSS, the high potential side is level-shifted to the potential having the oscillating high power supply VDD potential, and output to the output circuit 670 at the subsequent stage. The output circuit 670 converts the drive signal level-shifted by the third level shifter 610 to a potential corresponding to the power supply potentials VDD and VSS of the output circuit into a liquid crystal drive waveform having an oscillating power supply (using a push-pull circuit). ) To output and drive the liquid crystal. By combining the swing power supply with the level shifter and using an output circuit having a swing power supply function as described above, the function of the swing power supply can be maximized with a simple configuration. The display pixels composed of the liquid crystal sandwiched between the electrodes having good performance can be driven with low power consumption and can be manufactured at low cost.

Further, the blocks of the respective parts in FIG. 4 will be described below using specific circuits. FIG. 5 is a circuit diagram of an embodiment of the second power supply circuit 170 shown in FIG.
Will be described. The second power supply circuit is generally referred to as a “three-terminal regulator”, and includes a DC-
An integrated circuit (hereinafter referred to as IC) IC1 serving as a DC power supply (DC-DC regulator) is used, and a DC low potential V
SL and the DC high potential VDL are input, and an original voltage for generating the DC intermediate potential VM, which is a DC output voltage-adjusted, is output. Since the VM is a voltage directly related to driving of the liquid crystal, the DC potential in the display device is further stabilized and increased in accuracy. IC
1 and the VSL, a capacitor C2 for stabilizing the power supply is inserted.
The voltage dividing resistors R1 and R2 are connected in series between the output 1 and VSL. Each resistance value is 15K ohm, and the resistance value accuracy is ± 0.5%, which is an extremely accurate resistance. The output of the DC intermediate power supply VM is taken out from the connection point of the series connection resistances R1 and R2 connected as the voltage dividing resistance, and the power supply of the potential between VM and VSL is obtained. At this time, a capacitor C162 for stabilizing the power supply is connected between VM and VSL. Since the DC intermediate potential VM obtained in this manner is a voltage directly related to driving of the liquid crystal, it is required to further stabilize and improve the DC potential in the display device. There is a need. As described above, since the VM is set with high accuracy and a more stable power supply can be taken out, the fluctuation of the display image is suppressed and the display quality is improved.

FIG. 6 which is an example circuit of the first power supply circuit 150 in the system block diagram 4 will be described. The center of the configuration of the first power supply circuit is a DC-DC power supply (DC
−CD regulator), and an IC having better controllability than the second power supply circuit was used. DC low potential V for IC2
SL and DC high potential VDL are input, switching is performed by IC2 and transistor Q1, and transistor Q1
A DC output power supply whose voltage is accurately adjusted by a choke coil (inductance) connected to the collector is output to the circuit of the next stage. Transistor Q1
Is rectified by the diode D1 and the pulse amplifier 25
0 is supplied together with VSL. The diode D1 has a function of preventing a reverse potential due to a capacitor load. A capacitor C6 is connected to the cathode side of D1 for suppressing power supply fluctuation. Since the first power supply circuit is also a source of a power supply directly related to the liquid crystal driving as described in the above VM, the DC potential in the display device is further stabilized and highly accurate. Since the circuit is easily affected by fluctuations and is the main power supply of the oscillating power supplies VDD and VSS, a circuit having higher voltage control performance than the second power supply circuit and a circuit having less loss and requiring a large amount of current are used. An optimal power source can be obtained as a power source.

A description will be given of FIG. 7 which is an embodiment circuit of the prescribed pulse shaping circuit 230 in FIG. 4 which is a system block diagram. The output signal Q of the D-type flip-flop IC5 clocked by a LOAD (for example, a clock signal of about 24 KHz based on a horizontal scanning signal of a video signal)
Is similarly input to the J input of a JK flip-flop using the LOAD signal as a clock (CKLOAD), and an AC pulse signal used for a swing power supply is obtained from the output signal Q2 (output C).

A description will be given of FIG. 8 which is an embodiment circuit of the pulse amplification circuit 250 in the system block diagram 4. The potential of the first power supply circuit 150 via the diode D1 and the potential of VSL are used as power supplies, and the input C is pulse-amplified using the output C which is the 2Q signal of the prescribed pulse shaping circuit 230 as an input. The pulse amplifier circuit 250 includes a P-type field effect transistor Q2 and an N-type bipolar transistor Q3.
In the push-pull circuit configuration. The gate of Q2 is connected to 2 of IC6 through a capacitor C8 and a resistor R11.
When connected to Q, a pulse signal is input. The capacitor C8 has a small capacitance of 0.01 microfarad, and is set corresponding to the frequency of the input pulse waveform. The resistor R10 and the diode D1 are for discharging the charge of the capacitor C8 and for biasing the gate of Q2. The base of Q3 is connected to the IC6 through a resistor R9.
2Q, a pulse signal is input.
Since the phases input to Q2 and Q3 are the same, Q2 and Q3 operate alternately, and approximately VDL-VS output from IC6.
The pulse signal of the potential between L is amplified to a pulse waveform of the potential from the first power supply, and the output D is output to the next level clamp circuit 270.

FIG. 9 which is an embodiment circuit of the level clamp circuit 270 in the system block diagram 4 will be described.
A pulse signal (potential is set between about 10-30 V) where the output D of the pulse amplifier 250 is received as the input D is received by three capacitors C9, C10, and C11. The pulse signal received by the capacitor C9 is a diode D connected to the subsequent stage of the capacitor.
31 and a capacitor C9 to generate a swing high power supply VDD. The other terminal of the diode D31 is connected to the DC power supply VD2, which is the output of the second power supply circuit 170 described above. Therefore, the potential of VDD is the forward bias potential of VDL and the diode (for example,
0.6V). The pulse signal received by the capacitor C10 is level-clamped by the diode D32 and the capacitor C10 connected to the subsequent stage of the capacitor, and generates the oscillating low power supply VSS. The other terminal of the diode D32 is connected to the DC low potential VSL (ground) described above. Therefore, the potential of VSS becomes the forward bias potential of VSL and the diode (for example,
0.6V). The pulse signal received by the capacitor C11 is composed of a P-type field effect transistor Q4 connected to the latter stage of the capacitor and the capacitor C11.
To generate a swing low power supply VCC. The source terminal of Q4 is connected to DC high potential VDL. The drain terminal of Q4 is connected to the capacitor C11 described above. The gate terminal of Q4 is connected to the output 2Q of the prescribed pulse shaping circuit 230 by a 10K ohm resistor R1.
1 are connected. Input C which is the gate terminal of Q4
Is the output C which is the output 2Q of the prescribed pulse shaping circuit 230.
Is input via a 10K ohm resistor R11. This operation will be briefly described.
4 is turned on, the level clamp voltage becomes VDL and is clamped at a potential of approximately VDL. On the other hand, when Q4 is turned off by the prescribed pulse output signal, the voltage is reduced to a potential on the lower potential side of the output of the pulse amplifier 250. Get dumped.
In this way, the VCC potential level-clamped by the transistor Q4 has the potential of VDL on the high potential side, and has the potential on the low potential side of the waveform after the output of the pulse amplifier 250 has passed through the capacitor on the low potential side. The oscillating power supply VCC having such a potential is provided.

As another usage, in the above embodiment, three types of VDD, VSS, and VCC were used as the swing power source.
If the capacitor and the diode or the transistor and the clamp power supply are set as required, the number of the oscillating power supplies can be increased or decreased, and the required oscillating power supply can be appropriately selected and designed. In the present invention, a diode clamp circuit is used to generate VDD and VSS of a high power supply and a low power supply for driving a liquid crystal, and a transistor is used to generate an intermediate power supply for the drive signal processing circuit 603a. To explain the reason, if level clamping is performed using a diode, the diode is connected so that current flows from the VCC line to the VDL line. On the other hand, when a reverse potential is applied to the diode, no current flows from the VDL side to the capacitor C11 via the diode. Then, although level clamping can be performed, it is difficult to supply the current to the VCC line. There is a problem that the VCC power supply current cannot be supplied to the subsequent circuit. In order to solve this problem, the transistor Q4 is used to supply the insufficient current from the transistor Q4. This means that even when the output 2Q of the IC 6 is at the potential H level, the transistor Q4 is turned on with the set on resistance. The diode has a forward potential of approximately 0.6 V, and the potential varies due to a flowing current and manufacturing variations between product lots.
On the other hand, in the transistor (Q4), the potential corresponding to the potential of the diode on the circuit has a large difference of 0.1 to 0.2V. Therefore, a clamp circuit is formed using a transistor in the drive signal processing circuit.

FIG. 10 is a diagram showing blocks after the first level shifter (level shift circuit) in FIG. FIG. 10 is a configuration diagram showing the configuration after the first level shifter in FIG. 4 in more detail than FIG. FIG. 10 shows a relationship between the signal and the oscillating power supply by describing a part of a logic signal (a clock related to a display drive signal, a selection signal, and the like). An embodiment will be described with reference to FIG. The liquid crystal drive timing signal DF (hereinafter, DF)
1) is input as an example, and FIG.
The function of each unit at 0 will be described. For example, 1
The DF, which is a 5 KHz pulse signal and has a clock signal function, is input to one input terminal of the first level shifter 510. The other input terminal of the first level shifter is connected to V
It is connected to SL (ground). The first level shifter is supplied with VDL as a high-potential power supply and a swing low power supply VSS as a low-potential power supply. Due to the first level shifter, the potential of the DF signal on the high potential side is VDL,
The level on the low potential side is shifted to a pulse signal of VSS. Q12 of output signal of first level shifter 510
Is input to the signal input terminal IN21 of the second level shifter 550. Similarly, Q11 of the output signal of the first level shifter 510 is equal to the signal input terminal IN of the second level shifter 550.
21. Next, the second level shifter 550 includes:
A swinging power supply VCC is supplied as a high-potential power supply, and VSS is supplied as a low-potential power supply. Second level shifter 55
0 indicates that the high potential of the DF signal is VCC and the low potential is VSS. As described above, the DF signal is supplied from the second-stage shifter 550 to the subsequent inverter 58.
The signal is converted into a pulse having an optimum potential as a 0 input signal. Then, the second level shifter 5 is connected to the inverter 580.
50 outputs Q21 are input. The above description and FIG.
As shown in (1), each circuit part (circuit block) is connected.

The DF signal, which is a signal level-shifted to a signal having the potential of the oscillating power supply and the oscillating low power supply, which are the logic power supplies in the scan electrode driving circuit IC 105, is output from the output circuit 6.
The signal is sent to a logic circuit located on the previous stage side of 70. On the other hand, in the case of the other clock signal,
With a circuit configuration basically similar to the description using the signal as an example, the level is shifted to a signal having the potential of the oscillating power supply VCC and the oscillating low power supply VSS that are the logic power supplies in the scan electrode driving circuit IC105. Formed into a clock signal. V
The clock signal shaped into a pulse waveform having a potential of CC and VSS is input to a drive signal processing circuit 603 which is a logic circuit block. The LV signal, which is a signal formed by the drive signal processing circuit, enters the third level shifter 610.

L which is a pulse waveform having a potential of VCC and VSS which is an output of the drive signal processing circuit 603.
The V signal is input to the third level shifter 610, and the swing high power supply VDD and the swing low power supply VSS are supplied to the third level shifter 610. The LV signal is level-shifted by the third level shifter 610 to a VIN signal having a pulse waveform having the potentials of VDD and VSS. After passing through the inverters 671 and 672, the VIN signal is supplied to the gate of the N-type field effect transistor 680 which controls whether or not to supply the DC intermediate potential VM to the display pixel, and further to the display pixel. The signal is supplied to one terminal of a NOR circuit 674 having two inputs for transmitting a signal to an N-type electric field transistor 675 constituting a push-pull output circuit for supplying a potential of VSS. NOR circuit 67 having two inputs
The other terminal of 4 is supplied with a level-shifted DF signal. On the other hand, the VIN signal is output from the inverters 671, 67
2, 673, that is, by adding and further adding a one-stage inverter to the above-mentioned contents, the DC intermediate potential VM
Is supplied to the gate of a P-type field effect transistor 679 which controls whether or not to supply the pixel to the display pixel, and a signal is supplied to a P-type field transistor 675 which constitutes a push-pull output circuit for supplying VDD potential to the display pixel. Is supplied to one terminal of an AND circuit 674 having two inputs. The level-shifted DF signal is supplied to the other input terminal of the AND circuit 674. The N-type field effect transistor 680 is connected in parallel to the P-type field effect transistor 679. P-type electric field transistor 675 on the high potential side of the push-pull output circuit for driving liquid crystal
Is connected to the oscillating high power supply VDD,
The source terminal of the N-type electric field transistor 678 on the low potential side of the push-pull output circuit for driving the liquid crystal is connected to the oscillating low power supply VS.
Connected to S. P constituting the push-pull output circuit
The drain of the N-type electric field transistor 675 is connected to the drain of the N-type electric field transistor 678 on the low voltage side.
Further, a connection point between the drain of the P-type electric field transistor 675 constituting the push-pull output circuit and the drain of the N-type electric field transistor 678 on the lower potential side is connected in parallel with each other to control the supply of VM. 6
The connection point where the source terminal of the P-type field transistor 679 is connected to the source terminal of the P-type electric field transistor 679 is connected. N connected in parallel
A connection point between the drain of the p-type electric field transistor 680 and the drain of the p-type electric field transistor 679 is connected to the DC intermediate power supply VM.

The drain of the high-potential-side P-type field transistor 675, which is a push-pull output circuit in the scan electrode driving circuit 105 (FIG. 1), and the low-potential-side N-type field transistor 6
A connection point to which the drain 78 is connected is connected to at least one of the scanning electrodes (not shown) constituting the display pixel.

On the other hand, the signal electrode drive circuit 106 also has an output circuit which forms a push-pull configuration with the drive logic circuit. The drain of the high potential side P-type field transistor 901 which is a push-pull output circuit and the low potential side N-type A connection point to which the drain of the electric field transistor 902 is connected is at least one of a signal electrode side electrode (not shown) constituting a display pixel.
Connected to two electrodes. Push-pull output circuit P on signal side
The source terminal of the N-type electric field transistor 901 is connected to the DC high power supply VD2 for the signal electrode, and the source terminal of the N-type electric field transistor 902 on the low potential side is connected to the DC low power supply VSL for the signal electrode.

From the above-mentioned push-pull output circuit incorporated in the scan electrode drive circuit 105, a pulse signal having three potentials of VDD, VM and VSS is output and applied to the scan electrodes. Further, a pulse signal having three potentials VD2, VM, and VSL is output from the push-pull output circuit incorporated in the signal electrode drive circuit 106, and is applied to the signal electrode. Here, in this embodiment, an intermediate potential of a pulse waveform having a potential difference of VD2−VSL is used. Next, the output waveform and the drive waveform applied to the liquid crystal will be described with reference to FIG.

FIG. 11 shows a driving waveform when the liquid crystal is driven in FIG. FIG. 11 shows a scan electrode drive waveform COM in one scan applied to one scan electrode.
DD and a signal electrode drive waveform SGD applied to the signal electrode
D, a scan electrode driving waveform COMDD, a liquid crystal driving waveform LCDD applied to the liquid crystal, a oscillating waveform of the oscillating high power supply VDD, and an oscillating waveform of the oscillating low power supply VSS. It shows the relationship. COMDD in the AA period shown in FIG. 11 is selected during a certain period and is selected during the tDU period within the high potential period of the oscillating high potential.
DD becomes a DC low potential VSL, and COMDD and SG
The liquid crystal driving waveform LCDD obtained by combining the DD is applied to the liquid crystal during the tDU period. COMDD in AB period of FIG.
Is selected for a certain period and is selected in a period tDD within the period of the low potential of the oscillating low potential VSS, and in the same period tDD, SGDD
Becomes DC high potential VD2, and COMDD and SGDD
Is applied to the liquid crystal during the tDD period. When the oscillating power supply is used in this manner, the maximum potential difference in the period AA is VDDmax−VSLmax.
= 18V (Example), while the maximum (m) in the period AB
ax) The potential difference is VDDmin−VSSmin = −18
V, the withstand voltage of the IC of the scan electrode driving circuit 105 is good at 18 V, which is the same as the conventional VDDmax +
A withstand voltage of approximately half of VSSmin = 36V may be used. The potential applied to the liquid crystal is VDDmax during the selection period tDU.
+ VSL, and VSSmi during the selection period tDD.
n + VD2. As described above, in the present invention, the withstand voltage of the scan electrode driving circuit is reduced to approximately half. Therefore, generally, when the withstand voltage is increased, the size of the transistor is increased and the degree of integration is reduced, and the degree of integration is reduced. As a result, the problem of disadvantageous cost and the problem that the power consumption is increased when the power supply voltage is high because the power consumption is proportional to the square of the power supply voltage in the circuit constituted by the complementary MOSs are improved. In recent years, those skilled in the art are competing for techniques for increasing the degree of integration of integrated circuits, so that the degree of integration is extremely advanced, and the number of production facilities and devices for producing low-integration ICs is extremely small. Driving a liquid crystal using an integrated circuit has an effect of reducing costs from such a viewpoint.

Returning to the description of FIG. 10, the scan electrode driving IC
In FIG. 105 (FIG. 1), in addition to the DF signal, a LOAD signal which is a source of a clock signal and a RE signal which is a reset signal are provided.
An ST signal or the like is input. For example, a REST signal is a level shifter 501 and a LOAD signal is a level shifter 502.
Then, the level is shifted as described in the description of the DF signal. After the LOAD signal is level-shifted, the logic signal is shaped into a clock signal CLOCK used in the drive circuit 600 by the logic circuit 503, and the logic signal is input to the inverter 580.
Is input to the drive circuit 600 via an inverter corresponding to. The function of transmitting the signal output of the second level shifter 550 to the drive circuit 600 having a logic circuit in the input stage in an optimum state by connecting the inverter 580 is provided. The driving circuit 600 includes a second driving circuit 602 including a plurality of integrated circuits each including a driving data processing circuit 603 and a driving output circuit 604, and a first driving circuit including a plurality of second driving circuits 602.
The driving circuit 601 and the first driving circuit 601 are provided with a plurality of circuits. Drive circuit 600, drive data processing circuit 6
03, the drive output circuit 604, the second drive circuit 602, the first
How the drive circuit 601 and the like are divided into blocks, and how many of the same circuits are formed into blocks having circuits may be appropriately selected in product specifications. Further, in the embodiment of the present invention, as shown in FIG.
Although the number of ICs used is one, the number of ICs to be used or the number of ICs to be used may be appropriately selected depending on the pixel density of the liquid crystal panel, the input terminal density of the liquid crystal panel, and the like. Further, although two-stage inverters 671 and 672 are connected to the output of the second level shifter 550, these inverters may be provided in one stage. In this case, however, the logic is inverted. Wiring must be changed to make the logic of the field effect transistor for VM control appropriate. Furthermore, two-stage inverters 671, 6
Although 72 can be omitted, it is preferable to include one inverter (for example, 671) as described above in consideration of the consistency between the second level shifter and the NOR circuit of the logic circuit.

FIG. 12 shows the first level shifter 510 and the second level shifter 55 at the next stage in the system block diagram 4.
11 is a circuit diagram of an embodiment of the inverter 580 in FIG.

First, the circuit portion of the first level shifter 510 will be described with reference to FIG. The gate is connected to the signal input means 530 and the power supply 51 which is a DC high power supply VDL is connected.
A MOS transistor 515 having a source connected to the power supply 1 and a back gate connected to a power supply 511 having a high DC potential.
The MOS transistor 51 having a gate connected to the power supply 512 which is a DC low potential VSL, a source connected to the signal input means 530, and a back gate connected to the power supply 511.
6. A MOS transistor 517 having a drain connected to the drain of the MOS transistor 515, a gate connected to the power supply 511, and a back gate connected to a power supply 514 which is a swing low power supply VSS. MOS transistor 5
A MOS transistor 518 having a drain connected to 16 drains, a gate connected to the power supply 511, and a back gate connected to the power supply 514. MOS transistor 517
Having a drain connected to the source of the
A MOS transistor 519 connected to the drain of the transistor 516 and having a source and a back gate connected to the power supply 514; MOS transistor 518 has a drain connected to the source, and has a gate connected to MOS transistor 515.
And the source and back gate are connected to the power supply 5
14 and a MOS transistor 520. The output of the first level shifter includes a signal 540 obtained from the drain of the MOS transistor 515 and a signal 545 obtained from the drain of the MOS transistor 516, and both of them enter the second level shifter 550.

The circuit configuration of the second level shifter 550 is shown in FIG.
2 will be described. Gate is the first level shifter 510
The power supply 51 connected to the drain of the MOS transistor 515 of which the source and the back gate are the oscillating low power supply VSS.
4 is connected to the MOS transistor 558 and the drain is MO.
A MOS transistor 556 connected to the drain of the S transistor 558 and having a source and a back gate connected to a power supply 551 which is a swinging power supply VCC. A MOS transistor 559 having a gate connected to the drain of the MOS transistor 516 of the first level shifter 510, and a source and a back gate connected to the power supply 514. A MOS transistor 557 having a drain connected to the drain of the MOS transistor 559 and a source and a back gate connected to a power supply 551 which is a swinging power supply VCC. Further, the gate of the MOS transistor 556 is connected to the drain of the MOS transistor 559, and the gate of the MOS transistor 557 is
Connected to the drain of OS transistor 558. Second
The output of the level shifter is a signal 555 obtained from the drain of the MOS transistor 559, and is input to a subsequent inverter.

The inverter circuit connected to the second stage of the second level shifter 550 will be described with reference to FIG. The gate is the MOS transistor 55 of the second level shifter 550
A MOS transistor 582 connected to the drain of the power supply circuit 9 and having a source and a back gate connected to a power supply 514 which is a swing low power supply VSS. The gate is the MOS of the second level shifter 550
The MOS transistor 581 is connected to the drain of the transistor 559, the source and the back gate are connected to the power supply 551 which is the swinging power supply VCC, and the drain is connected to the drain of the MOS transistor 582.

The operation of the circuit shown in FIG. 12 will be described. As an example, the DF signal is composed of a pulse signal having a potential of VDL and a potential of VSL, and this pulse signal is input means 530
Will be described. Hereinafter, MOS transistor is abbreviated as MOS, P-type MOS transistor is referred to as PMOS, and N-type MOS transistor is referred to as NMOS. First, the operation when the input potential of the input means 530 is VDL will be described. Input means 53 of first level shifter 510
When the input potential of 0 is VDL (high potential), the PMOS 51
5 turns off and the PMOS 516 turns on. Then N
VDL is applied to the gate of the MOS 519 and the NMOS 5
19 turns on. On the other hand, VDL is applied to the gate of the NMOS 517, and the NMOS 517 has a certain resistance, and
517 is on. This NMOS 517 is a PM
It has an effect of suppressing a through current when the OS 515 and the NMOS 519 are switched on and off. In addition, NM
Since the gate potential of the OS 520 becomes a low potential of approximately VSS, the NMOS 520 is turned off. As a result, signal 540
Becomes low potential, and the signal 545 becomes high potential. N of the second level shifter 550 that has received the signal 540 having a low potential
The MOS 558 is turned off, and the gate potential of the PMOS 557 is set to a high potential to turn off the PMOS 557. on the other hand,
Second level shifter 5 receiving signal 545 attained high potential
The NMOS 559 of 50 is turned on, the gate potential of the PMOS 556 is set to a low potential, and the PMOS 556 is turned on. The low potential output of the drain of this NOMS 559 is
This signal is supplied as a signal 555 to the next-stage inverter. Since the signal 555 related to the gate is at a low potential,
The MOS 582 is turned off, the PMOS 581 is turned on, and the inverter output signal 583 outputs a high potential VCC.

Next, the input potential of the input means 530 becomes VSL
The operation will be described in the case of. When VSL (low potential) is input to the input means 530, the PMOS 515 turns on and the PMO
S516 is turned off. Then, VDL is applied to the gate of the NMOS 520, and the NMOS 520 is turned on.
Then, on the other hand, VDL is applied to the gate of the NMOS 518, and the NMOS 518 is turned on with a certain resistance. This NMOS 518 has a function of suppressing a through current when the PMOS 516 and the NMOS 520 are switched on and off. This NMOS 517 and NM
PMOS 518 and NMOS due to the on-resistance of OS 518
519, and turning on the PMOS 516 and the NMOS 520.
Through current at the time of switching off is suppressed, current consumption is reduced, and breakdown due to heat generation of the transistor is prevented.
Further, since the gate potential of the NMOS 519 becomes a low potential of approximately VSS, the NMOS 519 is turned off. As a result, the signal 545 has a low potential and the signal 540 has a high potential. The NMOS 558 of the second level shifter 550 that has received the signal 540 that has become high potential is turned on, and the PMOS 5
The PMOS 557 is turned on by setting the gate potential of 57 to a low potential. On the other hand, the second signal 545 receiving the low potential signal
The NMOS 559 of the level shifter 550 is turned off, and P
The gate potential of the MOS 556 is set to a high
Turn 6 off. The high-potential output of the drain of the NOMS 559 is supplied as a signal 555 to the next-stage inverter. The inverter generates a signal 555 applied to the gate.
Is high potential, the NMOS 582 is turned on and the PMO
S581 is turned off, and the signal 583 of the inverter output becomes the low potential VSS.

The third level shifter will be described with reference to FIG. 13 which is a circuit diagram of an embodiment of the third level shifter 610 in the system block diagram 4. The gate is connected to the input means 630 of the signal, and the source is
The PMOS transistor 615 connected to the power supply 611 which is a DD, the back gate is also connected to the power supply 611, the gate is connected to the input means 631 of the signal, the source is connected to the power supply 611, and the back gate is also connected to the power supply 611. The PMOS transistor 616 has a drain connected to the drain of the PMOS transistor 615, the back gate has a PMOS transistor 617 connected to the power supply 611, and the drain connected to the drain of the PMOS transistor 616. 611
And a drain connected to the source of the PMOS transistor 617 and the gate of the PMOS transistor 618, the gate is connected to the signal input means 630, and the source and the back gate are connected to the power supply 614. NMOS transistor 619, P
It has a drain connected to the source of the MOS transistor 618 and the gate of the PMOS transistor 617. The gate is connected to the input means 631 for the signal. The source and the back gate are connected to the power supply 614. The output of the third level shifter is NMO
The signal 640 is output from the drain of the S transistor 620.

The operation of the third level shifter will be described. First, as the input potential of the input means 630, the power supply during oscillation VCC
The operation when the high potential side of the power supply VCC is input and the low potential side of the oscillating power supply VCC is input as the input potential of the input means 631 will be described. When a signal is input to each of the input means as described above, a high potential side input of the input means 630 causes the NMOS
619 turns on. In addition, due to the high potential side input of the input means 630, the PMOS 615 is turned on with a certain resistance because the gate potential is VCC and lower than the source potential VDD. On the other hand, due to the low potential side input of the input means 631, the PMOS 616 has a certain resistance value and is on, and the NMOS 620 is off. When the NMOS 619 is turned on, a low potential is applied to the gate of the PMOS 618, the PMOS 618 is turned on, the drain of the PMOS 618 becomes high, the PMOS 617 is turned off, and a high potential of VDD is output as the signal 640. Due to the on-resistance of the PMOS 615 and the PMOS 616, P
The through current at the time of switching on / off of the MOS 617 and the NMOS 619 and the PMOS 618 and the NMOS 620 is suppressed, the consumption current is reduced, and destruction due to heat generation of the transistor is prevented.

Next, an operation in which the input potential of the input means 630 is inputted to the low potential side of the power supply VCC while fluctuating, and the input potential of the input means 631 is inputted to the high potential side of the power supply VCC while fluctuating will be described. When a signal is input to each input means as described above, the low potential side input of the input means 630 causes P
The MOS 615 has a certain resistance value and is turned on.
S619 is turned off. On the other hand, due to the high potential side input of the input means 631, the PMOS 616 is turned on with a certain resistance value, and the NMOS 620 is turned on. NMOS 62
When 0 is turned on, a low potential is applied to the gate of the PMOS 617, and the PMOS 617 is turned on.
The drain of the drain 87 becomes high potential, turning off the PMOS 618 and outputting a low potential of VSS as the signal 640. Thus, the level shift can be easily performed by using the circuit of the present invention.

Although the features of the present invention have been described with reference to a liquid crystal display device, the present invention can be applied to a liquid crystal printer device using a liquid crystal shutter, and substantially the same effects as those of the present invention described below can be obtained. Further, although the features of the present invention have been described with respect to the liquid crystal display device, the present invention can be applied to a display device using an organic EL (electroluminescence), and substantially the same effects as those of the present invention described below can be obtained. As described above, the present invention is an excellent invention which is widely applicable to display devices and printers using liquid crystals and EL elements.

[0070]

According to the present invention, downsizing is further advanced,
The display area of the liquid crystal display device can be enlarged within a limited area, the peripheral area of the display area can be narrowed, and an IC, which is an integrated circuit, is mounted on the substrate in an IC chip state in the peripheral area ( Hereinafter, referred to as COG)
Since the IC becomes smaller, the peripheral area can be particularly narrowed. Furthermore, because the IC can be made smaller, COG
Also, TAB (tape automatic bonding) and TCP (tape carrier package) of a mounting method similar to that of the above can be reduced in size, and the peripheral area can be narrowed.
Since the withstand voltage of the IC (integrated circuit) could be reduced, the slimness and miniaturization of the IC were obtained.

In the conventionally used method, the potential is changed during the AC driving operation, and the scanning electrode driving device operates with V1 and V1.
2. Output in combination of V3 and V4. At that time, the signal electrode driving device also outputs in combination of V5 and V4 and V1 and V6. Therefore, both the scan electrode driving device and the signal electrode driving device require a withstand voltage not less than the potential difference of V1-V4, and thus require a high withstand voltage electrode driving device. Although a withstand voltage integrated circuit was required, according to the present invention, it is not necessary to configure the signal electrode driving device with a high withstand voltage element. There is an effect that it is possible to cope with a high-speed operation of the signal electrode driving device due to an increase in the number of data signals accompanying the operation. In addition, with regard to power consumption, high-speed operation at a high voltage is not required, and there is an effect that low power consumption can be obtained.

In the prior art, the H level of VDD and VSS
L level appears at the same time, the potential difference between VDD and VSS increases, and an IC with a high breakdown voltage must be manufactured.
Although there were problems such as an increase in the outer shape of C and an increase in current consumption, the present invention as described above, that is, because the phase of the VDD pulse power supply and the phase of the VSS pulse power supply are matched, VDDmax It is sufficient to manufacture an IC that can withstand the potential difference between the voltage and VSSmax, and a great improvement can be obtained by using the swing power supply of the present invention. Without increasing the withstand voltage of the scan electrode driver, it is possible to greatly reduce the withstand voltage of the signal electrode driver.
Higher density and lower power consumption are now possible.

According to the present invention, the oscillating power supplies VDD, VSS, and VCC output from the level clamp circuit are connected to the subsequent stages.
By supplying the signal to the first level shifter, the second level shifter, and the third level shifter, it is possible to generate a signal potential at which the circuit operation of the output circuit is optimally started, and supply the signal potential to the output circuit configured by the push-pull circuit. By doing so, optimal operation (optimal operation is, for example, complete turn-on and turn-off of a transistor constituting a push-pull circuit) becomes possible, and unnecessary power consumption loss in the transistor can be reduced. And the reliability is also improved. In this way, by combining the swing power supply with the level shifter and using the output circuit having the swing power supply function, the function of the swing power supply can be maximized with a simple configuration. This has the effect that a good display image can be obtained.

In the present invention, a diode clamp circuit is used to generate a high power supply and a low power supply VDD and VSS for driving, and a transistor is used to generate an intermediate power supply VCC for a drive signal processing circuit. If a diode is used to make a level clamp to create a VCC power supply, the diode will be connected so that current will flow from the VCC line to the VDL line. It is difficult to supply a sufficient VCC power supply current to a subsequent circuit. However, an insufficient current is supplied from a transistor to solve the problem. The diode has a forward potential of approximately 0.6 V, and the potential varies due to a flowing current and manufacturing variations between product lots. On the other hand, in the transistor, the potential corresponding to the potential of this diode on the circuit is 0.1-0.
It has a great difference from 2V. Therefore, by forming a clamp circuit using a transistor in the drive signal processing circuit, there is an effect that variation in production is suppressed, yield is improved, and power loss due to elements is reduced. According to the present invention, a diode clamp circuit is used to generate VDD and VSS of the oscillating high power supply and the oscillating low power supply for driving the display element, and transistors are used to generate the oscillating power supply for the drive signal processing circuit. The use of the distinguished circuit has the effect of preventing fluctuations due to current flowing through the forward potential of the diode and manufacturing variations in the forward potential between lots. On the other hand, the oscillating high power supply and the middle power supply, which are also used to drive the display element that is driven, are diodes with low component costs, so if the chip area is the same, there are more transistors than components with higher component costs than diodes. It has the effect of obtaining a current, and has the effect of achieving efficient circuit operation, product cost reduction and proper price by optimizing the type of semiconductor element according to the load.

The driving potential difference applied to the display element is the same as the conventional one, but the time-based operating voltage of the display element electrode driving circuit or the output circuit is half of the conventional voltage, so that the withstand voltage of the electrode driving circuit is almost half. When the breakdown voltage is increased, the size of the transistor is increased and the degree of integration is reduced, the reduction in the degree of integration is disadvantageous in terms of cost, and the complementary MOS is used. In a circuit, the problem that the power consumption increases in proportion to the square of the power supply voltage when the power supply voltage is high is improved by the present invention in which a desired drive can be obtained with a low voltage power supply. In recent years, those skilled in the art are competing for techniques for increasing the degree of integration of integrated circuits, so that the degree of integration is extremely advanced, and the number of production facilities and devices for producing low-integration ICs is extremely small. Driving a liquid crystal using an integrated circuit has an effect of reducing costs from such a viewpoint. As described above, according to the present invention, a display device that is small, thin, lightweight, and consumes low current can be obtained.

The use of the switching power supply as the source power supply of the oscillating power supply provides a power supply that can respond to the switching operation, and has the effect of providing an oscillating power supply with good efficiency and quick response.

Since the prescribed pulse shaping device is a frequency dividing circuit composed of transistors, an oscillating power source whose frequency is lowered from the scanning signal can be set arbitrarily and freely. Image display quality is improved, and cost can be reduced by reducing design man-hours.

The pulse amplifier comprises a first transistor and a second transistor, wherein the source of the first transistor is connected to the first power supply, the drain is connected to the second transistor, and the second transistor is connected to the second transistor. By connecting the circuit with the emitter connected to a low DC power supply, a complementary switch circuit is formed and one of the transistors is turned off first, the through current flowing between both transistors is suppressed, power dissipation is reduced, and the transistor due to heat It has the effect of preventing destruction. Further, since the on-resistance of the transistor connected to the high power supply and the transistor connected to the low power supply side are low, a power supply having a low output resistance can be obtained, and a drive current to the liquid crystal can be efficiently supplied. Has an effect.

At least a first level shifter and a second level shifter are provided between the wiring of the scanning electrode output device for driving the scanning electrode and the wiring from the oscillation power supply generating device for generating the power of the oscillation power supply.
And the third level shifter and the output circuit, and the above-described serially connected configuration is accommodated in one integrated circuit, so that the swing power supply wiring is concentrated in the integrated circuit. It is effective in minimizing the size and minimizing the radiation of noise from the voltage swing power supply wiring.

A first level shifter, a second level shifter, a first inverter, a drive signal processing circuit, a third level shifter, and an output circuit in which a plurality of other inverters are connected to an input stage are provided and connected in the order described above. With such a configuration, the electrodes can be driven with optimal signal transmission, so that the drive signal transmission efficiency is good, and there is an effect that noise is also strong. In particular, since an inverter is connected between the level shifter 2 and the drive signal processing circuit to separate the level shifter and the drive signal processing circuit, the level shifter is not affected by the subsequent drive signal processing circuit and has high reliability. There is an effect that signal transmission can be performed.

At least a first level shifter, a second level shifter, a first inverter and a drive are provided between a swing power supply generating device for generating the power of the swing power supply and a scan electrode output device for driving the scan electrode. A signal processing circuit, a third level shifter, and an output circuit in which a plurality of other inverters are connected to an input stage and a configuration in which the inverters are connected in the above-described order make it possible to appropriately perform a transmission potential and perform a subsequent operation in a preceding stage. Since the influence on the electrode is reduced, the signal is optimally transmitted, and the electrode is driven.

A third NMOS transistor having a drain connected to the drain of the first PMOS transistor, a gate connected to the high DC power supply, and a back gate connected to the oscillating low power supply; 2nd PM
By connecting to a fourth NMOS transistor having a drain connected to the drain of the OS transistor 516, a gate connected to the DC high power supply, and a back gate connected to the DC low power supply, an input signal is not input. Since the transistor is controlled by the potential relationship between the source and the drain of the NMOS transistor with respect to the high DC power supply applied to the gate, the load on the circuits in all stages can be reduced, and the operation can be performed with high reliability and high resistance to noise. .

The use of the second level shifter has an effect that a signal between VDL and VSS can be converted into a signal of a potential difference between VCC and VSS with low current consumption. Also, by converting to a low-amplitude signal using a logic circuit power supply, low-voltage operation of the subsequent logic circuit can be performed with the signal as it is, and low power consumption of the logic circuit is obtained. This has the effect that a small size can be easily obtained.

Since the inverter circuit is connected to the next stage of the second level shifter, a signal without distortion can be sent to the subsequent logic circuit, which has the effect of preventing malfunction of the subsequent circuit.

By configuring and using the third level shifter, a low-amplitude signal between VCC and VSS can be supplied to VDD-VSS.
This has the effect of being able to convert to a signal of the potential difference between S. In this manner, the signal is converted into a potential, and is used as a signal of an output circuit that uses VDD-VSS at the subsequent stage as a power supply, so that the output transistor of the output circuit can efficiently supply sufficient output to the liquid crystal,
Further, since the supply can be maintained for a necessary period, the liquid crystal is optimally driven, and the display quality is improved.

In the output circuit configuration, control of whether to output VM power to the liquid crystal is performed by connecting at least the source of the twenty-first PMOS transistor and the source of the twenty-second NMOS transistor, and the source is the drain of the nineteenth PMOS. And the drain of a twentieth NMOS transistor is connected to the drain of a nineteenth PMOS transistor having a configuration in which the drain of the twenty-first NMOS transistor is connected to the drain of the twenty-second NMOS transistor. With the configuration connected to the power supply VM, VM power can be supplied to the liquid crystal with low output impedance, unnecessary current consumption can be reduced, and the liquid crystal can be efficiently driven.

The source of the nineteenth PMOS transistor on the high potential side is connected to the oscillating high power supply in the circuit at the final stage of the scan electrode output device for driving the liquid crystal. The source terminal of the twentieth NMOS transistor on the potential side is connected to the oscillating low power source, and the drain of the nineteenth PMOS transistor is connected to the twentieth NM transistor.
Connected to the drain of the OS transistor.
Drain of PMOS transistor and 20th NMOS
A source of a 22nd NMOS transistor and a source of a 21st PMOS transistor, which are connected in parallel and control the supply of VM, are connected to a connection point with the drain of the transistor. Is connected to at least one electrode, and the drain of the parallel-connected 22nd NMOS transistor is connected to the 21st PM
A connection point to which the OS transistor 6 is connected is connected to a DC intermediate power supply. Further, the gate of the twentieth NMOS transistor is connected to a two-input NOR circuit output, and one input terminal of the NOR circuit is connected to the first input terminal. The second input means is connected to the input means and the other input terminal is at least n.
(Positive integer) inverters, and the gate of the nineteenth PMOS transistor is a two-input NAND
One input terminal of the NAND circuit is connected to the first input means, and the other input terminal is connected to the second input means via at least n ± 1 (positive integer) inverters. With the above configuration, V to the liquid crystal
M power supply, VDD power supply to the liquid crystal, V
Any one of the SS power supplies can be freely selected, the power can be supplied to the liquid crystal, the liquid crystal driving waveform can be optimally formed, and the liquid crystal can be optimally driven, so that the display quality,
For example, it has the effects of improving luminance unevenness, improving contrast, improving crosstalk, and improving display flicker failure.

Although the features of the present invention have been described with reference to a liquid crystal display device, the present invention can be applied to a liquid crystal printer device using a liquid crystal shutter, and substantially the same effects as those of the present invention described below can be obtained. In addition, although the features of the present invention have been described with respect to the liquid crystal display device, the present invention can be applied to a display device using an organic EL (electroluminescence), and substantially the same effects as those of the present invention described below can be obtained. As described above, the present invention can provide the same effects as those of a liquid crystal which can be applied to a liquid crystal, a display device using an EL element, and a printer. .

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of the present invention, and is a system block mainly showing an oscillating power supply and a scanning side driving circuit connected to an output of the oscillating power supply and performing liquid crystal driving using the oscillating power supply. FIG.

FIG. 2 is a diagram illustrating a potential of a power supply swing method according to an embodiment of the present invention, and is a diagram illustrating an example of a voltage level of an input signal with respect to a potential of the power supply swing method.

FIG. 3 is a block diagram illustrating a configuration of a specific example of a driving circuit of the liquid crystal display device according to the present invention when the present invention is used in a liquid crystal display device.

FIG. 4 is a system block diagram showing a system block diagram in FIG. 1 in detail;

FIG. 6 is a circuit diagram of an embodiment of a second power supply circuit 170 in the system block diagram 4.

FIG. 6 is a circuit diagram of an embodiment of the first power supply circuit 150 in the system block diagram 4;

FIG. 8 is a circuit diagram of an embodiment of a prescribed pulse shaping circuit 230 in the system block diagram 4.

FIG. 9 is a circuit diagram of an embodiment of the pulse amplification circuit 250 in the system block diagram 4.

FIG. 9 is a circuit diagram of an embodiment of the level clamp circuit 270 in the system block diagram 4;

10 is a diagram showing blocks after the first level shifter (level shift circuit) in FIG. 1, and a configuration diagram showing the configuration after the first level shifter in FIG. 4 in more detail than FIG. 4; It is.

FIG. 11 shows a drive waveform when the liquid crystal is driven in FIG.

FIG. 12 is a diagram illustrating a first level shifter 510 and a second level shifter 550 in the next stage in the system block diagram 4;
6 is a circuit diagram of an embodiment of the inverter 580 in FIG. 5.

FIG. 13 is a circuit diagram of an embodiment of a third level shifter 610 in the system block diagram 4;

FIG. 14 is a block diagram showing a circuit configuration system according to the related art.

FIG. 15 is a diagram showing a conventional liquid crystal AC operation.
4 shows an output potential waveform of a scan electrode driver and an output potential waveform of a signal electrode driver.

FIG. 16 shows an oscillating power supply potential waveform showing the state of the power supply potential in the power supply oscillating method.

[Explanation of symbols]

REFERENCE SIGNS LIST 100 Drive device in display device 101 LCD controller 102 Oscillating power supply generation circuit 103 Primary processing circuit for input data signal 105 Scanning electrode drive circuit (IC) 106 Signal electrode drive circuit (IC) 150, 105a First power supply circuit (DC -DC converter:
DC-DC converter) 160, 161 Resistance 170 Second power supply circuit (DC-DC converter: DC-D)
C converter)) 230 prescribed pulse shaping circuit 250, 250a pulse amplifier 270 level clamp circuit 270a swing power supply circuit 500, 500a level shifter (circuit) 501, 502, 503 level shifter circuit 504 logic circuit 510 first level shifter (circuit) 550 second Level shifter (circuit) 580, 671, 672, 673 Inverter 600 Drive circuit 601 First drive circuit 602 Second drive circuit 603, 603a Drive signal processing circuit 604 Drive output circuit 610, 610a Third level shifter (circuit) 670, 670a Output circuit 674 AND circuit 675, 679, 901 P-type field effect transistor 676 NOR circuit 678, 680, 902 N-type field effect transistor 800a Liquid crystal panel 801 Liquid crystal element 900 Driving output Circuit 903 Drive logic circuit VDD High swing power supply (potential) inside scan electrode drive device VCC Power supply swinging inside scan electrode drive circuit (potential) VSS Low swing power supply (potential) inside scan electrode drive device VM DC intermediate potential VDL Indicates a DC high potential corresponding to the high level potential of the input signal of the external system, VSL a DC low potential corresponding to the low level potential of the input signal of the external system, or the ground potential in the external system. VD2 High potential for signal electrode DF Liquid crystal drive timing signal

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme court ゛ (Reference) G09G 3/20 622 G09G 3/20 622C (72) Inventor Nobuno Hagiwara 6-1, Honcho, Tanashi-shi, Tokyo No. 12 Citizen Watch Co., Ltd. Tanashi Factory (72) Inventor Shinichi Yamauchi 6-11-12 Honcho, Tanashi-shi, Tokyo F-term (reference) 2H093 NA43 NB11 NC03 NC05 NC09 NC11 ND32 ND39 ND42 ND43 5C006 AC24 AC26 AF51 AF69 AF78 BB12 BF06 BF26 BF34 BF43 FA47 5C080 AA10 BB05 DD26 EE25 FF12 GG02 JJ02 JJ03 JJ04

Claims (22)

[Claims] 1. A plurality of power supplies for generating a plurality of potentials, a plurality of drive signal processing devices for processing a signal for display driving using the power supply, and a signal electrode formed by signals from some of the drive signal processing devices. A liquid crystal drive including a signal electrode output device to be driven and a scan electrode output device for driving a scan electrode by a signal from another part of the drive signal processing device, and a matrix electrode including the signal electrode and the scan electrode In the device and its driving method, a part of the plurality of power supplies is a DC power supply having a substantially constant potential with respect to time, and the other part of the plurality of power supplies has a potential with time. The signal electrode is driven by processing the DC power supply into a signal electrode drive waveform by the signal electrode output device, and the scanning electrode is driven by the swing electrode. The scanning electrode is driven by processing a dynamic power supply and the DC power supply into a scanning electrode driving waveform by the scanning electrode output device, and at least one level shifter device is inserted in a preceding stage of the driving signal processing circuit. A liquid crystal driving device and a driving method thereof, wherein a signal obtained from a DC power supply is converted into a signal obtained from a swing power supply. 2. The oscillating power supply includes a specified pulse shaping device that generates a specified pulse, a first power supply device that generates a potential serving as a source of the oscillating power, and a first pulse forming device that receives a signal from the specified pulse shaping device. A pulse amplifying device for switching the power supplied from the power supply device to generate a pulse that is a source of the oscillating power supply, and a level clamp device, wherein an input of the pulse amplifying device is connected to an output of the prescribed pulse shaping device; 2. The liquid crystal driving device according to claim 1, wherein a power supply of the pulse amplification device is connected to the first power supply device, and an output of the pulse amplification device is connected to the level clamp device. . 3. The oscillating power source includes at least a oscillating high power source and an oscillating low power source supplied to the scan electrode output device, and at least a oscillating power source supplied to a level shifter device and a signal processing device. A liquid crystal driving device and a driving method thereof according to claim 2. 4. The liquid crystal driving device according to claim 2, wherein the first power supply device comprises a switching power supply device. 5. The liquid crystal driving device according to claim 2, wherein the prescribed pulse shaping device is an integrated circuit device constituted by a bipolar transistor. 6. The pulse amplifying device comprises a first transistor and a second transistor, a source or an emitter of the first transistor is connected to a first power supply device, and a drain or a collector of the first transistor is the same. 3. The liquid crystal of claim 2, wherein the liquid crystal is connected to a drain or collector of a second transistor, the source or emitter of the second transistor having a push-pull circuit connection connected to a second power supply. Driving device and driving method thereof. 7. The pulse amplifier according to claim 1, wherein the first transistor is a P-type field effect transistor, the second transistor is an NPN transistor, the first power supply is a DC high power supply, and the second power supply is a DC low power supply. 7. The liquid crystal driving device according to claim 6, wherein the driving device is a power supply. 8. The liquid crystal according to claim 2, wherein the level clamp device has a configuration in which a level clamp device including a capacitor and a diode and a level clamp device including a capacitor and a transistor are mixed. Driving device and driving method thereof. 9. The level clamp period of the transistor is controlled by connecting the output of the prescribed pulse shaping device to the gate or base of the transistor of the level clamp device comprising a capacitor and a transistor. And a driving method thereof. 10. The level clamp device has at least a first capacitor, a second capacitor, and a third capacitor, and one terminal of each of the capacitors is connected to an output of the pulse amplifying device. The other terminal of the first capacitor is connected to a first diode, the other terminal of the first diode is connected to a DC power supply for determining a level clamp potential, and the first capacitor and the first diode are connected. The output of the oscillating power supply is obtained from the connection portion. The other terminal of the second capacitor is connected to a second diode, and the other terminal of the second diode is a direct current that determines a level clamp potential. The output of the oscillating power supply is obtained from a connection portion connected to a power supply and to which the second capacitor and the second diode are connected. The other terminal of the third capacitor is connected to the drain or collector of the transistor, the source or drain of the transistor is connected to a DC power supply for determining a level clamp potential, and the output of the specified pulse shaping device is connected to the gate or base of the transistor. The liquid crystal driving device and the driving method thereof according to claim 8, wherein the liquid crystal driving device is connected to the liquid crystal device. 11. A plurality of power supplies for generating a plurality of potentials, a plurality of drive signal processing devices for processing a display drive signal using the power supply, and a signal electrode formed by signals from some of the drive signal processing devices. A liquid crystal drive comprising a signal electrode output device to be driven and a scan electrode output device for driving a scan electrode by a signal from another part of the drive signal processing device, and a matrix electrode composed of the signal electrode and the scan electrode In the device and its driving method, a part of the plurality of power supplies is a DC power supply having a substantially constant potential with respect to time, and the other part of the plurality of power supplies has a potential with time. An oscillating power source having a period that varies with respect to the oscillating power source, wherein the oscillating power source generates a specified pulse, a first power supply device that generates a potential serving as a source of the oscillating power source, and the specified pulse forming device. apparatus A pulse amplifying device that switches a power supply supplied from the first power supply device to generate a pulse which is a source of a swing power supply, a level clamp device including a capacitor and a diode, and a level including a capacitor and a transistor. A level clamping device having both a clamping device and an input of the pulse amplifying device connected to an output of a prescribed pulse shaping device; a power supply of the pulse amplifying device connected to the first power supply device; A liquid crystal driving device and a driving method thereof, wherein the output of (1) is connected to a level clamp device. 12. A plurality of power supplies for generating a plurality of potentials, a plurality of drive signal processing devices for processing a display drive signal using the power supply, and a signal electrode formed by signals from some of the drive signal processing devices. A liquid crystal drive including a signal electrode output device to be driven and a scan electrode output device for driving a scan electrode by a signal from another part of the drive signal processing device, and a matrix electrode including the signal electrode and the scan electrode In the device and its driving method, a part of the plurality of power supplies is a DC power supply having a substantially constant potential with respect to time, and the other part of the plurality of power supplies has a potential with time. An oscillating power source having a period that varies with respect to the oscillating power source, wherein the oscillating power source generates a specified pulse, a first power supply device that generates a potential that is a source of the oscillating power source, and the specified pulse forming device. apparatus A pulse amplifying device for switching a power supply supplied from the first power supply device to generate a pulse serving as a source of a swing power supply, a level clamp device including a capacitor and a diode, and a level clamp device including a capacitor and a transistor An input of the pulse amplifying device is connected to an output of the prescribed pulse shaping device, a power supply of the pulse amplifying device is connected to the first power supply device, and an output of the pulse amplifying device. Is connected to a level clamp device, and the level clamp period of the transistor is controlled by connecting the output of the prescribed pulse shaping device to the gate or base of the transistor of the level clamp device comprising a capacitor and a transistor. A liquid crystal driving device according to claim 8 and the liquid crystal driving device. Dynamic way. 13. A plurality of power supplies for generating a plurality of potentials, a plurality of drive signal processing devices for processing a display drive signal using the power supply, and a signal electrode formed by signals from some of the drive signal processing devices. A liquid crystal drive including a signal electrode output device to be driven and a scan electrode output device for driving a scan electrode by a signal from another part of the drive signal processing device, and a matrix electrode including the signal electrode and the scan electrode In the device and its driving method, a part of the plurality of power supplies is a DC power supply having a substantially constant potential with respect to time, and the other part of the plurality of power supplies has a potential with time. The signal electrode is driven by processing the DC power supply into a signal electrode drive waveform by an output device, and the scan electrode is connected to the oscillating power supply and the DC power supply. The scan electrode is driven by processing a power supply and a scan electrode driving waveform by an output device, and a wiring of a scan electrode output device that drives the scan electrode from an output of a swing power supply device that generates the swing power source And at least a first level shifter, a second level shifter, a drive signal processing circuit, a third level shifter, and an output circuit, and are connected in the order described above to perform optimal signal transmission. A liquid crystal driving device for driving an electrode and a driving method thereof. 14. A plurality of power supplies for generating a plurality of potentials, a plurality of drive signal processing devices for processing a display drive signal using the power supply, and a signal electrode formed by signals from some of the drive signal processing devices. A liquid crystal drive including a signal electrode output device to be driven and a scan electrode output device for driving a scan electrode by a signal from another part of the drive signal processing device, and a matrix electrode including the signal electrode and the scan electrode In the device and its driving method, a part of the plurality of power supplies is a DC power supply having a substantially constant potential with respect to time, and the other part of the plurality of power supplies has a potential with time. The signal electrode is driven by processing the DC power supply into a signal electrode drive waveform by an output device, and the scan electrode is connected to the oscillating power supply and the DC power supply. A scan electrode is driven by processing a power supply and a scan electrode driving waveform by an output device, and a wiring of a scan electrode output device that drives the scan electrode from a swing power supply device that generates power of the swing power source And at least a first level shifter, a second level shifter, a drive signal processing circuit, a third level shifter, and an output circuit. A liquid crystal driving device and a driving method thereof. 15. At least a first level shifter, a second level shifter and a second level shifter are provided between a wiring of a swing power supply for generating a power of the swing power and a wiring of a scan electrode output device for driving the scan electrode. One inverter, a drive signal processing circuit, a third level shifter, and an output circuit in which a plurality of other inverters are connected to the input stage, and the electrodes are connected in the above-described order so as to perform optimal signal transmission. 14. The liquid crystal driving device according to claim 13, wherein the driving is performed. 16. At least a first level shifter, a second level shifter, and a first inverter are provided between a swing power supply device for generating a power supply of the swing power supply and a scan electrode output device for driving the scan electrodes. And a drive signal processing circuit, a third level shifter, and an output circuit in which a plurality of other inverters are connected to the input stage, and the electrodes are connected in the above-described order to drive the electrodes with optimum signal transmission. 14. The liquid crystal driving device according to claim 13, wherein the driving method is performed. 17. The first level shifter has a first PMOS transistor having a gate connected to the input means and a source and a back gate connected to a high DC power supply, and a gate connected to a low DC power supply and a source connected to the input means. A second PMOS transistor having a drain connected to the drain of the first PMOS transistor and having a gate connected to the high DC power supply and a back gate connected to the oscillating low power supply; Connected third NMOS
A transistor, a fourth NMOS transistor 518 having a drain connected to the drain of the second PMOS transistor 516, a gate connected to the DC high power supply, and a back gate connected to the oscillating low power supply; and a third NMOS transistor 518. A fifth transistor having a drain connected to the source of the transistor, a gate connected to the drain of the second PMOS transistor, a source and a back gate connected to the oscillating low power supply,
A transistor having a drain connected to the source of the fourth NMOS transistor, a gate connected to the drain of the first PMOS transistor 515, a source and a back gate connected to the oscillating low power supply, and a sixth NMOS transistor 520; Further, the output of the first level shifter is supplied to the second PMOS transistor 5 together with the first output obtained from the drain of the first PMOS transistor.
14. The liquid crystal driving device according to claim 13, wherein the liquid crystal driving device has a second output obtained from 16 drains. 18. The second level shifter, a seventh NMOS transistor 558 having a gate connected to the output of the first level shifter and a source and a back gate connected to a oscillating low power supply, and a drain connected to a drain of the NMOS transistor. A ninth PMOS transistor having a source and a back gate connected to a power supply during oscillation, and an eighth transistor having a gate connected to another output of the first level shifter and having a source and a back gate connected to a power oscillation low power supply. NMO
An S transistor; a tenth PMOS transistor 557 whose drain is connected to the drain of the eighth NMOS transistor and whose source and back gate are connected to the power supply while swinging; and the gate of the ninth PMOS transistor is an eighth NMOS transistor.
A tenth PMOS connected to the drain of the transistor;
The gate of the transistor is the seventh NMOS transistor 5
58, and the output of the second level shifter is an eighth NMOS.
14. The liquid crystal driving device and the driving method thereof according to claim 13, wherein the configuration is obtained from a drain of the transistor. 19. An eleventh NMOS transistor in which the first inverter has a gate serving as an input terminal and a source and a back gate are connected to an oscillating low power supply, and the source has an input terminal and a source and a back gate are oscillating. 16. The liquid crystal driving device according to claim 15, comprising a twelfth PMOS transistor 581 connected to a power supply and having a drain connected to a drain of the eleventh NMOS transistor. 20. The third level shifter, a thirteenth PMOS transistor having a gate connected to the input means, a source and a back gate connected to the oscillating high power supply, a gate connected to another input means, and a source connected to the source. A fourteenth PMOS transistor having a back gate connected to the oscillating high power supply, a fifteenth PMOS transistor having a drain connected to the drain of the thirteenth PMOS transistor, and having a back gate connected to the oscillating high power supply; It has a drain connected to the drain of the fourteenth PMOS transistor, and has a back gate connected to the oscillating high power supply and connected to the sources of the sixteenth and fifteenth PMOS transistors and the gate of the sixteenth PMOS transistor. Drain, the gate is connected to the input means, and the source and the back gate are The 17th NM connected to the oscillating low power supply
The OS transistor has a drain connected to the source of the sixteenth PMOS transistor and the gate of the fifteenth PMOS transistor, the gate is connected to the other input means of the signal, and the source and the back gate are oscillating. 14. The liquid crystal driving device according to claim 13, comprising an eighteenth NMOS transistor connected to a power supply, wherein an output of the third level shifter is obtained from a drain of the eighteenth NMOS transistor. 21. The output circuit, wherein the source of a twenty-first PMOS transistor is connected to the source of a twenty-second NMOS transistor, and the source is connected to the drain of a nineteenth PMOS transistor and the drain of a twentieth NMOS transistor. Connected to the drain of a nineteenth PMOS transistor having a configuration, the drain of a twenty-first PMOS transistor and the twenty-second N
The connection point to which the drain of the MOS transistor is connected is connected to the DC power supply, the gate of the twenty-first PMOS transistor is connected to the output of at least one inverter device connected to the input means, and the back gate is the oscillating high power supply. Wherein the gate of the twenty-second PMOS transistor is connected to the input of the at least one inverter device connected to the input means, and the back gate is connected to the oscillating low power supply. The liquid crystal driving device according to claim 13 and a driving method thereof. 22. An output circuit for driving a liquid crystal, wherein a source of a nineteenth PMOS transistor on a high potential side is connected to a swing high power supply in a circuit at a final stage of a scan electrode output device for driving a liquid crystal. The source terminal of the twentieth NMOS transistor on the low potential side is connected to the oscillating low power supply, and the drain of the nineteenth PMOS transistor is connected to the twentieth NMOS transistor.
And the drain of the nineteenth PMOS transistor is connected to the drain of the nineteenth PMOS transistor.
A second connection point for controlling the supply of the DC intermediate power supply VM connected in parallel to the connection point with the drain of the MOS transistor.
Source of two NMOS transistors and twenty-first PMOS
The source of the transistor is connected, and at least one scanning electrode is connected to this connection point. The connection point between the drain of the 22nd NMOS transistor connected in parallel and the 21st PMOS transistor is: , A DC intermediate power supply VM is connected, and the gate of the twentieth NMOS transistor is connected to 2
One input terminal of the NOR circuit is connected to the input NOR circuit output, and one input terminal of the NOR circuit is connected to the first input means, and the second input means is connected to the other input terminal via at least n (positive integer) inverters. The gate of the nineteenth PMOS transistor is connected to a two-input NAND circuit output, one input terminal of the NAND circuit is connected to first input means, and the other input terminal has at least n input means. 14. The liquid crystal driving device and the driving method thereof according to claim 13, wherein the liquid crystal driving device has a configuration connected via ± 1 (positive integer) inverters.