JP2007101740A - Driving circuit for display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a driving circuit for a display device which does not need an expensive isolation circuit using a photocoupler with little possibility of time degradation, and with no restriction to a driving waveform. <P>SOLUTION: In the driving circuit for the display device, a level shift circuit 100 is equipped with a signal line 91 for first level conversion and a signal line 29 for second level conversion each of which have switching parts 103 and 104 and a potential difference generation part as signal lines 91 and 92 for level conversion, and in each of which transmitted signal voltages are mutually different in polarity. Then either one of the signal line 91 and signal line 92 which have unique feeding direction restricting means 105 and 109 is selected and used according to the large/small relation between a reference voltage and a driving reference voltage of a control power circuit. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a drive circuit for a display device that performs display by driving a light emitting element such as an inorganic EL (electroluminescence) element at a high voltage with bipolar polarity.

JP-A-9-54566 JP 2000-298455 A JP 2004-258103 A

  A dot matrix type display device using a light emitting element is usually driven by using a scanning side (row) driver IC (scanning driving circuit) and a data side (column) driver IC (data driving circuit). For example, Patent Document 1 discloses a drive circuit that applies an offset voltage to a scan drive circuit in a dot matrix type EL display device using inorganic EL elements. Patent Document 2 discloses a drive circuit using a thyristor as a scanning side driver IC. In either method, the reference potential of the scan driving circuit is on the high voltage side or the low voltage side with respect to the reference potential of the control circuit depending on the polarity of the voltage waveform applied to the light emitting element. In order to transmit a signal from the control circuit to the scan drive circuit in such a potential relationship, the signal is obtained by insulating the control circuit side and the scan drive circuit side in a circuit using a photocoupler called an isolation circuit. I try to transmit.

  However, in the above configuration, the isolation circuit for power source separation uses an expensive photocoupler, and thus has a disadvantage of increasing the cost. In particular, the pattern of the control signal for performing bipolar scan control of the dot matrix of the display element is complex, and sometimes 3 to 4 types of signals to be transmitted from the control circuit to the scan drive circuit are required. The structure of an isolation circuit using a coupler becomes more and more complicated, and it is difficult to avoid the problem of cost increase. Furthermore, the photocoupler has a problem of deterioration with time of the incorporated LED (that is, life of light emission intensity), and there is a problem that it is difficult to ensure the life in an environment where it is frequently used for a long period of time such as an automobile meter.

  On the other hand, Patent Document 3 discloses a method of transmitting a signal without using a photocoupler, but it has a structure that can be transmitted only when the reference potential of the control circuit and the reference potential of the scanning drive circuit match. Therefore, there is a problem that the drive waveform is restricted.

  An object of the present invention is to provide a drive circuit for a display device that does not require an expensive isolation circuit using a photocoupler, is less likely to deteriorate with time, and does not restrict the drive waveform.

Means for Solving the Problems and Effects of the Invention

In order to solve the above-described problems, a display device drive circuit according to the present invention includes:
A scanning drive circuit for applying a scanning voltage to the scanning electrode of the display panel having the light emitting element formed at the intersection of the scanning electrode and the data electrode as a pixel;
A data driving circuit for applying a data voltage to the data electrodes;
A drive reference voltage switching circuit that switches the level of the drive reference voltage, which is a reference voltage of the scan drive circuit, so that the polarity of the combined voltage of the scan voltage and the data voltage is inverted in a predetermined cycle; and the drive reference voltage A floating power supply unit for scanning having a sub power supply unit for generating a floating power supply voltage of a driving logic system with reference to
A control circuit for outputting a primary control logic signal with a fixed reference voltage for controlling the scanning drive circuit, the data drive circuit, and the drive reference voltage switching circuit;
A level shift circuit that modulates a float power supply voltage using a primary control logic signal, converts the level into a secondary control logic signal based on the drive reference voltage, and outputs the converted signal to the scan drive circuit. The level conversion signal line that directly connects the power supply unit and the control power supply circuit that is the power supply circuit of the control circuit, and the current on the level conversion signal line based on the reference voltage difference between the scanning float power supply unit and the control power supply circuit side are primary. The switching unit that switches based on the input of the control logic signal, and the input voltage from the level conversion signal line is input via the branch input line, and the input voltage changes due to the switching of the current from the branch input line A secondary control logic signal output unit for outputting a secondary control logic signal based on the second control logic signal on the level conversion signal line Provided on the control power supply circuit side from the branch point to the power supply section, and when the current passes, the input signal voltage width to the secondary control logic signal output section is the reference voltage between the scanning float power supply section and the control power supply circuit side. And a level shift circuit including an input signal voltage adjustment unit that reduces the difference so as to be smaller than the difference.

  In the display device drive circuit according to the present invention, the power supply of the scan drive circuit is a scan float power supply unit in which the reference voltage varies as the drive voltage polarity is inverted. When the primary control logic signal on the side of the control circuit having a fixed reference voltage is converted into a secondary control logic signal for directly driving the scan drive circuit in which the reference voltage varies, an isolation circuit is not interposed. Rather, the scanning float power supply unit and the control power supply circuit are directly connected by the level conversion signal line, and a current is actively passed through the level conversion signal line due to the reference voltage difference therebetween. An input signal voltage adjustment unit is provided on the level conversion signal line, and when the current passes, the input signal voltage width to the secondary control logic signal output unit is changed by the input signal voltage adjustment unit to the scanning float power supply unit. It is reduced so as to be smaller than the reference voltage difference from the control power supply circuit side. As a result, an expensive isolation circuit using a photocoupler can be eliminated, and the level shift circuit can be configured at a much lower cost. In addition, since the level shift circuit does not use LEDs, there is little risk of deterioration over time, and there is no restriction on the drive waveform.

  The light emitting element can be composed of an inorganic EL element. In an inorganic EL element, an EL light emitting portion is a functional dielectric, and it is necessary to perform excitation bias of charged particles necessary for light emission by applying a high voltage waveform whose polarity changes. Therefore, the present invention is suitable for application on the premise of polarity reversal at a high reference voltage.

  The input signal voltage adjustment unit can be configured by an adjustment resistor inserted in series on the level conversion signal line. According to this configuration, a simple circuit using an adjustment resistor can generate a large potential difference between, for example, a grounded reference voltage of the control power supply circuit and a reference voltage biased by the sub power supply unit of the floating power supply unit for scanning. It can be easily absorbed by the configuration.

  The above switching unit can be constituted by a transistor (which may be either an FET or a bipolar transistor). In this case, an auxiliary capacitance larger than the parasitic capacitance of the transistor can be inserted between the input line to the secondary control logic signal output section and the level conversion signal line toward the scanning float power supply section. In accordance with the switching of the polarity of the reference voltage of the scanning float power supply unit, the charge accumulated in the parasitic capacitance of the transistor forming the switching unit is discharged and a noise current flows, and the switching unit is off-controlled. There is a possibility that a voltage change edge will occur at the input to the next control logic signal output unit, causing a malfunction of the scan drive circuit. However, by providing the auxiliary capacitance as described above, the charge of the transistor is absorbed, and even when the reference voltage of the scanning float power supply is switched, a steep voltage change edge is less likely to occur, thus preventing a malfunction of the scanning drive circuit. can do.

  The drive reference voltage switching circuit can perform switching so that the polarity of the drive reference voltage changes periodically. The level shift circuit includes, as level conversion signal lines, a first level conversion signal line and a second level conversion signal line, each having a switching unit and a potential difference generation unit and having different polarities of transmitted signal voltages. Depending on the magnitude relationship between the reference voltage of the control power supply circuit and the drive reference voltage, one of the first level conversion signal line and the second level conversion signal line each having a specific energization direction regulating means is selected. Can be used. When the reference voltage (drive reference voltage) of the scanning float power supply section periodically inverts the polarity, the magnitude relationship between the reference voltage of the control power supply circuit and the drive reference voltage is also inverted. Accordingly, the polarity of the signal voltage applied to the level conversion signal line (that is, the direction of the current to flow) is reversed according to the magnitude relationship. As described above, the level conversion signal line is provided with the first level conversion signal line and the second level conversion signal line. Accordingly, by selecting and using either one of the signal lines, the level conversion of the primary control logic signal to the secondary control logic signal is performed very smoothly despite the polarity of the drive reference voltage being periodically inverted. be able to.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 shows an overall configuration of an EL display device 15 which is an example to which the present invention is applied. The EL display device 15 can be roughly divided into a display device driving circuit 10 and a display panel 1. The display device drive circuit 10 has the following requirements.
Scan driving circuit 4: A scanning voltage is applied to the scanning electrode 2 of the display panel 1 having the light emitting element 77 formed at the intersection of the scanning electrode 2 and the data electrode 3 as a pixel.
Data drive circuit 5: A data voltage is applied to the data electrode 3.
Scanning float power supply unit 60: Drive reference that switches the level of the drive reference voltage, which is the reference voltage of the scan drive circuit 4, so that the polarity of the combined voltage of the scan voltage and the data voltage is inverted at a predetermined period. It has a voltage switching circuit 6 and a sub power supply unit 41 that generates a floating power supply voltage for a driving logic system based on the drive reference voltage.
Control circuit 7: Outputs a primary control logic signal with a fixed reference voltage for controlling the scanning drive circuit 4, the data drive circuit 5, and the drive reference voltage switching circuit 6.
Level shift circuits 100, 200, and 300: The float power supply voltage is modulated by using the primary control logic signal, thereby converting the level into a secondary control logic signal based on the drive reference voltage and outputting it to the scan drive circuit 4 To do. As shown in FIG. 2, it is configured with the following requirements.
... Level conversion signal lines 91 and 92 are provided in such a manner that the scanning float power supply unit 60 and the control power supply circuit 51 which is the power supply circuit of the control circuit 7 are directly connected.
Switching units 103 and 104: The currents on the level conversion signal lines 91 and 92 based on the reference voltage difference between the scanning float power supply unit 60 and the control power supply circuit 51 are switched based on the input of the primary control logic signal.
... Secondary control logic signal output unit 113: Input voltages from the level conversion signal lines 91 and 92 are input via the branch input lines 114 and 115, and accompanying the switching of current from the branch input lines 114 and 115. A secondary control logic signal is output based on the change in input voltage.
Input signal voltage adjustment unit 106, 110: Provided on the control power supply circuit 51 side from the branch point to the secondary control logic signal output unit 113 on the level conversion signal lines 91, 92, and when the current passes, The input signal voltage width to the control logic signal output unit 113 is reduced to be smaller than the reference voltage difference between the scanning float power supply unit 60 and the control power supply circuit 51 side.

  The display panel 1 is an EL panel in which an inorganic EL element (light emitting element) 77 formed at the intersection of the scanning electrode 2 and the data electrode 3 is used as a pixel. In the inorganic EL element 77, the portion located at the electrode intersection functions individually as a light emitter, but since it is a dielectric, in this embodiment, it is configured as a passive matrix EL panel formed as a single inorganic EL thin layer. ing. The polarity of the combined voltage of the scanning voltage and the data voltage is applied to each pixel by the line-sequential scanning method while being alternately inverted, and is driven so that the EL element 77 emits light during the scanning-side selection period (this operation). This is known as disclosed in detail in Patent Documents 1 to 3, and will not be described in detail.

  The reference potential (and terminal) of the data driving circuit 5 and the control circuit 7 is indicated by the symbol GND, and this potential is the ground potential (for example, ground potential) of the entire EL display device 15. A power supply voltage from a control power supply circuit 51 for driving the logic system of the data drive circuit 5 and the control circuit 7 with reference to GND is supplied from the inside or the outside. This potential is set as a logic power supply potential (and terminal: control power supply voltage) VDD. The data drive circuit 5 is supplied with the power supply voltage from the EL drive waveform power supply circuit 52 from inside or outside. This potential is defined as a high-voltage power supply potential VEE. The voltage values of VDD and VEE are arbitrary, but here, VDD = 5V and VEE = 50V based on GND.

  The reference potential (and terminal: drive reference voltage) of the scanning drive circuit 4 is indicated by the symbol FGND. The power supply voltage from the sub power supply unit 41 for driving the logic system of the scan driving circuit 4 is supplied from the inside or the outside with reference to FGND. This potential (and terminal) is set as a logic power supply potential (float power supply voltage) FVDD. The scan driving circuit 4 is supplied with a power source 42 for EL driving waveform from the inside or the outside. This potential (and terminal) is set as a high-voltage power supply potential FVEE. The voltage values of FVDD and FVEE are arbitrary, but here, FVDD = 5V and FVEE = 200V on the basis of FGND.

  The potential relationship between GND and FGND is determined by the operation of the drive reference voltage switching circuit 6. When a positive scanning voltage is applied from the scanning drive circuit 4, the switch 61 of the drive reference voltage switching circuit 6 is energized and the switch 62 is de-energized. At this time, the potential of FGND becomes 50 V to which VEE is added (based on GND). Similarly, FVDD = 55V and FVEE = 250V. On the other hand, when a negative scanning voltage is applied from the scanning drive circuit 4, the switch 61 of the drive reference voltage switching circuit 6 is in a non-energized state and the switch 62 is in a conductive state. At this time, the potential of FGND becomes −200 V obtained by subtracting FVEE (based on GND). Similarly, FVDD = −195V and FVEE = 0V. In this embodiment, the scanning float power supply unit 60 can be regarded as being composed of the drive reference voltage switching circuit 6 and the four power supply units 41, 42, 51, 52.

  In the circuit of this embodiment, for example, as disclosed in Patent Document 2 or Patent Document 3, the scan drive circuit 4 outputs a binary control signal input to three types of input terminals (CLK, DATA, PC). (The number of input terminals increases or decreases depending on the configuration of the scanning drive circuit 4). The input terminal is recognized as a low level if the voltage value of the signal is FGND and as a high level if the voltage value = FVDD.

  The control circuit 7 is composed of an integrated circuit such as a gate array or a microcomputer, and outputs three types of signals that are the source of CLK, DATA, and PC in synchronization with signals sent to the drive reference voltage switching circuit 6 and the data drive circuit 5. (101, 201, 301). The voltage value of this signal is GND at a low level and VDD at a high level. These are input to the respective level shift circuits 100, 200, 300, output as signals (102, 202, 302) whose voltage levels are converted, and input to the scanning drive circuit 4. Since the level shift circuits 100, 200, and 300 all have the same configuration, the level shift circuit 100 will be described below as a representative.

FIG. 2 shows details of the level shift circuit 100 as an example.
The input signal voltage adjustment units 106 and 110 include adjustment resistors 106 and 110 inserted in series on the level conversion signal lines 91 and 92. Further, the switching units 103 and 104 are constituted by transistors, and the transistors are arranged between the input line to the secondary control logic signal output unit 113 and the level conversion signal lines 91 and 92 toward the scanning float power supply unit 60. Auxiliary capacitances 107 and 111 larger than the parasitic capacitance are inserted. Each transistor is composed of a MOSFET having a parasitic diode. The parasitic diode plays a role of securing a conduction path for noise current generated by line-to-line capacitive coupling or the like when the FGND potential is switched.

  As described above, the drive reference voltage switching circuit 6 performs switching so that the polarity of the drive reference voltage FGND changes periodically. The level shift circuit 100 (200, 300) includes the switching units 103 and 104 and the potential difference generation unit as the level conversion signal lines 91 and 92, respectively, and the first level conversion in which the polarities of the transmitted signal voltages are different from each other. Signal line 91 and second level conversion signal line 92 are provided. Then, the first level conversion signal line 91 and the second level conversion signal line having their own energization direction regulating means 105 and 109, respectively, according to the magnitude relationship between the reference voltage of the control power supply circuit 51 and the drive reference voltage. 92 is selected and used.

  Specifically, the following configuration is adopted. That is, the control reference voltage terminal GND which is the reference voltage terminal of the control power supply circuit 51 is grounded, and the first level conversion signal line 91 is connected to the float power supply voltage terminal FVDD of the scanning float power supply unit 60 and the control power supply circuit 51. The control reference voltage terminal GND is connected to the control reference voltage terminal GND. The second level conversion signal line 92 is provided so as to connect the drive reference voltage terminal FGND of the scanning float power supply unit 60 and the control power supply voltage terminal VDD which is the power supply voltage terminal of the control power supply circuit 51. .

  The first level conversion signal line 91 is inserted in series with the first level conversion signal line 91 so as to be forward biased when the float power supply voltage terminal FVDD side has a higher voltage than the control reference voltage terminal GND. A diode 105. The second level conversion signal line 92 is serially connected to the second level conversion signal line 92 so as to be forward-biased when the control power supply voltage terminal VDD side becomes higher voltage than the drive reference voltage terminal FGND side. The diode 109 is inserted into the. As described above, the first level conversion signal line 91 and the second level conversion signal line 92 are biased according to the polarity of the voltage difference between the control power supply circuit 51 side and the scanning float power supply unit 60 side, respectively. By inserting the diodes 105 and 109 that are opposite to each other, the functions of the energization direction restricting means 105 and 109 can be easily realized.

  The first level conversion signal line 91 and the second level conversion signal line 92 are opposite in polarity to the voltage difference between the control power supply circuit 51 side and the scanning float power supply unit 60 side. It is appropriate to use transistors whose driving polarities are mutually inverted for the switching units 103 and 104 provided. In FIG. 2, the switching units 103 and 104 employ MOSFETs having different channel conductivity types. A signal distribution unit 93 is provided that distributes the primary control logic signal from the control circuit 7 to the transistors on the signal lines 91 and 92 in the form of the polarity being inverted. This contributes to simplification of the input circuit configuration to the signal lines 91 and 92. Here, the signal distribution unit 93 includes an input-side buffer unit 120 and an inverter 121 that inverts a distribution input signal to the switching unit 103 to the signal line 92 side.

  The first level conversion signal line 91 and the second level conversion signal line 92, which are selected and used according to the polarity, inevitably have opposite signal energization polarities. However, when the polarity of the voltage difference between the control power supply circuit 51 side and the scanning float power supply unit 60 side is inverted, the logical polarity of the secondary control logic signal is also inverted accordingly. Therefore, it is desirable to keep the logical polarity of the secondary control logic signal unchanged regardless of which polarity is established. Therefore, in the present embodiment, the secondary control logic signal output unit 113 includes the potential change signal output from the potential difference generation unit of the first level conversion signal line 91 and the potential difference generation unit of the second level conversion signal line 92. If one of the potential change signals output from the signal is logically inverted and the logical sum is output as a secondary control logic signal, the primary control logic signal is input from either signal line. Regardless, the logic polarity of the secondary control logic signal can be kept constant.

  Specifically, the secondary control logic signal output unit 113 is similar to the buffer unit 122 that receives a potential change signal from one of the first level conversion signal line 91 and the second level conversion signal line 92, and the other side. The inverter section 123 receives the potential change signal from the input section, and the OR section 124 calculates the logical sum of the outputs of the buffer section 122 and the inverter section 123. As a result, the secondary control logic signal output unit 113 that can stably cope with polarity inversion between the control power supply circuit 51 side and the scanning float power supply unit 60 side is realized.

  In FIG. 2, the secondary control logic signal output unit 113 is configured as a CMOS logic circuit in which a buffer unit 122, an inverter unit 123, and an OR operation unit 124 are integrated on a CMOS integrated circuit. In addition, a pull-up resistor 108 or a pull-down resistor 112 is provided between the branch input lines 114 and 115 to the secondary control logic signal output unit 113 and the level conversion signal lines 91 and 92 toward the scanning float power supply unit 60. A functioning auxiliary resistor is provided. Thereby, even when the signal current on the first level conversion signal line 91 to the second level conversion signal line 92 is cut off by the switching units 103 and 104, the logic input to the CMOS logic circuit does not become high impedance, A bi-state input state of the primary control logic signal to the secondary control logic signal output unit 113 can be maintained, and a stable secondary control logic signal can be supplied to the scan driving circuit 4.

  As shown in FIG. 3, Zener diodes 116 and 117 may be inserted between the branch input lines 114 and 115 and the level conversion signal lines 91 and 92 in parallel with the auxiliary resistors. In this way, the edge height of the bi-state input to the CMOS logic circuit can be kept constant, which contributes to further stabilization of the secondary control logic signal output.

  The level shift circuit 100 (200, 300) in FIG. 2 is configured as a MOS-IC. The switching units 103 and 104 made of MOSFETs are CMOS logic circuits (and the distribution input unit 93: the buffer unit 120 and the inverter unit 121 are also CMOS logic circuits) forming the secondary control logic signal output unit 113, and the level shift circuit. It is incorporated in a CMOS-IC forming 100, 200, 300. Thereby, the level shift circuits 100, 200, and 300 can be made compact.

  The scan drive circuit 4 can also be configured as a MOS-IC. As shown in FIG. 5, the CMOS logic circuit forming the secondary control logic signal output unit 113 is connected to the MOS-IC forming the scan drive circuit 4. Can be incorporated into The scanning drive circuit 4 is generally configured as a high voltage type large-scale integrated circuit for scanning control of a large number of high voltage drive light emitting elements 77. If the CMOS logic circuit forming the secondary control logic signal output unit 113 having a configuration peculiar to the present invention is incorporated in the MOS-IC forming the scan drive circuit 4, the circuit pattern of the MOS-IC is only slightly changed. Can be easily and inexpensively supported. In this case, the level shift circuit 100 (200, 300) has a simple configuration in which the secondary control logic signal output unit 113 is omitted as shown in FIG. A pair 102 ′ (202 ′, 302 ′) of the branch input line 114 from the first level conversion signal line 91 and the branch input line 115 from the second level conversion signal line 92 is as shown in FIG. The secondary control logic signal output unit 113 ′ incorporated in the MOS-IC 2 constituting the scan driving circuit 4 is input.

Hereinafter, the operation of the level shift circuit 100 (200, 300) of FIG. 2 will be described.
1, the primary control logic signal from the control circuit 7 is input to the signal distribution unit 93 of FIG. 2 via the input signal lines 101 (201 and 301), and further input to the gate of the MOSFET 104. A diode 105 and an adjustment resistor 106 are connected in series to the drain, and the direction of the diode 105 is a cathode on the drain side, and the order of the diode 105 and the adjustment resistor 106 may be changed. And a pull-up resistor 108 and a branch input line 114 to the secondary control logic signal output unit 113.

  On the other hand, the other ends of the auxiliary capacitance 107 and the pull-up resistor 108 are connected to FVDD. An input signal 101 from the control circuit 7 is further input to the gate of the MOSFET 103 through the inverter 121. A diode 109 and an adjustment resistor 110 are connected in series to the drain of the MOSFET 103. The direction of the diode 109 may be the anode on the drain side, and the order of the diode 109 and the adjustment resistor 110 may be switched. One end of the adjustment resistor 110 is connected to the auxiliary capacitance 111, the pull-down resistor 112, and the branch input line 115 of the secondary control logic signal output unit 113. The other ends of the auxiliary capacitance 111 and the pull-down resistor 112 are connected to FGND. Although the logic is inverted using the inverter unit 121 here, an inverted logic signal of the signal 101 may be separately generated on the control circuit 7 side and directly input.

First, an operation when the potential of FGND is equal to or higher than VDD will be described.
On the first level conversion signal line 91 side, when the input signal 101 is at a high level, the MOSFET 104 becomes conductive, and a current flows from FVDD to the drain of the MOSFET 104 through the pull-up resistor 108, the adjustment resistor 106, and the diode 105. When the current flows, a potential difference is generated between both ends of the pull-up resistor 108, and the branch input line 114 is recognized as being at a low level. The pull-up resistor 108 has a function of preventing the potential of the branch input line 114 from becoming high impedance when no current flows. When the input signal 101 is at a low level, no current flows because the MOSFET 104 is non-conductive. Therefore, no potential difference is generated in the pull-up resistor 108 and the branch input line 114 is recognized as being at a high level.

  On the other hand, on the second level conversion signal line 92 side, since the logic is inverted by the inverter unit 121, the MOSFET 103 is in a non-conductive state when the input signal 101 is at a high level, and is in a conductive state when the input signal 101 is at a low level. However, since the potential of FGND is higher than VDD, the diode 109 is reverse-biased and no current flows regardless of the state of the MOSFET 103. Therefore, the branch input line 115 is fixed at a low level. The secondary control logic signal output unit 113 is configured to output a low level when the input from the branch input line 114 is at a high level and the input from the branch input line 115 is at a low level, and otherwise outputs a high level. ing. Therefore, when the input 101 (201, 301) in FIG. 1 is at the low level, the output 102 (202, 302) is at the low level, and when the input 101 (201, 301) is at the high level, the output 102 (202, 302). Becomes high level. That is, the voltage level is converted by logic non-inversion.

Next, an operation when the potential of FVDD is equal to or lower than GND will be described.
In this case, since the diode 105 is reverse-biased, the branch input line 114 is fixed at a high level. The logic of the input terminal 115 is determined by the logic of the input signal 101 by the same operation as described above. As a result, when the input 101 in FIG. 2 is at a low level, the output 102 (202, 302) is at a low level, and when the input 101 is at a high level, the output 102 (202, 302) is at a high level.

  The operation when the potential of FGND is equal to or lower than VDD and the potential of FVDD is equal to or higher than GND is as follows. First, the logic of both branch input lines 114 and 115 changes according to the input 101. When the input 101 is at a low level, the output 102 (202, 302) is at a low level, and when the input 101 is at a high level, the output 102 (202, 302) is at a high level. As described above, although the operation differs depending on the potential relationship between GND and FGND, the results are all the same logic non-inversion voltage level conversion, and it can be seen that signals can be transmitted regardless of the potential relationship between GND and FGND. In addition, as shown in FIG. 4, it is also possible to change the logic of the secondary control logic signal output unit 113 and transmit by logic inversion.

Next, details of the operation of the auxiliary capacitances 107 and 111 will be described.
The potential of FGND is switched by the drive reference voltage switching circuit 6. For example, when the MOSFET (transistor) 103 is non-conductive and FGND changes from 50 V to −200 V, the drain voltage of the MOSFET 103 changes from 5 V (VDD) to −200 V (FGND). Since a transistor has a parasitic capacitance of several tens to several hundreds pF between terminals, a current flows even in a non-conducting state due to a change in drain voltage. Assuming that the voltage change amount per unit time of the drain voltage is dV / dt and the parasitic capacitance between the source and gate of the drain terminal is Ct, the current value is Ct × dV / dt. When the auxiliary capacitance 111 is not provided, the product of the current value and the pull-down resistor 112 becomes a voltage value. Depending on the amount of change, the branch input line 115 becomes a high level, which may cause the scan drive circuit 4 to malfunction. is there. The auxiliary capacitance 111 receives current due to the parasitic capacitance of the MOSFET 103 and has an effect of preventing the potential of the input terminal 115 from rising. The capacitance of the auxiliary capacitance 111 is more effective than the parasitic capacitance of the MOSFET 103, and the larger the capacitance, the greater the voltage change amount can be withstood.

  Next, as shown in FIG. 7, in the level conversion circuit 100 (200, 300), the buffer unit and the inverter unit of the secondary control logic signal output unit 113 are both configured by bipolar transistors 230 and 231. (The same reference numerals are given to the common parts with FIG. 2 and the detailed description is omitted). Both primary control logic signals are input to the bases of the bipolar transistors 230 and 231. Each base is provided with input resistors 232 and 234 connected in series to the adjusting resistors 106 and 110, respectively, and a connection point between the resistors 106 and 232 and the resistors 110 and 234, and FVCC (= 5V: FVDD in FIG. 2). And diodes 208 and 222 for maintaining the change width of the base input voltage at 5V.

  In FIG. 7, the OR operation unit is configured by a wired OR connection unit (reference numerals 102 (202, 302) are outputs thereof) between the buffer unit 230 and the inverter unit 231. Thereby, the number of constituent elements of the secondary control logic signal output unit 113 can be reduced, and the circuit can be simplified. In this case, the secondary control logic signal output unit 113 can be configured by a TTL logic integrated circuit unit. The switching unit includes bipolar transistors 222 and 225 (input adjustment resistors 131 and 132 are provided at the base), and the level shift circuits 100, 200, and 300 together with the secondary control logic signal output unit 113. Can be incorporated in a bipolar IC. In this way, the level shift circuits 100, 200, 300 can be made compact. In this case, the ICs (120, 121) in the signal distribution unit 93 are also configured by TTL-ICs. Note that diodes 123 and 126 functionally equivalent to the parasitic diodes of the MOSFETs 103 and 104 in FIG. 2 are connected between the collectors and emitters of the bipolar transistors 222 and 225.

The operation of the circuit of FIG. 7 will be described.
The operation when the potential of FGND is equal to or higher than VCC (= 5V) is as follows. On the first level conversion signal line 91 side, when the input signal 101 is at a high level, the bipolar transistor 225 becomes conductive. As a result, the control circuit side of the first level conversion signal line 91 becomes conductive to GND, and the input of the bipolar transistor 230 becomes low level to make it conductive. As a result, a current flows through the first level conversion signal line 91. On the other hand, on the second level conversion signal line 92 side, since the logic is inverted by the inverter unit 121, the bipolar transistor 222 becomes non-conductive when the input signal 101 is high and becomes conductive when the input signal 101 is low. However, since the potential of FGND is higher than VCC, the diode 109 is reverse-biased and no current flows regardless of the state of the bipolar transistor 222. Then, the bipolar transistor 231 becomes conductive in the form of being pulled up via the resistor 233 on the collector side of the bipolar transistor 230. As a result, the wired OR output 102 (202, 302) conducts to FGND while being pulled up by the resistor 235, and becomes low level. That is, the secondary control logic signal output unit 113 outputs a low level when the input from the branch input line 114 is at a low level and the input from the branch input line 115 is at a high level, and outputs a high level otherwise. It has a configuration. Therefore, when the input 101 (201, 301) in FIG. 1 is at a low level, the output 102 (202, 302) is at a high level, and when the input 101 (201, 301) is at a high level, the output 102 is output.
(202, 302) goes low. That is, the voltage level is converted by logic inversion.

  Next, the operation when the potential of FVCC is equal to or lower than GND is as follows. In this case, since the diode 105 is reverse-biased, the branch input line 114 is fixed at a low level. The logic of the input terminal 115 is determined by the logic of the input signal 101 by the same operation as described above. As a result, when the input 101 in FIG. 2 is at a high level, the output 102 (202, 302) is at a low level, and when the input 101 is at a low level, the output 102 (202, 302) is at a high level. In addition, as shown in FIG. 8, it is also possible to change the logic of the secondary control logic signal output unit 221 and perform transmission without logic inversion.

  The operation when the potential of FGND is equal to or lower than VCC and the potential of FVCC is equal to or higher than GND is as follows. First, the logic of both branch input lines 114 and 115 changes according to the input 101. When the input 101 is at a high level, the output 102 (202, 302) is at a low level, and when the input 101 is at a low level, the output 102 (202, 302) is at a high level. As described above, although the operation differs depending on the potential relationship between GND and FGND, the results are all the same logic inversion voltage level conversion, and it can be seen that signals can be transmitted regardless of the potential relationship between GND and FGND. In addition, as shown in FIG. 8, it is also possible to change the logic of the secondary control logic signal output unit 221 and perform transmission without logic inversion.

  Although the present embodiment has been described with respect to the EL display device, it is needless to say that the present invention can also be applied to other display devices such as FED and PDP in which the reference potential of the scanning drive circuit changes.

The block diagram which shows the 1st example of a hardware constitutions of the display apparatus which has the drive circuit of this invention. The circuit diagram which shows the 1st example of a level shift circuit. The circuit diagram which shows a 2nd example similarly. The circuit diagram which shows a 3rd example similarly. The block diagram which shows the 2nd example of the hardware constitutions of the display apparatus which has the drive circuit of this invention. FIG. 6 is an explanatory diagram of a level shift circuit when the configuration of FIG. 5 is adopted. The circuit diagram which shows the 4th example of a level shift circuit. The circuit diagram which shows the 5th example of a level shift circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Display panel 2 Scan electrode 3 Data electrode 4 Scan drive circuit 5 Data drive circuit 6 Drive reference voltage switching circuit 7 Control circuit 10 Display device drive circuit 15 EL display device 41 Sub power supply unit 60 Scanning float power supply unit 91, 92 levels Conversion signal line 93 Signal distribution unit 100, 200, 300 Level shift circuit 103, 104 MOSFET (switching unit)
105, 109 diode (energization direction regulating means)
106,110 Adjustment resistor (input signal voltage adjustment unit)
107, 111 Auxiliary capacitance 108 Pull-up resistor 112 Pull-down resistor 113 Secondary control logic signal output unit 114, 115 Branch input line 116, 117 Zener diode 122 Buffer unit 123 Inverter unit 124 OR operation unit 222, 225 Bipolar transistor (switching unit) )
230 Buffer (bipolar transistor)
231 Inverter part (bipolar transistor)

Claims (15)

A scanning drive circuit for applying a scanning voltage to the scanning electrode of the display panel having a light emitting element formed at an intersection of the scanning electrode and the data electrode as a pixel;
A data driving circuit for applying a data voltage to the data electrode;
A drive reference voltage switching circuit that switches a level of a drive reference voltage that is a reference voltage of the scan drive circuit so that a polarity of a combined voltage of the scan voltage and the data voltage is inverted at a predetermined period; A scanning float power supply unit having a sub power supply unit for generating a drive logic system float power supply voltage based on the drive reference voltage;
A control circuit for outputting a primary control logic signal having a fixed reference voltage for controlling the scan driving circuit, the data driving circuit, and the driving reference voltage switching circuit;
A level shift circuit that modulates the float power supply voltage using the primary control logic signal, converts the level into a secondary control logic signal based on the drive reference voltage, and outputs the secondary control logic signal to the scan drive circuit; The level conversion signal line directly connecting the scanning float power supply unit and the control power supply circuit that is the power supply circuit of the control circuit, and the reference voltage difference between the scanning float power supply unit and the control power supply circuit side A switching unit that switches a current on the level conversion signal line based on an input of the primary control logic signal, an input voltage from the level conversion signal line is input via the branch input line, and the branch input line The secondary control logic signal output that outputs the secondary control logic signal based on the input voltage change accompanying the switching of the current from And the control power supply circuit side than the branch point to the secondary control logic signal output unit on the level conversion signal line, and the input to the secondary control logic signal output unit when the current passes through A level shift circuit including an input signal voltage adjustment unit that reduces a signal voltage width to be smaller than a reference voltage difference between the scanning float power supply unit and the control power supply circuit side;
A drive circuit for a display device, comprising:   The display device driving circuit according to claim 1, wherein the light emitting element is an inorganic EL element.   The display device drive circuit according to claim 1, wherein the input signal voltage adjustment unit includes an adjustment resistor inserted in series on the level conversion signal line.   The switching unit is composed of a transistor, and is larger than the parasitic capacitance of the transistor between the input line to the secondary control logic signal output unit and the level conversion signal line toward the scanning float power supply unit The display device driving circuit according to claim 1, wherein an auxiliary capacitance is inserted. The drive reference voltage switching circuit performs the switching so that the polarity of the drive reference voltage periodically changes.
The level shift circuit includes a first level conversion signal line and a second level conversion signal having the switching unit and the potential difference generation unit, respectively, and having different polarities of signal voltages transmitted as the level conversion signal lines. A first level conversion signal line and a second level conversion signal each having a specific energization direction restricting means according to the magnitude relationship between the reference voltage of the control power supply circuit and the drive reference voltage. 5. The display device driving circuit according to claim 1, wherein one of the signal lines is selected and used. A control reference voltage terminal which is a reference voltage terminal of the control power supply circuit is grounded, and the first level conversion signal line is connected to a float power supply voltage terminal of the scanning float power supply unit and a control reference voltage terminal of the control power supply circuit. The second level conversion signal line connects the drive reference voltage terminal of the scanning float power supply unit and the control power supply voltage terminal which is the power supply voltage terminal of the control power supply circuit. Provided,
The first level conversion signal line is inserted in series with the first level conversion signal line so as to be forward biased when the float power supply voltage terminal side has a higher voltage than the control reference voltage terminal. Having a diode,
The second level conversion signal line is inserted in series with the second level conversion signal line so as to be forward biased when the control power supply voltage terminal side has a higher voltage than the drive reference voltage terminal side. 6. The display device driving circuit according to claim 5, further comprising a diode.   The switching unit provided in each of the first level conversion signal line and the second level conversion signal line uses transistors whose driving polarities are inverted from each other, and each of the primary control logic signals from the control circuit is supplied to the switching circuit. 7. The display device driving circuit according to claim 5, further comprising a signal distribution unit that distributes one of the transistors on the signal line in the form of polarity reversed.   The secondary control logic signal output unit is output from the potential change signal output from the potential difference generation unit of the first level conversion signal line and from the potential difference generation unit of the second level conversion signal line. 8. The logical sum operation is performed by logically inverting one of the potential change signals and the logical sum is output as the secondary control logic signal. 8. Drive circuit for a display device.   The secondary control logic signal output unit includes a buffer unit that receives the potential change signal from one of the first level conversion signal line and the second level conversion signal line, and the potential change from the other. The display device drive circuit according to claim 8, comprising: an inverter unit that receives signals and an OR operation unit that calculates an OR of outputs from the buffer unit and the inverter unit.   The secondary control logic signal output unit includes a CMOS logic circuit in which the buffer unit, the inverter unit, and the OR operation unit are integrated on a CMOS integrated circuit, and the branch to the secondary control logic signal output unit The display device driving circuit according to claim 9, further comprising an auxiliary resistor functioning as a pull-up resistor or a pull-down resistor between the input line and the level conversion signal line directed to the scanning float power supply unit.   11. The display device driving circuit according to claim 10, wherein a Zener diode is inserted in parallel with the auxiliary resistor between the branch input line and the level conversion signal line.   The level shift circuit is configured as a MOS-IC, the switching unit is configured by a MOSFET, and is incorporated in the CMOS-IC that forms the level shift circuit together with the CMOS logic circuit that forms the secondary control logic signal output unit. 12. The display device drive circuit according to claim 8, wherein the display device drive circuit is formed.   12. The scan drive circuit is configured as a MOS-IC, and the CMOS logic circuit forming the secondary control logic signal output unit is incorporated in the MOS-IC forming the scan drive circuit. The display device drive circuit according to any one of the preceding claims.   In the secondary control logic signal output unit, both the buffer unit and the inverter unit are configured by bipolar transistors, and the OR operation unit is a wired OR connection unit between the buffer unit and the inverter unit. The display device driving circuit according to claim 7, which is configured.   The secondary control logic signal output unit is configured by a TTL logic integrated circuit unit, the switching unit is configured by a bipolar transistor, and the bipolar control logic signal output unit and the bipolar shifter that forms the level shift circuit are included in the bipolar IC. The display device driving circuit according to claim 14, which is incorporated.

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