JP2001066567A - Oscillating power source circuit for liquid crystal panel - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an oscillating power source circuit for a liquid crystal panel permitting to reduce an IC in size. SOLUTION: Level shifters 101, 102, 103, 104 and buffers 105, 106 are formed on an SOI substrate. An upper side oscillating power source VDD is composed of the level shifters 101, 102 are the buffer 105. Similarly, the lower side oscillating power source are composed of the level shifters 103, 104 and the buffer 106. Since the voltage to be applied to each element can be reduced to almost a half of a selection pulse amplitude and the withstand voltage of the element is lowered, an IC can be reduced in size.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a swing power supply circuit for a liquid crystal panel characterized by an integrated circuit substrate and a level shift means.

[0002]

2. Description of the Related Art A passive type liquid crystal panel has a structure in which a signal electrode and a scanning electrode are formed on two transparent substrates opposed to each other with a liquid crystal layer interposed therebetween, and an intersection portion is defined as a pixel. Responds to the effective value to perform matrix display. In particular, a display method in which the effective value of each pixel in the liquid crystal panel in the non-selection period is equal and a difference in the effective value of each pixel appears only during the selection period is called a voltage averaging method. While various waveforms have been devised based on the voltage averaging method, a method of applying a low-voltage data signal waveform to the signal electrode and applying a high-voltage selection pulse to the scan electrode is also used in many products. I have.

FIG. 4 illustrates this method. (A)
FIG. 2 is a schematic diagram enlarging a part of a conventional example of a passive type liquid crystal panel, and FIG. 2 (B) is a driving waveform diagram thereof.
(A), the vertically long rectangular signal electrodes S1, S2, S
3 are arranged in the horizontal direction, and the rectangular scanning electrodes T which are long in the horizontal direction.
1, T2, T3 are arranged in the vertical direction. In addition, between the signal electrodes S1, S2, and S3 and the scanning electrodes T1, T2, and T3, an alignment film, an insulating layer, and the like are stacked in addition to the liquid crystal layer, but are not shown. The intersection of the signal electrodes S1, S2, S3 and the scanning electrodes T1, T2, T3 is a pixel. Of these, the pixels G22, G23 formed at the intersection of the signal electrodes S2, S3 and the scanning electrode T2 are shown by oblique lines. Is shown.
(B) shows a state around the selection pulse. The driving waveform applied to the scanning electrode T1 was initially at the ground level (hereinafter referred to as VM level) for liquid layer driving since it was in the non-selection period. However, in the selection period, a negative high-voltage selection pulse appears. , Returns to the VM level when the non-selection period comes again. Similarly, the drive waveforms of the scan electrodes T2 and T3 also have positive and negative selection pulses in each selection period, and are at the VM level in other non-selection periods. The drive waveform of the signal electrodes S2 and S3 is a binary (± VD) low voltage data signal waveform centered on the VM level. For the sake of explanation, the waveforms of the signal electrodes S2 and S3 have opposite polarities, and the polarities are switched every selection period. From these, the driving waveform of the pixels G22 and G23 is obtained as the difference between the driving waveform of the scanning electrode T2 and the driving waveform of the signal electrodes S2 and S3. When the driving waveforms of the pixels G22 and G23 are compared, the polarity is reversed in the non-selection period, but the absolute value | ± VD |
It can be seen that each has a constant value. Therefore, the effective values applied to the pixels G22 and G23 during the non-selection period become equal. On the other hand, in the selection period, a pulse having a high peak value (VT + VD) is applied to the pixel 22, while a pulse having a low peak value (VT-VD) is applied to the pixel 23. The pixel 22 is larger than the pixel 23. In other words, the difference between the transmittances of the pixels 22 and 23 is created using the difference in the effective value only during the selection period.

A method of applying a low-voltage, constant-amplitude data signal waveform to the signal electrode and applying a high-voltage selection pulse to the scanning electrode at the time of selection is performed by a circuit for driving the signal electrode (hereinafter referred to as a signal electrode driving IC). ) Can be reduced, which is advantageous for reducing the size and power consumption of the signal electrode driving IC. However, a circuit for driving the scan electrodes (hereinafter, referred to as a scan electrode drive IC) outputs a positive / negative high-voltage pulse, so that an ordinary circuit requires a power supply having a voltage of + VT or more and a voltage of -VT or less. Even in the method of generating a selection pulse by switching the C-MOS analog switch, which is the minimum case, a voltage difference (2 VT) between power supplies is applied to the scan electrode drive IC, and the scan electrode drive IC has a remarkably high withstand voltage. Requires a structure. This high withstand voltage structure is
Since the C size increases, and the size increase causes various cost increases, we have developed an oscillating power supply that can obtain a desired waveform with half the breakdown voltage, and have adopted it in various products.

[0005] The swing power supply will be described with reference to FIG. (A)
FIG. 3 is a waveform diagram of the oscillating power supply, and FIG. 3B is a circuit diagram for creating the oscillating power supply. In (A), the upper swing power supply VDD is a square wave that switches between the highest value as the voltage VT and the lowest value as the voltage VM, and the lower swing power supply VSS is
This is a square wave that switches between the highest value as the voltage VM and the lowest value as the voltage −VT, and the upper and lower swing power supplies VDD and VSS are synchronized. This switching is called swinging. The upper and lower swing power supplies VDD and VSS and the voltage VM are supplied to the scan electrode drive IC as power supplies. Although not shown, a start signal FLM (FIRST LI) indicating the start of selection is provided.
NE MARKER), a clock LP (LATCH PULSE) indicating the switching of the selection period, a signal DB indicating the polarity of the selection pulse, and the like are controlled. There are several methods of transmitting the signals FLM, LP, DB, etc. to the scan electrode driving IC operating on the swing power supply system, but the description is omitted. In the oscillating power supply system, the polarity of the selection pulse is given by inverting the logical value of the VM level during the selection period. For example, an output circuit that applies a drive waveform to the scan electrode T1
Since the lower swing power supply VSS and the output terminal are connected during the selection period of the scan electrode T1 and connected to the VM level during the non-selection period, the drive waveform of (B) T1 is obtained. In this case, the VM level is at the high level during the selection period. Similarly, a circuit for outputting a drive waveform to the scan electrode T2 may connect the output terminal to the upper swing power supply VDD during the selection period of the scan electrode T2 (the VM level in the selection period is low). In this manner, positive and negative high voltage selection pulses can be output. However, the scan electrode driving IC has a voltage (VDD-VSS = V
Since only T) is applied, if an oscillating power supply is employed, the IC breakdown voltage can be reduced to half of the selection pulse amplitude.

Some of our products are shown in FIG.
The circuit shown in FIG. 3B is assembled on a printed circuit board to create the above-mentioned swing power supply waveform. The signal DB is input to the resistors R1 and R2 and the capacitors C1 and C2. The other ends of the resistor R1 and the capacitor C1, and the other ends of the resistor R2 and the capacitor C2 are connected to the base of the PNP transistor Q1, respectively.
Connected to the base of NPN transistor Q2. P
The emitters of the NP transistor Q1 and the NPN transistor Q2 are HV and 0V, respectively (circuit ground).
Connect to the collector is common. One ends of the capacitors C3 and C4 are connected to the collectors of the transistors Q1 and Q2, and the other ends are connected to the anode of the diode D1 and the cathode of the diode D2, respectively. The cathode of the diode D1 and the anode of the diode D2 are V
M level.

The resistors R1 and R2 and the capacitors C1 and C2
And the transistors Q1 and Q2 are inverted level shifters, which convert the high level voltage of the signal DB to 0V and the low level voltage to the voltage HV. Since the level-shifted signal is clamped to the lowest voltage at the VM level by the capacitor C3 and the diode D1, the clamped signal becomes the upper power supply VDD of the swing power supply. Similarly, the level-shifted signal is supplied to the capacitor C4 and the diode D2.
, The highest voltage is clamped to the VM level, and the clamped signal becomes the lower power supply VSS of the swing power supply. (The voltage drop in the transistors Q1 and Q2 and the diodes D1 and D2 was ignored. The same applies hereinafter.)

The above-mentioned oscillating power supply has a voltage of + VT, VM, -V
This is an example of three values of T. Depending on the product specifications, two voltages may be used near the ground for driving the liquid crystal to obtain a quaternary value. For example, when there is an upper and lower voltage ± VD of the data signal output from the signal electrode driving IC, (the voltage VM is a voltage + V
D and the voltage −VD), the upper swing power supply VDD is set to the voltage +
VT and the voltage + VD, and the lower swing power supply VSS may be constituted by the voltage -VD and the voltage -VT. This is because when a control signal is sent to the scan electrode driving IC using a gap between the voltage + VD and the voltage −VD as a countermeasure for crosstalk, a diode or a MIM (METAL INSU) is used as a switching element.
It is used for driving an active type liquid crystal panel using a LATER METAL) element.

However, the swing power supply circuit requires many components to be mounted on a circuit board, and a customer unfamiliar with the swing power supply feels that it is difficult to use the swing power supply.
This hindered the spread of swing power supplies. Therefore, in order to make the swing power supply easy to use, a study of circuit integration (IC) has begun. In general, a power supply IC is required to be able to integrate various power supply systems relatively freely and to have high electrical reliability. However, a normal C-MOS integrated circuit is
Since a P-type region (P-well) and an N-type region (N-well) are formed on a common silicon substrate and each region is electrically separated by applying a reverse voltage, the degree of freedom in power supply setting is limited. In addition, a thyristor structure peculiar to a C-MOS transistor is formed, and a phenomenon that a large amount of current flows due to an electric shock (hereinafter, referred to as latch-up) is accompanied. As a countermeasure, a technique of forming an insulating layer on a silicon substrate, forming an island-shaped silicon region on the insulating layer, and forming a circuit in the silicon region (SILICON ON INSULAT).
OR hereinafter referred to as SOI). That is, S
Since the OI can completely separate the P-well region and the N-well region, the region separation by the reverse voltage becomes unnecessary, and the thyristor structure is eliminated. Therefore, an integrated circuit having a high degree of freedom in power supply setting and no latch-up is realized. it can.

[0010]

However, the concept of selecting the voltage + VT, the voltage VM, and the voltage -VT using an analog switch as a swing power supply circuit requires that at least the voltage (2VT) be applied to the IC. Therefore, it is necessary to increase the breakdown voltage, and the problem of increasing the IC size remains. SUMMARY OF THE INVENTION It is an object of the present invention to provide a swing power supply circuit for a liquid crystal panel capable of reducing the size of an IC.

[0011]

SUMMARY OF THE INVENTION In order to achieve the above-mentioned object, the present invention is to form a level shift means for an upper swing power supply and a level shift means for a lower swing power supply on an SOI substrate. A signal indicating a swing timing is input to the level shift means for the swing power supply and the level shift means for the lower swing power supply, and the upper and lower power supplies of the level shift means for the upper swing power supply have the highest selection pulse respectively. And the power supply below and above the level shift means for the lower swing power supply are the minimum voltage of the selection pulse and the voltage near the ground level of the liquid crystal drive, respectively. There is a feature.

[0012]

FIG. 1 is a circuit diagram (A) and a waveform diagram (B) of a first embodiment of the present invention. In FIG. 1A, the power supply 110 is a low-level voltage GND of a signal DB indicating a swing timing, and the power supply 111 is a signal D.
The high-level voltage VDL of B, the power supply 112 is the highest voltage + VT of the upper swing power supply VDD, the power supply 113 is the lowest voltage -VT of the lower swing power supply, and the power supply 114 is output from the signal electrode driving IC. The high-level voltage + VD of the low-voltage data signal, and the power supply 115 is the low-level voltage -VD of the low-voltage data signal. Voltages VDL, GND, + VD,
-VD is a low voltage and is a value near the voltage VM. A low-voltage logic signal DB 107 that determines the swing timing of the swing power supply is input to the level shifter 101 (always a positive signal and an inverted signal are input to the level shifter in the integrated circuit. The inverted signal of the signal DB is also input to the level shifter 101 together with the position signal DB, but the inverted signal is not shown because it is a signal pair.
Hereinafter the same). The upper and lower power supplies of the level shifter 101 are a power supply 112 (voltage + VT) and a power supply 110 (voltage GND).
It is. The level shifter 102 is a level shifter 10
1 is input and the upper and lower power supplies are the power supply 112 (voltage + V
T) and the power supply 114 (voltage + VD). Buffer 10
5, the output of the level shifter 102 is input, and the upper and lower power supplies are a power supply 112 (voltage + VT) and a power supply 114 (voltage + V
In D), the upper swing power supply VDD108 is output. Similarly, the level shifter 103 receives the signal DB 107, and the upper and lower power supplies are a power supply 111 (voltage VDL) and a power supply 113 (voltage -VT). The level shifter 104 receives the output of the level shifter 102, and the upper and lower power supplies 115
(Voltage-VD) and the power supply 113 (voltage-VT). The buffer 106 receives the output of the level shifter 104, and the upper and lower power supplies are a power supply 115 (voltage −VD) and a power supply 11.
At 3 (voltage-VT), the lower swing power supply VSS109 is output. Level shifters 101 and 102 and buffer 105
Is a level shift means for the upper swing power supply, and the level shifters 103 and 104 and the buffer 106 are level shift means for the lower swing power supply.

In FIG. 1A, a level shifter 101 is shown.
Means that the high level and the low level are the voltages + VT and G, respectively.
The voltage of the signal DB is converted to be ND. Subsequently, the level shifter 102 converts the output of the level shifter 101 into a voltage so that the low level becomes the voltage + VD. The buffer 105 performs impedance conversion of the output of the level shifter 102. By this process, the signal DB becomes the upper swing power supply V
It is converted to DD108. Similarly, the level shifter 103
Means that the high level and the low level are the voltages VDL and −, respectively.
The voltage of the signal DB is converted so as to be VT. Subsequently, the level shifter 104 converts the output of the level shifter 101 into a voltage so that the high level becomes the voltage −VD. The buffer 106 performs impedance conversion of the output of the level shifter 104. By this process, the signal DB becomes lower swing power supply V
Converted to SS109.

In FIG. 1B, the signal DB has a high-level voltage VDL and a low-level voltage GND, and if the voltage GND is 0V, the voltage VDL becomes 1.5.
This is a normal logic signal of about V to 5V. Voltage + V
T varies depending on the number of divisions of the liquid crystal panel and the threshold value, but in many cases is about 10 V to 30 V. Similarly, the voltage -VT is -1.
It is about 0V to 30V. Data signal voltage ± VD also ±
It is about 1V to ± 3V. The upper oscillating power supply VDD oscillates in synchronization with the signal DB with the highest value being the voltage + VT and the lowest value being the voltage + VD. Similarly, the lower voltage VSS oscillates in synchronization with the signal DB with the highest value being the voltage -VD and the lowest value being the voltage -VT. The voltage VM serving as the ground level for driving the liquid crystal exists between the voltage + VD and the voltage -VD.

In this embodiment, the level shifters 101, 102, 103, 104 and buffers 105, 1 of FIG.
06 is formed on the SOI substrate. Level shifter 1
01 indicates that the power supply is the power supply 112 (voltage + VT) and the power supply 110
(Voltage GND), the element withstand voltage is equal to the voltage (+ VT−GN).
D) It suffices if it is at least. Since the voltage GND and the voltage + VD are close to each other, the element withstand voltages of the level shifter 102 and the buffer 105 are set to be the same as those of the level shifter 101. The element withstand voltage of the level shifters 103 and 104 and the buffer 106 is equal to or higher than the voltage (VDL − (− VT)).
Since ND and voltage VDL have substantially the same value, each element is formed independently because of the SOI structure. Therefore, the withstand voltage of all elements is designed using the voltage (+ VT−GND) or more as a guide.

FIG. 2 is a transistor-level circuit diagram of the first embodiment of the present invention shown in FIG.
Represents level shifters 101 and 102, (B) represents level shifters 103 and 104, and (C) represents buffers 105 and 106.
Corresponding to In FIG. 2A, P-channel transistors 201 and 202 and an N-channel transistor 203 are connected in series. Since the P-channel transistors 201 and 202 are separated because of the SOI structure, each substrate is connected to each source (hereinafter, the substrate is connected to the source of the transistor itself in FIG. 2). . Similarly, P-channel transistors 204 and 205 and an N-channel transistor 206 are also connected in series. The positive signal IN209 is input to the gates of the transistors 201 and 203, and the inverted signal INB210 is input to the gates of the transistors 204 and 206. Transistor 2
The point at which the gate of the transistor 02 and the drains of the transistors 205 and 206 are connected becomes the positive output OUT211. The gate of the transistor 205 and the transistors 202 and 20
The point to which the drain of No. 3 connects is the inverted output OUTB212. The normal signal IN209 of the level shifter 101 is a signal DB, the inverted signal 210 is an inverted signal of the signal DB, and the normal and inverted outputs OU of the level shifter 101 are output.
T211 and OUTB212 are level shifters 1 respectively.
02 and the inverted signals IN and INB. The upper power supply 207 is at the voltage + VT, while the lower power supply is
The level shifter 101 in FIG. 7A has a voltage GND, and the level shifter 102 has a voltage + VD. The level shifter 101 and the level shifter 102 have the same breakdown voltage and connection relationship of the transistors, but have different parameters such as the gate size because the input signal voltage is different.

FIG. 2B also shows a P-channel transistor 221 and an N-channel transistor 22.
2,223, P-channel transistor 224 and N
The channel transistors 225 and 226 are connected in series, and the positive signal IN229 is output from the transistor 221.
223 and the inverted signal INB230 is input to the gates of the transistors 224 and 226. The gate of the transistor 222 and the transistors 224 and 2
The point where the drain of the transistor 225 is connected is the positive output OUT231, and the point where the gate of the transistor 225 is connected to the drains of the transistors 221 and 222 is the inverted output OU.
TB232. Normal signal I of level shifter 103
N229 is the signal DB, and the inverted signal 230 is the signal DB
And the inverted outputs OUT231 and OUTB232 of the level shifter 103 become the inverted and inverted signals IN and INB of the level shifter 104, respectively. The lower power supply 228 has a voltage -VT, while the upper power supply has a voltage VDL in the level shifter 103 and a voltage -VD in the level shifter 104. Level shifter 10
3 and the level shifter 104 have the same transistor breakdown voltage and connection relationship, but have different input signal voltages and different parameters such as gate size.

In FIG. 2C, a two-stage inverter is constituted by P-channel transistors 241 and 243 and N-channel transistors 242 and 244. The input signal terminal IN247 is connected to transistors 241 and 242.
And the drains of the transistors 243 and 244 are output terminals OUT248. Upper and lower power supply 24
5 and 246 are the voltages + VT and + VD in the case of the buffer 105 of FIG. 1A, and are the voltages -VD and -VT in the case of the buffer 106.

FIG. 3 is a circuit diagram of a second embodiment of the present invention. The signal DB303 that determines the phase of the swing power supply is
After the minimum voltage is clamped to the voltage + VD by the capacitor 310, the diode 311, and the resistor 312, it is input to the comparator 301 (an inverted signal is omitted in FIG. 3 as in FIG. 1A). Power supply 30 above and below comparator 301
6, 307 are a voltage + VT and a voltage + VD, respectively.
The output 304 is the upper swing power supply VDD. Similarly, the signal DB 303 includes the capacitor 313 and the diode 31
4. After the highest voltage is clamped to the voltage −VD by the resistor 315, the voltage is input to the comparator 302. Comparator 3
01, the upper and lower power supplies 308 and 309 respectively have a voltage −VD
And the voltage −VT, and the output 305 becomes the lower swing power supply VSS. If the resistances 312 and 315 have a large value, the capacitors 310 and 313 need only have a small capacity. Therefore, the capacitors 310 and 313, the diodes 311 and 314, and the resistors 312 and 315 can be formed in an IC. If a clamp circuit is used, only one level shifter is required for each of the upper and lower swing power supplies. If the scan electrode driving IC and the display panel can be handled as a small load, the buffers 105 and 106 according to the first embodiment can be omitted. Up and down level shift means were created with a clamp circuit and a level shifter.

[0020]

As described above, according to the present invention, the voltage range applied to the comparator and the buffer for creating the upper swing power supply is about the voltage (+ VT-GND), and the lower swing power supply is created. The voltage range applied to the comparator and the buffer for performing the operation is the voltage (VDL − (− VT)), and each voltage range corresponds to the amplitude of the selection pulse (2VT).
, The element withstand voltage can be reduced to about half of the selection pulse amplitude, and the size of the IC can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram (A) of a first embodiment of the present invention.
And a waveform diagram (B).

FIG. 2 is a transistor-level circuit diagram according to the first embodiment of the present invention.

FIG. 3 is a circuit diagram according to a second embodiment of the present invention.

FIG. 4 is a schematic diagram (A) and a waveform diagram (B) of a conventional liquid crystal panel.

5A and 5B are a waveform diagram (A) and a circuit diagram (B) of a conventional swing power supply.

[Explanation of symbols]

101, 102, 103, 104, 301, 302
Level shifters 105 and 106 Buffers 108 and 304, swing power supplies 109 and 305 on the upper side of VDD, swing power supplies 107 and 303 on the lower side of VSS, signals 112, 207 and 306 indicating the timing of DB swing, and the maximum value of the + VT selection pulse. 110, the low level voltage 111 of the GND signal DB, the high level voltage 114 of the VDL signal DB, the high level voltage 115 of the + VD data signal, the low level voltage 113 of the −VD data signal 113, 228, 309, and the −VT selection pulse. Minimum voltage

Continued on the front page F term (reference) 2H093 NA07 NC04 NC09 ND38 ND52 NH13 5C006 AC02 AC25 AC26 AF51 AF78 BB11 BF14 BF34 BF42 BF43 EB05 FA41 5C080 AA10 BB05 DD25 EE25 FF01 FF09 JJ02 JJ03 JJ04

Claims (1)

[Claims] 1. A low-voltage data signal waveform is applied to a signal electrode of a liquid crystal panel around a ground level of liquid crystal driving,
A drive system for applying a high-voltage positive or negative selection pulse to a scan electrode at the time of selection, wherein a power supply of a scan electrode drive circuit for generating the selection pulse is a swing power supply for a liquid crystal panel. In the circuit, a level shift means for the upper swing power supply and a level shift means for the lower swing power supply are formed on the SOI substrate, and the level shift means for the upper swing power supply and the level for the lower swing power supply are formed. A signal indicating swing timing is input to the shift means, and the upper and lower power supplies of the level shift means for the upper swing power supply are supplied with the voltage of the highest value of the selection pulse and the ground voltage near the ground level of the liquid crystal drive, respectively. And the lower and upper power supplies of the level shift means for the lower swing power supply are a voltage of a minimum value of the selection pulse and a voltage near a ground level of the liquid crystal drive, respectively. Oscillating power supply circuit of that the liquid crystal panel.