JP2001265297A - Scanning line driving circuit and planar display device having the same circuit and its driving method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a scanning line driving circuit capable of stably operating a planar display device by stably operating level shifter circuits. SOLUTION: This canning line driving circuit is constituted of a timing circuit part to which voltage is supplied from a voltage supplying source, a level shifter circuit part 101 generating voltage driving pixel switching elements, a plurality of gate voltage sources for connecting the voltage supplying source to the level shifter part and a gate buffer part 102 supplying the output of the circuit part 101 to scanning lines. Moreover, the circuit part 101 is a part in which flip-flop type level shifter circuits performing level shifts for every gate voltage source are connected in series and transistors to be controlled by a power source detecting circuit 103 are arranged in parallel with respect to outputs from respective level shifter circuits.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flat display device with a built-in drive circuit, in which a scanning line drive circuit and a signal line drive circuit are integrated on an insulating substrate simultaneously with a pixel TFT, and a method of driving the same.

[0002]

2. Description of the Related Art An active matrix type liquid crystal display device (hereinafter abbreviated as AM-LCD) using a semiconductor switching element is one of the liquid crystal display devices which are flat display devices. 2. Description of the Related Art A thin film transistor type liquid crystal display device (hereinafter abbreviated as TFT-LCD) using a thin film transistor (hereinafter abbreviated as a TFT) formed of a polycrystalline silicon thin film as a switching element has been actively developed.

[0003] This TFT-LCD uses a semiconductor switching element provided on a transparent insulating substrate made of glass or the like, for example, to control the voltage applied to the liquid crystal of one pixel, and is characterized by a clear image quality. Has,
It is widely used as a graphic display for OA equipment terminals and television screens.

In recent years, an integrated circuit for a scanning line driving circuit and a signal line driving circuit has been replaced with a well-known method of disposing the integrated circuit outside a transparent insulating substrate of a liquid crystal display element, and is integrally formed on a transparent insulating substrate simultaneously with a pixel TFT. Drive circuit built-in TFT-LCD
Is being developed. In order to realize such a configuration, a TFT using polycrystalline silicon (hereinafter referred to as p-Si
TFT).

[0005] As shown in FIG.
It comprises a timing circuit 2A constituted by a shift register, a level shifter circuit 2B for shifting a logic system power supply voltage to an operation voltage of a pixel TFT, and a buffer circuit 2C corresponding to a scanning line load.

[0006] Today, a driving circuit built-in type TFT, in which a scanning line driving circuit is integrated on a transparent insulating substrate together with a pixel TFT, is used.
LCD panels are being developed with the goal of increasing size and higher definition.

[0007] As the panel size increases as the size increases, the scanning lines also become longer. Further, since the scanning line driving pulse width is shortened by aiming at high definition, the horizontal blanking time is also shortened.

Further, as the length of the scanning line increases, the resistance and capacitance of the scanning line increase, and the scanning line driving pulse delay increases.

Due to these factors, poor image quality such as uneven brightness occurs in the scanning line direction.

Therefore, in order to increase the definition of the display device, it is necessary to reduce the load on the scanning lines and to reduce the scanning line driving pulse delay.

As a countermeasure against this problem, as shown in FIG. 11, a scanning line driving circuit is provided on one side of the display panel for one scanning line in the same panel size.
The case where the scanning line driving circuit is constituted by only one side supplying the driving pulse from one scanning line driving circuit over the entire length of the scanning line, and the case where the scanning line driving circuit is provided on two opposite sides of the display panel and When a scanning line driving circuit that supplies a driving pulse is configured, the pulse delay difference at a place where the delay of the scanning line driving pulse is the largest is that the scanning line resistance load is reduced by half and the scanning line capacitance load is reduced by half in both-side driving. Therefore, the scanning line load is one-fourth that of one-side drive.

As described above, there is an attempt to reduce the delay of the scanning line driving pulse by arranging the scanning line driving circuits on both sides of the panel with the aim of increasing the size and definition of the panel.

[0013]

As described above, it is effective to drive the scanning lines from both sides of the display panel in order to increase the size of the display panel and to increase the definition. The magnitude of the scanning line driving pulse output by the scanning line driving circuit (one scanning line driving circuit and the other scanning line driving circuit) never becomes different in potential (magnitude) stochastically. If different potentials are output, a current flows from the high voltage side to the low voltage side between the scanning line driving circuits on both sides, increasing power consumption or damaging the driving circuit. I understand that there is.

Further, the reason why the scanning line driving pulses output different potentials between the scanning line driving circuits on both sides is that the level shifter circuit among the block circuits shown in FIG. 10 becomes unstable when the power is turned on. I understand.

SUMMARY OF THE INVENTION An object of the present invention has been made in response to the above-mentioned technical problem, and it is possible to obtain a good display image on a large, high-definition flat display device without damaging a circuit. An object of the present invention is to provide a scanning line driving circuit and a driving method thereof.

[0016]

SUMMARY OF THE INVENTION The present invention has been made based on the above-mentioned problems, and comprises a plurality of scanning lines and a plurality of video signal lines orthogonal to the scanning lines. A scanning line driving circuit for supplying a scanning line driving signal for driving a scanning line to each of the scanning lines of the active matrix type liquid crystal display device having an image switching element connected to a signal line; The circuit is the first
A voltage source, a plurality of gate voltage sources, a power supply detection circuit, a transistor controlled by the power supply detection circuit, a timing generation circuit supplied with a voltage from the first voltage source, the first voltage source and the plurality of A level shifter circuit that is connected to the gate voltage source and generates a voltage for driving the pixel switching element; and a gate buffer that supplies an output voltage output from the level shifter circuit to the scan line. A flip-flop type level shifter circuit for shifting a level is connected in series for each of the individual gate voltage sources, and the transistors are arranged in parallel at an output of the level shifter circuit. A scanning line driving circuit is provided.

The present invention also provides an active matrix type comprising a plurality of scanning lines and a plurality of video signal lines orthogonal to the scanning lines, wherein an image switching element connected to the scanning lines and the video signal lines is formed. In a power-on sequence of a scanning line driving circuit that supplies a scanning line driving signal for driving a scanning line to each of the scanning lines of the liquid crystal display device, the scanning line driving circuit includes a first voltage source and a plurality of gates. A voltage source, a power supply detection circuit, a transistor controlled by the power supply detection circuit, a timing generation circuit to which a voltage is supplied from the first voltage source, and connected to the first voltage source and a plurality of gate voltage sources. A level shifter circuit that generates a voltage for driving the pixel switching element, and a gate buffer that supplies an output voltage output from the level shifter circuit to the scanning line. The first voltage source that enables the operation of the timing generation circuit is turned on, the individual gate voltages are turned on in the same order as the order of series connection of the level shifter circuits, and the level is set for each individual gate voltage. And a power-on sequence of the scanning line driving circuit.

Further, the present invention relates to a scanning line driving circuit for sequentially outputting scanning pulses including a high level and a low level voltage to a plurality of scanning lines, a first and a second level shifter circuit connected in series to each other, A first and a second transistor connected in parallel to outputs of the first and the second level shifter circuits; and a power supply detecting circuit for controlling the first and the second transistors. A scanning line driving circuit is provided.

Still further, according to the present invention, there are provided a plurality of signal lines and scanning lines, a pixel electrode electrically connected to the signal lines via switch elements connected to the scanning lines, and both ends of the scanning lines. , A first and a second scanning line driving circuit for sequentially outputting a scanning pulse including a high level and a low level voltage, wherein the first level shifter circuit generates the first reference voltage by the first level shifter circuit. A method for driving a flat panel display device, characterized in that when the level is shifted to one voltage and the level of the second reference voltage is shifted to the second voltage by the second level shifter circuit, the operation of the second level shifter circuit is controlled. Is what you do.

[0020]

Embodiments of the present invention will be described below in detail with reference to the drawings. The embodiment described below is merely one of preferred examples, and the scope of the present invention is not limited to the embodiment.

As shown in FIG. 1, the liquid crystal display device 1 is a light transmission type liquid crystal display device (p-SiTFT-LCD) having a diagonal size of 15 inches using a polycrystalline silicon TFT as a pixel TFT. Yes, array substrate 10
And an opposing substrate 20 opposing the array substrate 10 at a predetermined distance from the array substrate 10, and a liquid crystal layer 30 interposed between the two substrates with an alignment film (not shown) interposed therebetween. The array substrate 10 and the opposing substrate 20 form a sealed space with a sealing material 40 provided around the array substrate 10 and hold the liquid crystal layer 30.

The array substrate 10 includes a plurality of gate (scanning) lines Y extending in the row direction, a plurality of signal lines X extending in the column direction, a scanning line Y and a signal line X. And a pixel thin film transistor, ie, a pixel TFT 11, which is a switching element provided at each intersection with the pixel electrodes 12, and a pixel electrode 12 provided for each pixel surrounded by individual scanning lines Y and signal lines X.

The gate electrode of the pixel TFT 11 has a scanning line Y
, And the source electrode is connected to the signal line X. The drain electrode is a pixel electrode 12 and a pixel electrode 12.
Are connected in parallel to the auxiliary capacitance electrode lines that provide the auxiliary capacitance 13. The pixel electrode 12
Is connected to the opposing electrode 21 of the opposing substrate 20.

A scanning line driving circuit 14 for driving the scanning line Y
a and 14b are formed by the same process as the pixel TFT 11
On the array substrate 10, it is formed integrally with the array substrate 10 on two sides facing each other (in a direction parallel to the signal line X).

Signal line drive circuit 15 for driving signal line X
Are a plurality of signal line driving ICs 51 provided by a TCP (tape carrier package) 50 which is a flexible wiring substrate, and a selection circuit 17 which functions as selection means formed on the array substrate 10 in the same process as the pixel TFT 11. It is constituted by and.

A PCB board 60 as an external circuit board is connected to the side of the TCP 50 opposite to the array board 10. On the PCB board 60, based on a reference clock signal input from outside or a digital data signal,
A control IC 61 that outputs various control signals and data signals synchronized with the control signals, a power supply circuit, and the like are provided.

FIGS. 2A and 2B and FIGS. 3A and 3B respectively show the p-Si TFT-L shown in FIG.
A scanning line driving circuit 14a, 1 for driving the scanning line Y of CD1
FIG. 4 is a schematic diagram illustrating a level shifter circuit incorporated in 4b and a sequence when the power is turned on. Note that FIG.
As shown in FIG. 3B and FIG. 3B, each of the level shifter circuits is a two-stage level shifter.

As described above, a technique has been proposed in which scanning line driving circuits are provided on two opposing sides of a display panel and scanning lines are driven from both sides of the display panel. It is known that the scanning line driving pulses output from the line driving circuit have different magnitudes. This is because the operation of the level shifter circuit in the drive circuit becomes unstable when the power is turned on. Therefore, the present invention is achieved by controlling the operation of the level shifter when the power is turned on.

That is, as shown in FIGS. 2A and 3A, when the power is turned on, the order in which the level shift circuits of each stage perform level shifts in order to stabilize the potential output from each output line is as follows. Each is a reference voltage VSS which is a logic low level, for example, 0V, and a reference voltage VDD which is a logic high level pulse, for example, + 10V.
Is assumed to have risen, the level of the pixel TFT is shifted to an on level, for example, the voltage GVDD of +15 V, and the reference voltage VSS is shifted to the off level of the pixel TFT, for example, to the voltage GVSS of -2 V.

More specifically, the GVD as shown in FIG.
The sequence in which D rises first is obtained by the configuration shown in FIG.

More specifically, the first-stage level shifter 10
1, GVDD is generated by shifting the level of the reference voltage VDD, which is a high-level pulse of the logic system, and the pixel T
By shifting the level to the ON level of the FT, FIG.
As shown in the center of the figure, GVDD rises, and the second-stage level shifter 102 shifts the level of the reference voltage VSS, which is a low-level pulse of the logic system, to generate GVSS and shifts the level to the off level of the pixel TFT. Thus, as shown in the lower part of FIG. 2A, GVSS is obtained.

Similarly, the GVSS shown in FIG.
Is obtained by the configuration shown in FIG. 3B.

More specifically, the first-stage level shifter 20
1, the reference voltage VSS, which is a logic low-level pulse, is level-shifted to generate GVSS, and the pixel TF
GVSS is generated as shown in the lower part of FIG. 3A by level-shifting to the OFF level of T, and the second-stage level shifter 202 shifts the level of the reference voltage VDD, which is a logic high-level pulse, to GVDD. By generating and shifting the ON level of the pixel TFT, FIG.
GVDD can be obtained as shown in the center of (a).

FIG. 4 is a schematic diagram showing an example of a circuit applicable to the first-stage level shifter 101 of the two-stage level shifter shown in FIG. 2B.

As shown in FIG. 4, when the logic system power supply, that is, the reference voltages VDD and VSS are raised, an NchTF
T is added, and the PchTFT of the second level shift circuit
Is turned on to control to output an on-level voltage of the pixel TFT that rises first.

FIGS. 5 and 6A to 6C are schematic diagrams showing an example of a two-stage level shifter circuit incorporating the first-stage level shifter shown in FIG. 4 and a driving method (sequence) thereof.

The two-stage level shifter shown in FIG. 5 is a step-up shift in which the first-stage level shifter 101 shifts the level of the reference voltage, and a depressurization shift in which the second-stage level shifter shifts the level of the reference voltage. When VDD is supplied in the circuit configuration shown in FIG.
A voltage supply sequence as shown in FIG.
6B) when the input In is equal to the reference voltage VSS as shown in FIGS. 6B and 6C.
By the respective outputs of the points A to F as shown in FIG. 6B, and when the input In is equal to the reference voltage VDD, the respective outputs of the points A to F as shown in FIG. Thus, the sequence shown in FIG. 6A, that is, the sequence shown in FIG. 2A is achieved. That is, when the two-stage level shifter shown in FIG. 5 is used, the operation starts when the voltage (GVDD) which rises first based on the logic system reference voltage becomes stable, and the level-shifted voltage (GVDD)
D, GVSS) are output.

It should be noted that the power supply detection circuit 103 operates from a reference voltage (VDD or VSS) until each input power supply (GVDD, GVSS) is turned on from an external power supply until the input power supply becomes stable.
S), a reference voltage (VDD or VSS), an input power supply (GVDD, G
There is a method of configuring a circuit that controls until VSS is stabilized by a comparison circuit in the scanning line driving circuit.

FIG. 7 is a schematic diagram showing an example of a circuit applicable to the first-stage level shifter 201 of the two-stage level shifter shown in FIG.

As shown in FIG. 7, when the logic power supply, that is, the reference voltages VDD and VSS are raised, the PchTF
T is added, Nch TFT of the second level shift circuit
Is turned on to control to output an off-level voltage (GVSS) of the pixel TFT that rises first.

FIGS. 8 and 9A to 9C are schematic diagrams showing an example of a two-stage level shifter circuit incorporating the first-stage level shifter shown in FIG. 7 and a driving method (sequence) thereof.

The two-stage level shifter shown in FIG. 8 is a depressurizing shift in which the first-stage level shifter 201 shifts the level of the reference voltage and a boosting shift in which the second-stage level shifter shifts the level of the reference voltage. Assuming that VDD is supplied by the circuit configuration shown in FIG. 8, the voltage supply sequence (same as FIG. 3A) as shown in FIG. 9A is equivalent to FIGS. 9B and 9C. As shown in FIG. 9B, when the input In is equal to the reference voltage VDD, the input In is equal to the reference voltage VSS as shown in FIG. 9A, the sequence shown in FIG. 9A, that is, the sequence shown in FIG. 3A is obtained by the respective outputs of the points A to F as shown in FIG. 9C. That is, when the two-stage level shifter shown in FIG. 7 is used, the operation starts when the voltage (GVSS) which rises first based on the logic system reference voltage becomes stable. In this case, the level-shifted voltage (GVSS) is used. , GVDD) are output.

Note that the power supply detecting circuit 203 operates from the input of each input power supply (GVDD, GVSS) from an external power supply until the reference voltage (VDD or VSS) is stabilized.
S), a reference voltage (VDD or VSS), an input power supply (GVDD, G
There is a method of configuring a circuit that controls until VSS is stabilized by a comparison circuit in the scanning line driving circuit.

As described above, according to the scanning line driving circuit of the present invention, the transistors are arranged in parallel between the output lines after the first-stage level shift of the two-stage level shifter circuit in the scanning line driving circuit. So, the transistor O
The operation of the level shifter circuit is stabilized by using the N resistor as the pull-up resistor and the pull-down resistor.

Further, a two-stage level shifter circuit that shifts a level from a logic system reference voltage in the scanning line driving circuit to a high level voltage and a low level voltage used for a scan pulse of a pixel TFT is a logic system high level pulse. A circuit that shifts the reference voltage (VDD) from the reference voltage (VDD) to the ON level of the pixel TFT (shifts GVDD) and a circuit that shifts the reference voltage (VSS), which is a logic low-level pulse, from the reference voltage (VSS) to the OFF level of the pixel TFT (Move GVSS), and the level shifter circuit can be operated stably by arranging the level shift circuit and setting the startup sequence at the time of turning on the power corresponding to the arrangement.

Further, when the on-level voltage (GVDD) of the pixel TFT is first raised and then the off-level voltage (GVSS) of the pixel TFT is raised, the first-stage level shift is performed by a logic high-level pulse. From the reference voltage, which is the on-level voltage of the pixel TFT (GVDD)
By arranging Nch TFTs in parallel on each level shift output line of the first stage, stable start-up is possible.

Furthermore, when the off-level voltage (GVSS) of the pixel TFT is first raised and then the on-level voltage (GVDD) of the pixel TFT is raised, the first-stage level shift is performed by the logic low level. The off-level voltage of the pixel TFT (GVS
In the configuration of S), a Pch TFT is arranged in parallel with each level shift output line of the first stage,
Stable startup is possible.

As described above, in the present embodiment, the order of level shift is changed in accordance with the power-on sequence, and transistors are arranged in parallel with each output line whose level has been shifted in the first stage. Stable operation can be guaranteed. Further, the circuit configuration can be achieved by a predetermined combination and the addition of a few elements, so that the price does not increase.

[0049]

As described above, according to the present invention, in the two-stage level shifter circuit in the scanning line driving circuit, transistors are arranged in parallel between the output lines shifted by one stage, and the transistors are arranged in parallel. The signal to be controlled is turned on until each power supply rises, and turned off when the power supply rises, thereby stabilizing the operation of the level shifter circuit, thereby suppressing generation of an undesired voltage when the power is turned on. The drive circuit and the flat panel display can be prevented from being damaged.

When the power is turned on, the voltage output from the scanning line driving circuit is stabilized, so that a flat display device such as a liquid crystal display device capable of displaying a large and high-definition image can be driven at a high speed. A scanning line driving circuit is provided.

Thus, a large, high-definition image can be obtained.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view illustrating an example of a liquid crystal display device (flat display device) to which a scanning line driving circuit according to an embodiment of the present invention is applied.

FIG. 2 shows a level shifter circuit incorporated in a scanning line driving circuit for supplying a scanning line driving signal to a scanning line of the liquid crystal display device shown in FIG. 1, and GVDD and GVSS which are driving currents for driving each TFT. FIG. 3 is a schematic diagram illustrating a sequence at the time of power-on for providing.

FIG. 3 shows a level shifter circuit incorporated in a scanning line driving circuit for supplying a scanning line driving signal to the scanning lines of the liquid crystal display device shown in FIG. 1, and GVDD and GVSS which are driving currents for driving each TFT. FIG. 3 is a schematic diagram illustrating a sequence at the time of power-on for providing.

FIG. 4 is a schematic diagram showing an example of a circuit applicable to the first-stage level shifter of the two-stage level shifter shown in FIG. 2B;

5 is a schematic diagram illustrating an example of a configuration of a two-stage level shifter including the first-stage level shifter illustrated in FIG. 4;

6 is a schematic diagram illustrating a sequence for driving the level shifter shown in FIG.

FIG. 7 is a schematic diagram showing an example of a circuit applicable to the first-stage level shifter of the two-stage level shifter shown in FIG.

8 is a schematic diagram illustrating an example of a configuration of a two-stage level shifter including the first-stage level shifter illustrated in FIG. 7;

FIG. 9 is a schematic diagram illustrating a sequence for driving the level shifter illustrated in FIG. 7;

FIG. 10 is a schematic diagram illustrating an example of a configuration of a scanning line driving circuit used as a known scanning line driving circuit.

11 is a schematic diagram illustrating an example of a known display panel in which the known scanning line driving circuit illustrated in FIG. 10 is provided on two sides and a known display device using the same.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Liquid crystal display device, 10 ... Array substrate, 11 ... Pixel TFT, 12 ... Pixel electrode, 13 ... Auxiliary capacitance, 14a ... Scan line drive circuit, 14b ... Scan Line drive circuit, 15 ... signal line drive circuit, 20 ... counter substrate, 21 ... counter electrode, 30 ... liquid crystal material, 101 ... level shifter, 102 ... level shifter, 103 ... Power supply detection circuit, 201: Level shifter, 202: Level shifter, 203: Power supply detection circuit.

Claims (11)

[Claims] An active matrix liquid crystal display device comprising a plurality of scanning lines and a plurality of video signal lines orthogonal to the scanning lines, wherein an image switching element connected to the scanning lines and the video signal lines is formed. A scanning line driving circuit for supplying a scanning line driving signal for driving a scanning line to each of the scanning lines, wherein the scanning line driving circuit comprises: a first voltage source; a plurality of gate voltage sources; A transistor controlled by the power supply detection circuit, a timing generation circuit to which a voltage is supplied from the first voltage source, and connected to the first voltage source and a plurality of gate voltage sources to drive the pixel switching element And a gate buffer that supplies an output voltage output from the level shifter circuit to the scanning line. The level shifter circuit A scan, wherein a flip-flop type level shifter circuit for shifting a level is connected in series for each of the individual gate voltage sources, and the transistors are arranged in parallel at an output of the level shifter circuit. Line drive circuit. 2. An active matrix type liquid crystal display device comprising: a plurality of scanning lines; and a plurality of video signal lines orthogonal to the scanning lines, wherein an image switching element connected to the scanning lines and the video signal lines is formed. In the power-on sequence of a scanning line driving circuit that supplies a scanning line driving signal for driving a scanning line to each of the above scanning lines, the scanning line driving circuit includes a first voltage source, a plurality of gate voltage sources, A power supply detection circuit, a transistor controlled by the power supply detection circuit, a timing generation circuit supplied with a voltage from the first voltage source, and a pixel connected to the first voltage source and a plurality of gate voltage sources. A level shifter circuit that generates a voltage for driving a switching element; and a gate buffer that supplies an output voltage output from the level shifter circuit to the scanning line. Turning on the first voltage source that enables the operation of the timing generator circuit, turning on the individual gate voltages in the same order as the serial connection of the level shifter circuits, and shifting the level for each individual gate voltage. A power-on sequence of the scanning line driving circuit. 3. The scanning line driving circuit according to claim 1, wherein said scanning line driving circuit includes a thin film transistor using polycrystalline silicon. 4. The scanning line driving circuit according to claim 1, wherein said scanning line driving circuit is formed simultaneously with said pixel switching element. 5. A scanning line driving circuit for sequentially outputting scanning pulses including a high level and a low level voltage to a plurality of scanning lines, comprising: a first and a second level shifter circuit connected in series with each other; And a first and a second transistor connected in parallel to the output of the second level shifter circuit, and a power supply detection circuit for controlling the first and the second transistors. circuit. 6. The first and second level shifter circuits further comprising: a first level shifter circuit which boosts an input first voltage to the high level voltage;
2. The scanning line drive circuit according to claim 1, wherein the second level shifter circuit is connected to reduce the voltage to the low level voltage. 7. The scanning line driving circuit according to claim 2, wherein said transistors include N-channel transistors. 8. The first and second level shifter circuits, wherein the first level shifter circuit reduces the input first voltage to the low level voltage, and then the second level shifter circuit inputs the second voltage.
2. The scanning line drive circuit according to claim 1, wherein the second level shifter circuit is connected to boost the voltage to the high level voltage. 9. The scanning line driving circuit according to claim 8, wherein said transistors include P-channel transistors. 10. A plurality of signal lines and scanning lines, a pixel electrode electrically connected to the signal line via a switch element connected to the scanning line, and high-level and low-level signals arranged at both ends of the scanning line. A first and second scanning line driving circuit for sequentially outputting scanning pulses including a low level voltage, wherein the first level shifter circuit changes the first reference voltage to the first voltage by the first level shifter circuit. A driving method of the flat display device, wherein the operation of the second level shifter circuit is controlled when the second reference voltage is shifted to the second voltage by the second level shifter circuit. 11. The system according to claim 1, wherein said second level shifter circuit is operated based on said first voltage.
Item 9. The method for driving a flat panel display device according to Item 0.