KR20040086516A - Shift register and display apparatus having the same - Google Patents

Abstract

PURPOSE: A shift register and a display device having the same are provided to reduce the number of external bus lines. CONSTITUTION: The shift register includes a plurality of stages generating a gate signal to a plurality of gate lines of a display device in sequence. According to each stage, the first pull-up driver(230) generates the first control signal in response to an output signal or a control signal of a prior stage. A pull-up unit(210) generates an output signal of a current stage in response to the first power clock and the first control signal. The second pull-up driver(250) generates the second control signal in response to the first power clock and the second power clock. And the third pull-up driver(240) drives in response to the output signal of a following stage by being connected to a low level port.

Description

SHIFT REGISTER AND DISPLAY APPARATUS HAVING THE SAME

The present invention relates to a shift register and a display device having the same, and more particularly, to a shift register and a display device having the same for reducing the number of external bus lines.

In recent years, the liquid crystal display device is equipped with a gate driving IC by a method such as a tape carrier package (TCP) or a chip on glass (COG), but the structure of the product is limited in terms of manufacturing cost or mechanical design.

In order to overcome the above limitations, a structure that does not employ the gate driving IC (hereinafter referred to as a GATE IC-Less structure) is devised, which is a circuit using an amorphous-silicon thin film transistor (hereinafter referred to as a-Si TFT). To do the same thing.

An a-Si TFT circuit for this purpose is disclosed in US Patent No. 5,517,542, as well as Korean Patent Application No. 2002-3398 (Publication No. 2002-66962) filed by the present applicant. The gate driving circuit having the GATE IC-Less structure includes one or more shift registers and provides a scan signal to the liquid crystal display panel.

Fig. 1 is a circuit diagram for explaining a conventional shift register, and specifically illustrates a stage of a shift register operating with a gate driving IC disclosed in Patent Application No. 2002-3398.

Referring to FIG. 1, each stage 100 of the shift register includes a pull-up part 110, a pull-down part 120, a pull-up driving part 130, and a pull-down. The driver may include a pull-down driving part 140 to output a gate signal (or scan signal) based on a scan start signal STV or an output signal of a previous stage. In this case, when the stage is the first stage of the shift register, a gate signal is output based on the scan start signal STV provided from a timing controller (not shown), and in the case of the remaining stages, the gate signal is output from the previous stage. Output the gate signal. The shift register is integrated in the TFT panel to perform an operation such as a gate driving circuit.

FIG. 2 is a diagram for explaining the gate driving circuit according to FIG. 1.

1 and 2, there are N stages in the gate driving circuit 174 which outputs N gate signals (or scan signals) GOUT [1], GOUT [2], ... GOUT [N]. (SRC [1], SRC [2], ... SRC [N]) and a dummy stage SRC [N + 1] for providing a control signal to the previous stage. Each of the stages SRC [1], SRC [2], ... SRC [N] has a first power clock CKV, a second power clock CKVB, and a gate-on voltage from the output of the next stage. The high level voltage VDD, which is VON, the ground level voltage VSS, which is a gate-off voltage VOFF, and a control signal are provided.

In particular, the first stage receives the scan start signal STV provided from a timing controller (not shown) together with the signals and outputs a first gate signal GOUT [1] for selecting a first gate line. The first gate signal GOUT [1] is output to the input terminal IN of the second stage. The second stage SRC [2] receives the first gate signal GOUT [1] provided from the previous stage together with the signals to receive the second gate signal GOUT [2] for selecting the second gate line. Output The second gate signal GOUT [2] is output to the input terminal IN of the third stage. In the same manner, the N-th stage SRC [N] and the control signal provided from the second power clock CKVB, the voltage VON / VOFF, and the dummy stage SRC [N + 1] and N-1. The N-th gate signal SRC [N-1] provided from the first stage SRC [N-1] is received to output the N-th gate signal GOUT [N] for selecting the N-th gate line. Output through terminal (OUT).

3 is a waveform diagram illustrating a driving waveform of a conventional shift register.

1 to 3, the stage of the shift register 174 is provided with a first power clock CKV or a second power clock CKVB. That is, the odd stage is provided with the first power clock CKV, and the even stage is provided with the second power clock CKVB corresponding to the inverted phase of the first power clock CKV. The shift register 174 generates a gate signal and sequentially provides the gate signal to gate lines of the thin film transistor substrate. The first power clock CKV and the second power clock CKVB are obtained from an output of a timing controller (not shown). In general, the output of the timing controller (not shown) has a signal of 0 to 3V amplitude and is amplified by a signal of -8 to 24V amplitude to drive a-Si TFT.

1 to 3, at least five bus lines are required to realize the Gate IC-Less structure using the a-Si transistor. Specifically, the bus line is connected to an odd-numbered gate line and a bus line for transmitting a scan start signal STV, which is a start signal in a horizontal direction, to transmit a first power clock CKV for applying a gate-off voltage. A bus line connected to an even-numbered gate line for transferring a second power clock CKVB for applying a gate-off voltage, and applying first and second power voltages VOFF and VON to respective stages, respectively. First and second power lines VSS and VDD.

The five bus lines are connected through a dummy pin path of a TCP in which a source driving IC is mounted, or are attached to a liquid crystal display panel and electrically connected to a gate driving region provided in the liquid crystal display panel.

However, there are the following problems in designing the gate driver having such a design structure.

That is, there is a problem in that a space for a jumper (JUMPER) configuration for connecting signals and power to each stage by wiring each bus line up and down and branching from each bus line is required. This problem is particularly acute in Narrow Bezel products, which have a large effective aspect ratio because of the limited black matrix space.

In addition, the manufacturing cost increases due to an increase in the TCP dummy space or the FPC width required when five or more bus lines are supplied via the TCP or FPC path, and applied to a product having a narrow attachment space. There is a problem that is not easy to do.

In addition, when implementing the gate driving circuit using the a-Si transistor, if the a-Si transistor is DC biased, there is a possibility of malfunction of the gate driving circuit composed of the deteriorated there is a possibility to delete the DC power applied from the outside Review is needed.

In addition, the driving voltage of the a-Si transistor requires a large potential difference of about -14V to + 20V, and because of this, a large potential difference between PADs of the liquid crystal display panel required when TCP or FPC is attached to the liquid crystal display panel. The metal pads may be damaged.

In particular, when the product is driven in a high temperature and high humidity environment, the moisture penetrated between the pads having high potential difference acts as an electrolyte between the two metal electrodes so that the pad metal is corroded and opened, or a current path is formed between the two metal electrodes. There is a serious problem that the liquid crystal display device malfunctions or is destroyed.

Accordingly, the technical and problem of the present invention is to solve such a conventional problem, and a first object of the present invention is to provide a shift register for reducing the number of external bus lines.

Further, a second object of the present invention is to provide a display device having the above shift register.

1 is a circuit diagram for explaining a conventional shift register.

2 is a view for explaining a gate driving circuit of a conventional shift register.

3 is a waveform diagram illustrating a driving waveform of a conventional shift register.

4 is a diagram for describing a gate driving circuit according to an exemplary embodiment of the present invention.

5 is a circuit diagram illustrating a unit stage of a shift register according to a first embodiment of the present invention.

6 is a circuit diagram illustrating a shift register according to a first embodiment of the present invention.

7 is a circuit diagram illustrating a unit stage of a shift register according to a second embodiment of the present invention.

8 is a circuit diagram illustrating a shift register according to a second embodiment of the present invention.

9 is a circuit diagram illustrating a unit stage of a shift register according to a third embodiment of the present invention.

10 is a circuit diagram for describing a shift register according to a third embodiment of the present invention.

11 is a circuit diagram illustrating a unit stage of a shift register according to a fourth embodiment of the present invention.

12 is a circuit diagram illustrating a shift register according to a fourth embodiment of the present invention.

13 is a circuit diagram illustrating a unit stage of a shift register according to a fifth embodiment of the present invention.

14 is a circuit diagram illustrating a shift register according to a fifth embodiment of the present invention.

15 is a circuit diagram illustrating a unit stage of a shift register according to a sixth embodiment of the present invention.

16 is a circuit diagram illustrating a shift register according to a sixth embodiment of the present invention.

17 is a diagram for describing a gate driving circuit according to another exemplary embodiment of the present invention.

18 is a plan view illustrating a display device according to an exemplary embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

210: pull-up part 220: pull-down part

230, 430: first pull-up driving unit 240, 340, 440, 640: second pull-up driving unit

1100 thin film transistor 1200 pixel electrode

1300: gate driver 1400: data driver

Stage: ASRC1, ASRC2, ..., ASRCN, BSRC1, BSRC2, ..., BSRCN

ASRCN + 1, BSRCN + 1: Dummy Stage

According to an embodiment of the present invention for achieving the first object of the present invention, in the shift register including a plurality of stages for sequentially generating a gate signal on a plurality of gate lines of the display device, each stage is A first pull-up driving unit, a pull-up driving unit, a second pull-up driving unit, and a third pull-up driving unit are included. The first pull-up driver generates a first control signal in response to an output signal or a control signal of a previous stage. The pull-up unit generates an output signal of a current stage in response to a first power clock and the first control signal. The second pull-up driver generates at least one second control signal in response to the first power clock and the second power clock. The third pull-up driving unit is connected to a low level terminal and drives in response to an output signal of a following stage.

According to an exemplary embodiment of the present invention for achieving the second object of the present invention, a gate signal is sequentially generated in a plurality of pixels each having a switching element scanned by a scan signal and a plurality of gate lines of a display panel. A display device including a shift register including a plurality of stages to display an image on the display panel, wherein each stage includes a first pull-up driving unit, a pull-up unit, and a second pull-up unit. A driver and a third pull-up driver. The first pull-up driver generates a first control signal in response to an output signal or a control signal of a previous stage. The pull-up unit generates an output signal of a current stage in response to a first power clock and the first control signal. The second pull-up driver generates at least one second control signal in response to the first power clock and the second power clock. The third pull-up driving unit is connected to a low level terminal and drives in response to an output signal of a following stage.

The second pull-up driving unit according to the exemplary embodiment of the present invention includes a first transistor, a second transistor, and a third transistor. The first transistor includes a gate electrode connected to a line to which the gate signal is applied, and a conductive path connecting between the terminal to which the first power clock is applied and the terminal to which the second power clock is applied. . The second transistor is connected between the terminal to which the first power clock is applied and the first transistor, and is operated as a diode. The third transistor may include a gate electrode connected to a line to which the second power clock is applied, a terminal to which the first power clock is applied, and the first transistor of the second pull-up driver and the second pull-up driver. And a conductive path connecting the common node of the transistor. The common node is connected to the third pull-up driver.

The second pull-up driving unit according to another embodiment of the present invention includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor. The first transistor includes a gate electrode connected to a line to which the gate signal is applied, and a conductive path connecting a terminal to which the first power clock is applied and a terminal to which the second power clock is applied. The second transistor includes a gate electrode connected to a line to which a second transistor control signal is applied, a conductive path connecting a terminal to which the first power clock is applied and the first transistor of the second pull-up driver; A common node with the first transistor of the second pull-up driver is connected to the gate electrode of the hold transistor of the first pull-up driver. The third transistor may include a gate electrode to which the second power clock is applied, a terminal to which the first power clock is applied, and the first transistor of the second pull-up driver and the second transistor of the second pull-up driver. And a conductive path connecting the common node. The fourth transistor includes a conductive path connecting a gate electrode to which the gate signal is applied, a terminal to which the first power clock is applied, and a terminal to which the second power clock is applied. The fifth transistor is connected between the terminal to which the first power clock is applied and the fourth transistor of the second pull-up driver, and is operated as a diode, and a common node with the fourth transistor is a gate of the second transistor. Connected to the electrode. The sixth transistor includes a gate electrode connected to a line to which the second power clock is applied, a conductive path connecting a terminal to which the first power clock is applied and the common node between the fourth transistor and the fifth transistor. It includes.

The second pull-up driving unit according to another embodiment of the present invention includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor. The first transistor includes a gate electrode connected to a line to which the gate signal is applied, a conductive path connecting a terminal to which the first power clock is applied and a terminal to which the second power clock is applied. The second transistor includes a gate electrode to which a second transistor control signal is applied, a conductive path connecting the terminal to which the first power clock is applied and the first transistor of the second pull-up driver, and the second pull-up. A common node with the first transistor of the driver is connected to the gate electrode of the hold transistor of the first pull-up driver. The third transistor is connected between a gate electrode to which the second power clock is applied, a terminal to which the first power clock is applied, and a first transistor of the second pull-up driver and a second transistor of the second pull-up driver. It includes a conductive path to connect. The fourth transistor includes a gate electrode connected to a line to which the gate signal is applied, a conductive path connecting a terminal to which the first power clock is applied and a terminal to which the second power clock is applied. The fifth transistor is connected to the terminal to which the first power clock is applied and the fourth transistor of the second pull-up driver, and is operated as a diode, and the common node of the fourth transistor is the gate of the second transistor. Connected to the electrode. The sixth transistor includes a gate electrode connected to a line to which the second power clock is applied, a conductive path connecting a terminal to which the first power clock is applied and the common node between the fourth transistor and the fifth transistor. It includes. The seventh transistor includes a gate electrode connected to the common node between the fourth transistor and the fifth transistor, and a conductive path connecting the first pull-up driver and a terminal from which the gate signal is output.

According to another embodiment of the present invention, the second pull-up driving unit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor. The first transistor includes a gate electrode connected to a line to which the gate signal is applied, a conductive path connecting a terminal to which the first power clock is applied and a terminal to which the second power clock is applied. The second transistor includes a gate electrode to which a second transistor control signal is applied, a conductive path connecting the terminal to which the first power clock is applied and the first transistor of the second pull-up driver, and the second pull-up. A common node with the first transistor of the driver is connected to the gate electrode of the hold transistor of the first pull-up driver. The third transistor may include a gate electrode to which the second power clock is applied, a terminal to which the first power clock is applied, and the first transistor of the second pull-up driver and the second transistor of the second pull-up driver. Connect the common node. The fourth transistor includes a gate electrode connected to a line to which the gate signal is applied, a conductive path connecting a terminal to which the first power clock is applied and a terminal to which the second power clock is applied. The fifth transistor connects the terminal to which the first power clock is applied and the fourth transistor of the second pull-up driver and is operated as a diode, and a common node with the fourth transistor is the gate of the second transistor. Connected to the electrode. The sixth transistor may include a conductive path connecting a gate electrode connected to a line to which the second power clock is applied, a terminal to which the first power clock is applied, and a common node between the fourth transistor and the fifth transistor. Include. The seventh transistor includes a gate electrode connected to a common node of the first transistor and the second transistor, and a conductive path connecting the first pull-up driver and a terminal from which the gate signal is output.

According to the shift register and the gate driving circuit having the shift register, the shift register including the amorphous-silicon thin film transistor can be normally operated even if only the bus lines providing the first and second power clocks and the scan start signal are provided.

Hereinafter, with reference to the accompanying drawings, it will be described in detail the present invention.

FIG. 4 is a diagram for describing a gate driving circuit according to an exemplary embodiment of the present invention. In particular, FIG. 4 is a diagram for describing an example of a gate driving circuit including a shift register having a plurality of stages.

Referring to FIG. 4, the gate driving circuit outputs N gate signals (or scan signals) GOUT [1], GOUT [2], ... GOUT [N] and N stages ASRC1, ASRC2, ASRC3, ..., ASRCN and one dummy stage ASRCN + 1 for outputting the dummy gate signal GDUMMY.

Here, the gate driving circuit is formed on the same plane as a liquid crystal display panel (not shown) having a switching element (not shown) formed in a region defined by a plurality of gate lines (not shown) and data lines (not shown). And outputs a gate signal for applying a scan signal to the gate electrode of the switching element.

The shift register is formed on the same panel as the display panel such as a liquid crystal display panel. The display panel includes switching elements formed in a region defined by a plurality of gate lines (or scan lines) and a plurality of data lines. The shift register provides the gate signals GOUT [1], GOUT [2], ... GOUT [N] to corresponding switching elements as the scan signal.

Each stage ASRC1, ASRC2,... ASRCN of the shift register includes a first clock stage CK1 receiving a first power clock CKV provided from the outside and a second power clock CKVB provided from the outside. ) Includes a second clock stage CK2. The phase of the second power clock CKVB is inverted with the phase of the first power clock CKV. Each of the stages ASRC1, ASRC2,... ASRCN includes a first control terminal CT1 receiving a first control signal, a second control terminal CT2 receiving a second control signal, and a third control signal. The third control terminal CT3 is provided with an output terminal (OUT) for generating the respective gate signals (GOUT [1], GOUT [2], ... GOUT [N]).

The first stage ASRC1 receives the first and second power clocks CKV and CKVB provided from the outside through the first and second power clock stages CK1 and CK2, and the first and third control stages CT1 and CT3. Receive a scan start signal STV and a second gate signal GOUT [2] provided from a second stage ASRC2, which is a next stage, through the second control terminal CT2. The first gate signal GOUT [1] for the selection of the output terminal OUT is output to the first control terminal CT1 of the second stage ASRC2.

The second stage ASRC2 transfers the first and second power clocks CKV and CKVB provided from the outside through the first and second power clock stages CK1 and CK2, and transfers them through the first control stage CT1. The first gate signal GOUT [1] provided from the first stage ASRC1, which is a stage, is the third gate signal GOUT [3 provided from the third stage ASRC3, which is the next stage, through the second control terminal CT2. ] And the scan start signal STV through the third control terminal CT3, respectively, and the second gate signal GOUT [2] for the selection of the second gate line to the output terminal OUT. The output box is output to the first control terminal CT1 of the third stage ASRC3.

In the above manner, the N-th stage ASRCN receives the first and second power clocks CKV and CKVB provided from the outside through the first and second power clock stages CK1 and CK2. The gate signal provided from the previous stage through CT1, the dummy gate signal GDUMMY provided from the dummy stage ASRCN + 1 through the second control terminal CT2, and the third control terminal CT3 The scan start signal STV is received through the N-th gate signal GOUT [N] for selecting the N-th gate line through the output terminal OUT, and the dummy stage ASRCN + 1 of the dummy stage ASRCN + 1. Output to the first control terminal CT1.

According to the gate driving circuit according to the present invention, even if only the bus line for transmitting the scan start signal (STV) and the bus line for transmitting the first and second power clock (CKV, CKVB), respectively, the scan A gate signal GOUT [1], GOUT [2], ... GOUT [N] for gate line selection is received by receiving a start signal and the first and second power clocks CKV and CKVB from the outside. You can see that.

According to the present invention described above, by reducing the number of external power supply line can reduce the number of bus lines required for the implementation of the gate driving circuit, it is possible to minimize the noise component generated between the bus line, as well as design The time margin can be secured, and the problem of corrosion due to moisture between the connection pads provided at the edges of the liquid crystal display panel can be solved.

Example 1

FIG. 5 is a circuit diagram illustrating a unit stage of a shift register according to a first embodiment of the present invention, and FIG. 6 is a circuit diagram illustrating a shift register employing the unit stage of FIG. 5 described above.

5 and 6, the unit stage 200 of the shift register according to the first embodiment of the present invention may include a pull-up unit 210, a pull-down unit 220, a first pull-up driving unit 230, and a second pull-up. The driver 250 and the third pull-up driver 240 may include a gate signal (or scan signal) based on the scan start signal STV and the output signals of the previous and next stages.

The pull-up unit 210 has a drain connected to the first power clock terminal CK1, a gate connected to the third pull-up driver 240, and a source connected to the first NMOS transistor M1 connected to the output terminal GOUT. And outputs the gate signal GOUT [N].

The pull-down unit 220 includes a second NMOS transistor M2 having a drain and a gate in common and connected to an output terminal GOUT, a drain connected to a source of the second NMOS transistor M2, and a source of the first NMOS. The third NMOS transistor M3 is connected to the drain of the transistor M1 and has a gate connected to the second power clock terminal CK2. Here, the second NMOS transistor M2 serves as a diode.

The first pull-up driver 230 includes a fourth NMOS transistor M4. The gate electrode and the drain electrode of the fourth NMOS transistor M4 are electrically connected to the first control terminal CT1. The source electrode of the fourth NMOS transistor M4 is electrically connected to the capacitor C at the first node N1.

The second pull-up driving unit 250 includes eighth to tenth NMOS transistors M8 to M10. In detail, the source of the eighth NMOS transistor M8 is connected to the second power clock terminal CK2, and a gate thereof is connected to the output terminal GOUT.

The ninth NMOS transistor M9 has a drain and a gate in common, and is connected to the first power clock terminal CK1, and a source is connected to the drain of the eighth NMOS transistor M8. In the tenth NMOS transistor M10, a drain is connected to the first power clock terminal CK1, a gate is connected to a second power clock terminal CK2, and a source is drained of the eighth NMOS transistor M8. And a source of the ninth NMOS transistor M9.

The eighth NMOS transistor M8 may be larger than the ninth NMOS transistor M9. That is, the W / L ratio of the eighth NMOS transistor M8 is preferably larger than the W / L ratio of the ninth NMOS transistor M9. This is because when the gate signal Gout [N] is at a high level, the eighth NMOS transistor M8 and the ninth NMOS transistor M9 are turned on at the same time, and the sixth NMOS transistor performing the hold function at this time. This is because a low level must be applied to the gate electrode of M6.

The third pull-up driving unit 240 is composed of a capacitor C and fifth to seventh NMOS transistors M5 to M7. In detail, the capacitor C is connected between the gate of the first NMOS transistor M1 and the output terminal GOUT. The fifth NMOS transistor M5 has a common drain and gate and is connected to one end of the capacitor C via the first node N1. The sixth NMOS transistor M6 has a drain connected to the source of the fifth NMOS transistor M5, a gate connected to the first power clock terminal CK1, and a source passed through the second node N2. Are connected to the second power clock terminal CK2.

The seventh NMOS transistor M7 has a drain connected to one end of the capacitor C via a first node N1, a gate connected to a second control terminal CT2, and a source connected to a third control terminal. (CT3). In this case, a scan start signal STV may be applied to the seventh NMOS transistor M7. Here, the fourth NMOS transistor M4 and the fifth NMOS transistor M5 serve as diodes.

Typically, since the first NMOS transistor M1 of the pull-up unit 210 implemented as an a-Si transistor has very small electron mobility, a high voltage amplitude for driving a large liquid crystal display, for example, 20V to In order to apply a gate pulse of about -14V to the gate line, it is very large.

Particularly, in the case of XGA class using 12.1 inches (30.734 cm), the parasitic capacitance of one gate line is about 250 to 300 [pF], and if it is intended to be driven by an a-Si transistor designed with a minimum design rule of 4 μm, When the channel length L is 4 mu m, the channel width W is about 5500 mu m. Therefore, parasitic capacitance Cgd, which is a parasitic capacitance of the first NMOS transistor M1 for driving the gate line, may be large.

In this case, the size of the parasitic capacitance Cgd is about 3 pF, which causes a malfunction of the gate driving circuit composed of the a-Si transistor. The parasitic capacitance Cgd is connected to a high amplitude, that is, a power clock CKV or CKVB of 20V to -14V, and the parasitic capacitance Cgd acts as a coupling capacitor to perform a pull-up function. This is because the gate voltage of the NMOS transistor M1 can be generated.

For example, when there is no means for maintaining the coupling capacitor at the gate-off voltage VOFF, the gate voltage of the first NMOS transistor M1 has a potential of the power clock CKV or CKVB of -14V to 20V. In addition, since an output voltage is obtained by subtracting the threshold voltage Vth of the first NMOS transistor M1 at a maximum of 20V and applied to the gate line of the liquid crystal display panel, an abnormal display phenomenon may occur.

Accordingly, in the gate driving circuit including the a-Si transistor, the sixth NMOS transistor M6 which performs a hold function to maintain the gate of the first NMOS transistor M1 outputting a scan pulse at the gate-off voltage VOFF. ) And the first NMOS transistor M, the gate signal GOUT [N] is the gate-off voltage for most of the time when the first NMOS transistor M1 does not generate an active gate signal to activate the pixel. The third NMOS transistor M3, which has a pull-down function to be at the (VOFF) level, is essential.

In operation, as the previous gate signal GOUT [N-1] output from the previous stage is applied to the fourth NMOS transistor M4, the fourth NMOS transistor M4 is the previous gate signal GOUT. It serves as a diode that receives [N-1]) as a carry signal.

The eighth NMOS transistor M8 is turned on by the current gate signal GOUT [N] having a high level, and the sixth NMOS transistor M6 is turned off. In this case, the ninth NMOS transistor M9 acts as a diode so that a high level signal is applied to the sixth NMOS transistor M6. When the first power clock CK1 is at a low level and the second power clock CK2 is at a high level, the tenth NMOS transistor M10 is turned on so that a low level signal is transmitted to the sixth NMOS transistor ( Is applied to M6). Therefore, the second pull-up driver 240 provides a control signal having the same phase as the first power clock CK1 to the sixth NMOS transistor M6.

The first NMOS transistor M1 maintains a low level due to the large capacitance of the NMOS transistor. When the first power clock CKV changes from a low level to a high level, the sixth NMOS transistor M6 performs a hold function to indicate that the gate voltage of the first NMOS transistor M1 has a high threshold. prevent. In particular, when the first power clock CKV changes from a low level to a high level, the current gate signal GOUT [N] becomes a high level, and the eighth NMOS transistor M8 is turned on. Therefore, since the gate electrode of the sixth NMOS transistor M6 is at a low level, the sixth NMOS transistor M6 electrically connected to the drain electrode of the eighth NMOS transistor M8 is turned off.

In this case, a voltage for turning on the sixth NMOS transistor M6 which performs the hold function may be generated by the control of the eighth to tenth NMOS transistors M8, M9, and M10. In detail, the first NMOS transistor M1 performs a sampling function of the first power clock CKV, that is, a sampling function of keeping the low level by a large parasitic capacitance of the NMOS transistor, and the first power clock ( The sixth NMOS transistor M6 prevents the gate voltage of the first NMOS transistor M1 from rising above the threshold voltage of the first NMOS transistor M1 when CKV is transitioned from a low level to a high level. The hold function may be performed.

In addition, the seventh NMOS transistor M7 discharges the capacitor C to the first power voltage VOFF by the next gate signal GOUT [N + 1] output from the next stage. Since the scan start signal STV is the first power voltage VOFF when the seventh NMOS transistor M7 is turned on, the scan start signal STV is connected to the source of the seventh NMOS transistor M7.

Accordingly, a shift register implemented as an a-Si transistor may be implemented without having a separate power line for applying the first power voltage VOFF or a separate power line for applying the second power voltage VON. The shift register can be employed as the gate driving circuit of the liquid crystal display device.

Second embodiment

7 is a circuit diagram illustrating a unit stage of a shift register according to a second embodiment of the present invention, and FIG. 8 is a circuit diagram illustrating a shift register according to a second embodiment of the present invention.

7 and 8, the unit stage 300 of the shift register according to the second embodiment of the present invention may include a pull-up unit 210, a pull-down unit 220, a first pull-up driving unit 230, and a second pull-up unit. The driver 340 may include a gate signal (or scan signal) based on the scan start signal STV and the output signals of the previous and next stages. Here, since the pull-up unit 210, the pull-down unit 220 and the first pull-up driving unit 230 have been described with reference to FIG. 5, detailed description thereof will be omitted.

The second pull-up driving unit 340 includes eighth to thirteenth NMOS transistors M8 to M13. Specifically, the eighth NMOS transistor M8 has a source connected to a second power clock terminal CK2, a gate connected to an output terminal GOUT, and a ninth NMOS transistor through a second node N2. M9 has a drain connected to the first power clock terminal CK1 and a source connected to the drain of the eighth NMOS transistor M8.

The drain of the tenth NMOS transistor M10 is connected to the first power clock terminal CK1, the gate is connected to the second power clock terminal CK2, and the source of the eighth NMOS transistor M8 is connected to the drain and the eighth NMOS transistor M8. It is connected to the source of the ninth NMOS transistor M9.

A source of the eleventh NMOS transistor M11 is connected to the second power clock terminal CK2, and a gate thereof is connected to the gate of the eighth NMOS transistor M8. The twelfth NMOS transistor M12 has a drain and a gate in common, and a source is connected to a gate of the ninth NMOS transistor M9 and a drain of the eleventh NMOS transistor M11.

The thirteenth NMOS transistor M13 has a drain connected to the first power clock terminal CK1, a gate connected to a second power clock terminal CK2, and a source of the drain and the source of the eleventh NMOS transistor M11. It is connected to the source of the twelfth NMOS transistor M12.

In operation, when the eighth NMOS transistor M8 is turned on because the current gate signal GOUT [N] is an active signal having a high level, the sixth NMOS transistor M6 remains turned off. . In this case, a low voltage is applied to the gate electrode of the ninth NMOS transistor M9. In particular, when the current gate signal GOUT [N] is applied to the gate electrode of the eighth NMOS transistor M8 and the gate electrode of the eleventh NMOS transistor M11, the eighth NMOS transistor M8 and the The eleventh NMOS transistor M11 is turned on. Accordingly, the channel resistance is increased by turning off the ninth NMOS transistor M9 electrically connected to the drain electrode of the eighth NMOS transistor M8 and the drain electrode of the eleventh NMOS transistor M11. That is, when the four ninth NMOS transistor M9 and the eleventh NMOS transistor M8 are turned on at the same time, a low level signal is applied to the sixth NMOS transistor.

When the current gate signal GOUT [N] is an inactive signal having a low level, the eighth NMOS transistor M8 is turned off and is connected to the gate electrode of the sixth NMOS transistor M6. The control signal having the same phase as the first power clock CKV is applied. In particular, since the second power clock CKVN is an active signal, the tenth NMOS transistor M10 and the thirteenth transistor M13 electrically connected to the second power clock terminal CK2 are turned on. Accordingly, a low level signal is applied to the gate electrode of the ninth NMOS transistor M9 so that the sixth NMOS transistor M6 is turned off.

According to the second embodiment of the present invention, a voltage for turning on the sixth NMOS transistor M6 which performs the hold function by the operations of the eighth to thirteenth NMOS transistors M8 to M13 is generated. can do.

In detail, the first NMOS transistor M1 performs a sampling function of the first power clock CKV, that is, a sampling function of maintaining a low level due to a large parasitic capacitance of the NMOS transistor, and the first power clock. In the state where CKV is transitioned from a low level to a high level, the sixth NMOS transistor M6 indicates that the gate voltage of the first NMOS transistor M1 rises above the threshold voltage of the first NMOS transistor M1. It performs the holding function to prevent.

According to the second embodiment described above, when the W / L ratio of the ninth NMOS transistor M9 is increased, the ninth NMOS transistor M9 turns on the sixth NMOS transistor M6. Since the W / L ratio of the eighth NMOS transistor M8 shown in the above-described first embodiment is larger than the W / L ratio of the ninth NMOS transistor M9, the ninth NMOS transistor M9 may be shortened. Solves a problem caused by an increase in the time constant for turning on the sixth NMOS transistor M6.

That is, in the first embodiment, the ninth NMOS transistor M9 operates as a diode, but in the second embodiment, the ninth NMOS transistor M9 is controlled by the operation results of the eleventh through thirteenth NMOS transistors M11, M12, and M13. do.

Third embodiment

9 is a circuit diagram illustrating a unit stage of a shift register according to a third embodiment of the present invention, and FIG. 10 is a circuit diagram illustrating a shift register according to a third embodiment of the present invention. In particular, the fifth NMOS transistor M5 serving as the diode shown in the first embodiment of FIG. 5 is excluded.

9 and 10, the unit stage 400 of the shift register according to the third embodiment of the present invention may include a pull-up unit 210, a pull-down unit 220, a first pull-up driving unit 430, and a second pull-up. The driver 440 and the third pull-up driver 450 include a gate signal (or scan signal) based on the scan start signal STV and the output signals of the previous and next stages. Here, since the pull-up unit 210 and the pull-down unit 220 have been described with reference to FIG. 5, detailed description thereof will be omitted.

The first pull-up driving unit 430 includes sixth and seventh NMOS transistors M6 and M7 and a capacitor C. Referring to FIG. Compared with FIG. 5, the fifth NMOS transistor M5 is omitted in the third embodiment of the present invention.

The sixth NMOS transistor M6 receives a drain electrode electrically connected to the first node N1, a source electrode electrically connected to the output terminal GOUT, and a control signal applied from the second pull-up driver 440. And a gate electrode.

The seventh NMOS transistor M7 includes a drain electrode electrically connected to the first node N1, a source electrode electrically connected to a third control terminal to which a scan start signal STV is applied, and a next gate from a next stage. And a gate electrode electrically connected to the second control terminal CT2 to which the signal GOUT [N] +1 is applied. The capacitor C is electrically connected between the first node N1 and the output terminal GOUT.

The second pull-up driving unit 440 includes eighth to tenth NMOS transistors M8 to M10.

In detail, the source of the eighth NMOS transistor M8 is connected to the second power clock terminal CK2 through the second node N2, and the gate of one end of the capacitor C and the sixth NMOS transistor M6 are connected to each other. It is connected to the source and output terminals (GOUT).

The drain and gate of the ninth NMOS transistor M9 are commonly connected to the first power clock terminal CK1, and the source is connected to the drain of the eighth NMOS transistor M8.

The drain of the tenth NMOS transistor M10 is connected to the first power clock terminal CK1, the gate is connected to the second power clock terminal CK2, and the source is the drain and the fifteenth of the eighth NMOS transistor M8. It is connected to the source of the NMOS transistor M9. In addition, the source electrode of the tenth NMOS transistor M10 is also connected to the gate electrode of the sixth NMOS transistor.

The third pull-up driver 450 includes a fourth NMOS transistor M4. The gate electrode and the drain electrode of the fourth NMOS transistor M4 are common and are electrically connected to the first control terminal CT1 to which the previous gate signal GOUT [N] -1 is applied. The source electrode of the fourth NMOS transistor M4 is electrically connected to the gate electrode of the first NMOS transistor M1 of the pull-up unit 210 through the first node N1.

The eighth NMOS transistor M8 is turned on / off according to the current gate signal GOUT [N]. When the current gate signal GOUT [N] is in an active state with a high level, the eighth NMOS transistor M8 remains turned on and the sixth NMOS transistor M6 is turned off. On the other hand, when the current gate signal GOUT [N] is in an inactive state at a low level, the eighth NMOS transistor M8 is turned off. In this case, a control signal having the same phase as the first power clock CKV is applied to the sixth NMOS transistor M6 from the second pull-up driver 440. That is, when the first power clock CKV is at the high level, the ninth NMOS transistor M9 operates as a diode, so the high level signal is applied to the sixth NMOS transistor M6. When the first power clock CKV is at a low level, the second power clock CKVB having a phase inverted from the first power clock CKV is at a high level so that the tenth NMOS transistor M10 is turned on. Is on. Therefore, a low level signal is applied to the sixth NMOS transistor M6. That is, the second pull-up driving unit 440 provides a control signal having the same phase as the first clock signal CKV to the sixth NMOS transistor M6.

Therefore, when the sixth NMOS transistor M6 maintains the turn-off state, a high level voltage is applied to the source electrode of the sixth NMOS transistor M6. In addition, when the sixth NMOS transistor M6 maintains the turn-on state, a low level voltage is applied to the source electrode of the sixth NMOS transistor M6.

Fourth embodiment

FIG. 11 is a circuit diagram illustrating a unit stage of a shift register according to a fourth embodiment of the present invention, and FIG. 12 is a circuit diagram illustrating a shift register according to a fourth embodiment of the present invention.

11 and 12, the unit stage 500 of the shift register according to the fourth exemplary embodiment of the present invention may include a pull-up unit 210, a pull-down unit 220, a first pull-up driving unit 430, and a second pull-up. Including the driver 350 and the third pull-up driver 440, the gate signal (GOUN-1) output from the previous stage, the gate signal (GOUN + 1) output from the next stage, the first power clock (CKV), The second power clock CKVB and the scan start signal STV are input to output a gate signal GOUT [N] corresponding to the current stage.

Here, the pull-up unit 210 and the pull-down unit 220 have been described with reference to FIG. 5, the first pull-up driving unit 430 has been described with reference to FIG. 9, and the second pull-up driving unit 340 has been described with reference to FIG. 7. As described in the detailed description thereof.

Here, the W / L ratio of the ninth NMOS transistor M9 is preferably larger than the W / L ratio of the eighth NMOS transistor M8. If the W / L ratio of the eighth NMOS transistor M8 shown in the third embodiment is greater than the W / L ratio of the ninth NMOS transistor M9, the ninth NMOS transistor M9 is the sixth. The long time constant for turning on the NMOS transistor M6 may cause a problem.

However, the W / L ratio of the ninth NMOS transistor M9 is greater than the W / L ratio of the eighth NMOS transistor M8 so that the ninth NMOS transistor M9 turns on the sixth NMOS transistor M6. It can shorten the time constant.

Fifth Embodiment

FIG. 13 is a circuit diagram illustrating a unit stage of a shift register according to a fifth embodiment of the present invention, and FIG. 14 is a circuit diagram illustrating a shift register according to a fifth embodiment of the present invention.

13 and 14, the unit stage 600 of the shift register according to the fifth embodiment of the present invention may include a pull-up unit 210, a pull-down unit 220, a first pull-up driving unit 230, and a second pull-up. Including the driver 640 and the third pull-up driver 240, the first power clock CKV, the second power clock CKVB, the gate signal GOUT [N-1] output from the previous stage, and the next stage. The gate signal GOUT [N + 1] and the scan start signal STV are output from the gate signal GOUT [N] corresponding to the current stage. Here, since the pull-up unit 210, the pull-down unit 220 and the first pull-up driving unit 230 have been described with reference to FIG. 5, detailed description thereof will be omitted.

The second pull-up driving unit 640 includes eighth to fourteenth NMOS transistors M8 to M14. In detail, the source of the eleventh NMOS transistor M8 is connected to the second power clock terminal CK2 through the second node N2, and the gate thereof is connected to the output terminal GOUT.

A drain of the ninth NMOS transistor M9 is connected to the first power clock terminal CK1, and a source of the ninth NMOS transistor M9 is connected to the drain of the eighth NMOS transistor M8. In the tenth NMOS transistor M10, a drain is connected to the first power clock terminal CK1, a gate is connected to the second power clock terminal CK2, and a source is connected to the eighth NMOS transistor M8. A drain and a source of the ninth NMOS transistor M9 are connected to each other. In addition, the source of the tenth NMOS transistor M10 is connected to the gate of the sixth NMOS transistor M6.

A source of the eleventh NMOS transistor M11 is connected to the second power clock terminal CK2, and a gate thereof is connected to the gate of the eighth NMOS transistor M8. The twelfth NMOS transistor M12 has a drain and a gate in common and is connected to the first power clock terminal CK1, and a source of the twelfth NMOS transistor M12 is connected to the gate of the ninth NMOS transistor M9 and the eleventh NMOS transistor M11. Connected to the drain.

The thirteenth NMOS transistor M13 has a drain connected to the first power clock terminal CK1, a gate connected to the second power clock terminal CK2, and a source of the eleventh NMOS transistor M11. A drain and a source of the twelfth NMOS transistor M12 are connected to each other. A drain of the fourteenth NMOS transistor M14 is connected to one end of the capacitor C through the first node N1, and a gate thereof is the source and ninth NMOS of the twelfth and thirteenth NMOS transistors M12 and M13. It is connected to the gate of the transistor M9, the source is connected to the other end of the capacitor (C) and the output terminal (GOUT).

That is, as in the fifth embodiment of the present invention, the voltage applied to the gate of the fourteenth NMOS transistor M14 connected to the output terminal GOUT and performing a hold function is applied to the sixth NMOS transistor M6. A voltage for turning on the sixth NMOS transistor M6 that performs the hold function may be generated even if the voltage is different from the voltage applied to the gate of the gate.

In detail, the first NMOS transistor M1 performs a sampling function of the first power clock CKV, that is, a sampling function of keeping the low level by a large parasitic capacitance of the NMOS transistor, and the first power clock ( The sixth NMOS transistor M6 prevents the gate voltage of the first NMOS transistor M1 from rising above the threshold voltage of the first NMOS transistor M1 when CKV is transitioned from a low level to a high level. Perform the hold function.

Sixth embodiment

FIG. 15 is a circuit diagram illustrating a unit stage of a shift register according to a sixth embodiment of the present invention, and FIG. 16 is a circuit diagram illustrating a shift register according to a sixth embodiment of the present invention.

15 and 16, the unit stage 700 of the shift register according to the sixth embodiment of the present invention may include a pull-up unit 210, a pull-down unit 220, a first pull-up driving unit 230, and a second pull-up. The first power clock CKV, the second power clock CKVB, the gate signal GOUT [N-1] output from the previous stage, and the next stage, including the driver 740 and the third pull-up driver 240. The gate signal GOUT [N] corresponding to the current stage is output based on the gate signal GOUT [N + 1] and the scan start signal STV. Here, since the pull-up unit 210, the pull-down unit 220 and the first pull-up driving unit 230 have been described with reference to FIG. 5, detailed description thereof will be omitted.

The second pull-up driving unit 740 includes eighth to fourteenth NMOS transistors M8 to M14.

In detail, the source of the eighth NMOS transistor M8 is connected to the second power clock terminal CK2, and the gate thereof is connected to the output terminal GOUT. A drain of the ninth NMOS transistor M9 is connected to the first power clock terminal CK1, and a source of the ninth NMOS transistor M9 is connected to the drain of the eighth NMOS transistor M8.

In the tenth NMOS transistor M10, a drain is connected to the first power clock terminal CK1, a gate is connected to the second power clock terminal CK2, and a source is connected to the eighth NMOS transistor M8. It is connected to the drain and the source of the ninth NMOS transistor M9. A source of the eleventh NMOS transistor M11 is connected to the second power clock terminal CK2, and a gate thereof is connected to the gate of the eighth NMOS transistor M8.

The twelfth NMOS transistor M12 has a drain and a gate in common and is connected to the first power clock terminal CK1, and a source is connected to a gate of the ninth NMOS transistor M9. The thirteenth NMOS transistor M13 has a drain connected to the first power clock terminal CK1, a gate connected to the second power clock terminal CK2, and a source of the eleventh NMOS transistor M11. A drain and a source of the twelfth NMOS transistor M12 are connected to each other.

A drain of the fourteenth NMOS transistor M14 is connected to one end of the capacitor C and an output terminal GOUT, a gate thereof is connected to a source of the ninth and tenth NMOS transistors M9 and M10, and a source thereof is The third pull-up driving unit is connected to the drain of the fourth NMOS transistor M4 and the other end of the capacitor C.

The voltage applied to the gate of the fourteenth NMOS transistor M14 electrically connected to the output terminal GOUT [N] of the sixth NMOS transistor M6 electrically connected to the fifth NMOS transistor M5 acting as a diode. When the voltage is different from the voltage applied to the gate electrode, a voltage for turning on the sixth NMOS transistor M6 is generated.

In detail, the first NMOS transistor M1 performs a sampling function of the first power clock CKV, that is, a sampling function of maintaining a low level due to a large parasitic capacitance of the NMOS transistor, and the first power clock. In the state where CKV is transitioned from a low level to a high level, the sixth NMOS transistor M6 indicates that the gate voltage of the first NMOS transistor M1 rises above the threshold voltage of the first NMOS transistor M1. Perform a hold function to prevent it.

In the above, the scan start signal STV is applied to every stage constituting the shift register, but a separate power line is provided as shown in FIG. 17 to replace the scan start signal STV. The second power supply voltage VSS may be applied via the line.

FIG. 17 is a diagram for describing a gate driving circuit according to another embodiment of the present invention. In particular, FIG. 17 is a view for explaining another example of a gate driving circuit including a shift register having a plurality of stages.

Referring to FIG. 17, the gate driving circuit outputs N gate signals (or scan signals) GOUT [1], GOUT [2], ... GOUT [N], and N stages BSRC1, BSRC2, One dummy stage SRCN + 1 for outputting the BSRC3, ..., BSRCN and the dummy gate signal GDUMMY is provided.

The first stage BSRC1 receives the first and second power clocks CKV and CKVB provided from the outside through the first and second power clock stages CK1 and CK2, and the first and third control stages CT1 and CT3. Receiving the scan start signal STV and the second gate signal GOUT [2] provided from the second stage BSRC2, which is the next stage, through the second control terminal CT2, respectively. The first gate signal GOUT [1] for selecting is output to the first control terminal CT1 of the second stage along with the output terminal OUT.

The second stage BSRC2 transfers the first and second power clocks CKV and CKVB provided from the outside through the first and second power clock stages CK1 and CK2 through the first control stage CT1. The first gate signal GOUT [1] provided from the first stage BSRC1, which is a stage, is the third gate signal GOUT [3 provided from the third stage BSRC3, which is the next stage, through the second control terminal CT2. ]) And the first power supply voltage VOFF through the third control terminal CT3, respectively, and the second gate signal GOUT [2] for selecting the second gate line is connected to the output terminal OUT. The output box is output to the first control terminal CT1 of the third stage BSRC3.

In the above manner, the N-th stage BSRCN receives the first and second power clocks CKV and CKVB provided from the outside through the first and second power clock stages CK1 and CK2. The gate signal provided from the previous stage through CT1, the dummy gate signal GDUMMY provided from the dummy stage BSRCN + 1 through the second control terminal CT2, and the third control terminal CT3 The first power supply voltage VOFF is provided through each of the first and second Nth gate signals GOUT [N] for selecting the Nth gate line through the output terminal OUT, and the dummy stage BSRCN + 1. Output to the first control terminal CT1.

According to the gate driving circuit according to the present invention, only the scan start signal STV, the first and second power clocks CKV and CKVB, and the first power supply voltage VOFF are inputted from an external source. It can be seen that the gate signal for line selection is output.

That is, according to another example of the gate driving circuit according to the present invention, the number of bus wirings required to implement the gate driving circuit can be reduced by reducing the number of external power lines, and the liquid crystal display employing a shift register. Not only can the margin be secured when the panel is designed, but the problem of corrosion caused by moisture between the connection pads can be solved.

In the above description, only the stage constituting the gate driving circuit has been described, but the same applies to the specific embodiments described with reference to FIGS. 5 to 16. For example, in the circuits shown in FIGS. 5 and 6, the scan start signal STV is applied only to the first stage, and the first power supply voltage is replaced with the scan start signal STV in the second and subsequent stages. By applying (VOFF), the number of bus lines provided externally can be reduced.

In the above, only the shift register employed in the gate driving circuit and the gate driving circuit having the same have been described. However, the present invention may also be applied to a liquid crystal display panel, a liquid crystal display, or the like having a gate IC-Less structure employing the gate driving circuit on the same substrate. It is self-evident.

Display device

18 is a plan view illustrating a display device according to an exemplary embodiment of the present invention.

Referring to FIG. 18, the display panel 1000 includes a display area DA and a peripheral area PA. An image is displayed in the display area DA of the display panel 1000. The driving circuit of the display panel 1000 is disposed in the peripheral area PA. The display panel 1000 includes an upper substrate, a lower substrate facing the upper substrate, and a liquid crystal layer interposed between the upper substrate and the lower substrate.

A plurality of data lines DL and a plurality of gate lines GL are formed in the display area DA. The data lines DL are arranged in a first direction and the gate lines GL are arranged in a second direction perpendicular to the first direction. The thin film transistor 1100 operating as a switching element is electrically connected to the respective data lines DL and the respective gate lines GL. The switching device 1100 includes a drain electrode electrically connected to the pixel electrode 1200, a gate electrode electrically connected to the gate line GL, and a source electrode electrically connected to the data line DL. Image data is transmitted to the pixel electrode 1200 through the data line DL and the switching element 1100.

The data driver 1400 is disposed in the peripheral area PA. The data driver 1400 is electrically connected to the data line DL to apply the image data to the source electrode of the switching device 1100. The gate driver 1300 is disposed in the peripheral area PA. In this case, the gate driver 1300 may include the shift register of FIG. 4 or 17. The gate driver 1300 is electrically connected to the gate line GL to apply a gate driving signal provided from the gate driver 1300 to the switching device 1100.

The gate driver 1300 includes a shift register, and the gate driver 1300 has a plurality of stages. Each of the stages is electrically connected to the gate line GL to apply a scan or gate driving signal output from one of the stages to the gate electrode of the switching element 1100 through the gate line GL. When the scan signal is applied to the gate electrode of the switching device 1100, the data driver 1400 provides the image data to the pixel electrode 1200 in response to the scan signal. The shift register 1300 of the display panel has stages described in the embodiments corresponding to FIGS. 5 through 16.

In addition, the shift register may be applied not only to a liquid crystal display panel without the gate driving circuit, but also to other display panels such as an organic electroluminescence display panel (OLED panel), a general liquid crystal display panel, and the like.

Although described above with reference to the embodiments, those skilled in the art can be variously modified and changed within the scope of the present invention without departing from the spirit and scope of the invention described in the claims below. I can understand.

As described above, according to the present invention, even if each of the bus lines for providing the scan start signal (STV) and the first and second power clocks is provided, the number of external bus lines can be realized by implementing the shift register using only the minimized bus lines. In addition, the noise component generated between the bus lines can be reduced by the reduction of, and a margin can be secured in the design of the gate driving circuit employing the shift register.

In addition, the problem of corrosion caused by moisture between the connection end pads provided at the edge of the liquid crystal display panel employing the gate driving circuit can be solved.

Claims (22)

A shift register comprising a plurality of stages that sequentially generate a gate signal on a plurality of gate lines of a display device, Each stage A first pull-up driver configured to generate a first control signal in response to an output signal or a control signal of a previous stage; A pull-up unit configured to generate an output signal of a current stage in response to a first power clock and the first control signal; A second pull-up driver configured to generate at least one second control signal in response to the first power clock and the second power clock; And A shift register connected to a low level terminal and including a third pull-up driving unit for driving in response to an output signal of a following stage. The shift register of claim 1, further comprising a pull-down unit driven in response to the second power clock. The method of claim 2, wherein the second pull-up driving unit A first transistor including a gate electrode connected to a line to which the gate signal is applied, and a conductive path connected between a terminal to which the first power clock is applied and a terminal to which the second power clock is applied; A second transistor connected between the terminal to which the first power clock is applied and the first transistor and operated as a diode; And A gate electrode connected to the line to which the second power clock is applied, a terminal to which the first power clock is applied, a common node of the first transistor of the second pull-up driver and the second transistor of the second pull-up driver; Including a third transistor including a conductive path for connecting, The common node is coupled to the third pull-up driver. The method of claim 3, wherein the third pull-up drive unit A first transistor having two terminals to which the first control signal is applied; A second transistor including a gate electrode connected to the common node of the second pull-up driver, and a conductive path connecting a line to which the first transistor and the second power clock are applied; A third transistor including a gate electrode connected to a line to which an output signal of the next stage is applied, and a conductive path connecting the pull-up unit and the low level terminal; And And a capacitor connecting the pull-up unit and the line to which the output signal of the current stage is applied. The shift register of claim 4, wherein the low level terminal is connected to a line to which a ground level signal (VSS) is applied or a line to which a scan start signal (STV) is applied. The display device of claim 5, wherein the pull-up part comprises a conductive path connecting a gate electrode connected to a line to which the first control signal is applied, a terminal to which the first power clock is applied, and a terminal to output the gate signal. And a first transistor. The method of claim 6, wherein the pull-down portion A first transistor having two terminals commonly connected to a terminal for outputting the gate signal; And And a second transistor including a gate electrode connected to a line to which the second power clock is applied, and a conductive path connecting the second transistor and a line to which the first power clock is applied. . 8. The shift register according to claim 7, wherein the phase of the first power clock applied to the odd stage and the phase of the first power clock applied to the even stage are inverted from each other. The shift register according to claim 8, wherein the phase of the second power clock applied to the odd stage and the phase of the second power clock applied to the even stage are inverted from each other. 2. The shift register according to claim 1, wherein said control signal is a scan start signal (STV). The method of claim 2, wherein the second pull-up driving unit A first transistor including a gate electrode connected to a line to which the gate signal is applied, and a conductive path connecting the terminal to which the first power clock is applied and the terminal to which the second power clock is applied; A second electrode including a gate electrode connected to a line to which a second transistor control signal is applied, a conductive path connecting the terminal to which the first power clock is applied and the first transistor of the second pull-up driver; A second transistor of which a common node of the first transistor is connected to a gate electrode of a hold transistor of the first pull-up driver; A gate electrode to which the second power clock is applied, a terminal to which the first power clock is applied, and the common node between the first transistor of the second pull-up driver and the second transistor of the second pull-up driver are connected. A third transistor comprising a conductive pass to make; A fourth transistor including a gate electrode to which the gate signal is applied, a conductive path connecting the terminal to which the first power clock is applied and the terminal to which the second power clock is applied; A terminal connected between the terminal to which the first power clock is applied and the fourth transistor of the second pull-up driving unit and operated as a diode, wherein a common node with the fourth transistor is connected to the gate electrode of the second transistor; 5 transistors; And A sixth path including a gate electrode connected to a line to which the second power clock is applied, a terminal to which the first power clock is applied, and a conductive path connecting the common node between the fourth transistor and the fifth transistor A shift register comprising a transistor. The method of claim 2, wherein the second pull-up driving unit A first transistor including a gate electrode connected to a line to which the gate signal is applied, a conductive path connecting a terminal to which the first power clock is applied and a terminal to which the second power clock is applied; A first conductive path connecting a gate electrode to which a second transistor control signal is applied, a terminal to which the first power clock is applied, and the first transistor of the second pull-up driver; A second transistor having a common node with a transistor connected to a gate electrode of a hold transistor of the first pull-up driver; A conductive path connecting a gate electrode to which the second power clock is applied, a terminal to which the first power clock is applied, and a first transistor of the second pull-up driver and a second transistor of the second pull-up driver; A third transistor comprising; A fourth transistor including a gate electrode connected to a line to which the gate signal is applied, a conductive path connecting a terminal to which the first power clock is applied and a terminal to which the second power clock is applied; A first node connected to the terminal to which the first power clock is applied and the fourth transistor of the second pull-up driver, operated as a diode, and a common node of the fourth transistor connected to the gate electrode of the second transistor; 5 transistors; A sixth path including a gate electrode connected to a line to which the second power clock is applied, a terminal to which the first power clock is applied, and a conductive path connecting the common node between the fourth transistor and the fifth transistor transistor; And A shift register including a gate electrode connected to the common node between the fourth transistor and the fifth transistor, and a seventh transistor including a conductive path connecting the first pull-up driver and a terminal from which the gate signal is output . The method of claim 2, wherein the second pull-up driving unit A first transistor including a gate electrode connected to a line to which the gate signal is applied, a conductive path connecting a terminal to which the first power clock is applied and a terminal to which the second power clock is applied; A first conductive path connecting a gate electrode to which a second transistor control signal is applied, a terminal to which the first power clock is applied, and the first transistor of the second pull-up driver; A second transistor having a common node with a transistor connected to a gate electrode of a hold transistor of the first pull-up driver; A gate electrode to which the second power clock is applied, a terminal to which the first power clock is applied, and the common node between the first transistor of the second pull-up driver and the second transistor of the second pull-up driver are connected. A third transistor; A fourth transistor including a gate electrode connected to a line to which the gate signal is applied, a conductive path connecting a terminal to which the first power clock is applied and a terminal to which the second power clock is applied; A terminal connected to the terminal to which the first power clock is applied and the fourth transistor of the second pull-up driving unit and operated as a diode, wherein a common node with the fourth transistor is connected to the gate electrode of the second transistor; 5 transistors; A sixth transistor including a gate electrode connected to a line to which the second power clock is applied, a terminal to which the first power clock is applied, and a conductive path connecting a common node between the fourth transistor and the fifth transistor ; And And a seventh transistor including a gate electrode connected to the common node of the first transistor and the second transistor, and a conductive path connecting the first pull-up driver and a terminal to which the gate signal is output. Shift register. A shift register including a plurality of pixels each having a switching element scanned by a scan signal, and a plurality of stages sequentially generating a gate signal on a plurality of gate lines of the display panel, and displaying an image on the display panel. In the display device to display, Each stage A first pull-up driver configured to generate a first control signal in response to an output signal or a control signal of a previous stage; A pull-up unit configured to generate an output signal of a current stage in response to a first power clock and the first control signal; A second pull-up driver configured to generate at least one second control signal in response to the first power clock and the second power clock; And And a third pull-up driving unit connected to a low level terminal to drive in response to an output signal of a following stage. The display device of claim 14, further comprising a pull-down part driven in response to the second power clock. The method of claim 15, wherein the second pull-up drive unit A first transistor including a gate electrode connected to a line to which the gate signal is applied, and a conductive path connecting between a terminal to which the first power clock is applied and a terminal to which the second power clock is applied; A second transistor connected between the terminal to which the first power clock is applied and the first transistor and operated as a diode; And A gate electrode connected to the line to which the second power clock is applied, a terminal to which the first power clock is applied, a common node of the first transistor of the second pull-up driver and the second transistor of the second pull-up driver; Including a third transistor including a conductive path for connecting, And the common node is connected to the third pull-up driving unit. The method of claim 16, wherein the third pull-up drive unit A first transistor having two terminals to which the first control signal is applied; A second transistor including a gate electrode connected to the common node of the second pull-up driver, and a conductive path connecting a line to which the first transistor and the second power clock are applied; A third transistor including a gate electrode connected to a line to which an output signal of the next stage is applied, and a conductive path connecting the pull-up unit and the low level terminal; And And a capacitor connecting the pull-up unit and a line to which the output signal of the current stage is applied. The display device of claim 17, wherein the pull-up part includes a gate path connected to a line to which the first control signal is applied, a conductive path connecting a terminal to which the first power clock is applied and a terminal to output the gate signal. A first transistor, The pull-down unit includes: a first transistor having two terminals commonly connected to a terminal for outputting the gate signal; And And a second transistor including a gate electrode connected to the line to which the second power clock is applied, and a conductive path connecting the second transistor and the line to which the first power clock is applied. . 19. The method of claim 18, wherein the phase of the first power clock applied to the odd-numbered stage and the phase of the first power clock applied to the even-numbered stage are inverted from each other and applied to the odd-numbered stage. And the phase of the second power clock and the phase of the second power clock applied to even-numbered stages are inverted with each other. The method of claim 15, wherein the second pull-up drive unit A first transistor including a gate electrode connected to a line to which the gate signal is applied, and a conductive path connecting the terminal to which the first power clock is applied and the terminal to which the second power clock is applied; A second electrode including a gate electrode connected to a line to which a second transistor control signal is applied, a conductive path connecting the terminal to which the first power clock is applied and the first transistor of the second pull-up driver; A second transistor of which a common node of the first transistor is connected to a gate electrode of a hold transistor of the first pull-up driver; A gate electrode to which the second power clock is applied, a terminal to which the first power clock is applied, and the common node between the first transistor of the second pull-up driver and the second transistor of the second pull-up driver are connected. A third transistor including a conductive pass to make; A fourth transistor including a gate electrode to which the gate signal is applied, a conductive path connecting the terminal to which the first power clock is applied and the terminal to which the second power clock is applied; A terminal connected between the terminal to which the first power clock is applied and the fourth transistor of the second pull-up driving unit and operated as a diode, wherein a common node with the fourth transistor is connected to the gate electrode of the second transistor; 5 transistors; And A sixth path including a gate electrode connected to a line to which the second power clock is applied, a terminal to which the first power clock is applied, and a conductive path connecting the common node between the fourth transistor and the fifth transistor A display device comprising a transistor. The method of claim 15, wherein the second pull-up drive unit A first transistor including a gate electrode connected to a line to which the gate signal is applied, a conductive path connecting a terminal to which the first power clock is applied and a terminal to which the second power clock is applied; A first conductive path connecting a gate electrode to which a second transistor control signal is applied, a terminal to which the first power clock is applied, and the first transistor of the second pull-up driver; A second transistor having a common node with a transistor connected to a gate electrode of a hold transistor of the first pull-up driver; A conductive path connecting a gate electrode to which the second power clock is applied, a terminal to which the first power clock is applied, and a first transistor of the second pull-up driver and a second transistor of the second pull-up driver; A third transistor comprising; A fourth transistor including a gate electrode connected to a line to which the gate signal is applied, a conductive path connecting a terminal to which the first power clock is applied and a terminal to which the second power clock is applied; A fifth terminal connected to the terminal to which the first power clock is applied and the fourth transistor of the second pull-up driver, operated as a diode, and a common node of the fourth transistor is connected to the gate electrode of the second transistor transistor; A sixth path including a gate electrode connected to a line to which the second power clock is applied, a terminal to which the first power clock is applied, and a conductive path connecting the common node between the fourth transistor and the fifth transistor transistor; And And a seventh transistor including a gate electrode connected to the common node between the fourth transistor and the fifth transistor, and a conductive path connecting the first pull-up driver and a terminal from which the gate signal is output. . The method of claim 15, wherein the second pull-up drive unit A first transistor including a gate electrode connected to a line to which the gate signal is applied, a conductive path connecting a terminal to which the first power clock is applied and a terminal to which the second power clock is applied; A first conductive path connecting a gate electrode to which a second transistor control signal is applied, a terminal to which the first power clock is applied, and the first transistor of the second pull-up driver; A second transistor having a common node with a transistor connected to a gate electrode of a hold transistor of the first pull-up driver; A gate electrode to which the second power clock is applied, a terminal to which the first power clock is applied, and the common node between the first transistor of the second pull-up driver and the second transistor of the second pull-up driver are connected. A third transistor; A fourth transistor including a gate electrode connected to a line to which the gate signal is applied, a conductive path connecting a terminal to which the first power clock is applied and a terminal to which the second power clock is applied; A terminal connected to the terminal to which the first power clock is applied and the fourth transistor of the second pull-up driving unit and operated as a diode, wherein a common node with the fourth transistor is connected to the gate electrode of the second transistor; 5 transistors; A sixth transistor including a gate electrode connected to a line to which the second power clock is applied, a terminal to which the first power clock is applied, and a conductive path connecting a common node between the fourth transistor and the fifth transistor ; And And a seventh transistor including a gate electrode connected to the common node of the first transistor and the second transistor, and a conductive path connecting the first pull-up driver and a terminal to which the gate signal is output. Display device.