TWI413965B - Shift register and display device having the same - Google Patents

Abstract

PURPOSE: A shift register and a display device having the same are provided to reduce the number of external bus lines. CONSTITUTION: The shift register includes a plurality of stages generating a gate signal to a plurality of gate lines of a display device in sequence. According to each stage, the first pull-up driver(230) generates the first control signal in response to an output signal or a control signal of a prior stage. A pull-up unit(210) generates an output signal of a current stage in response to the first power clock and the first control signal. The second pull-up driver(250) generates the second control signal in response to the first power clock and the second power clock. And the third pull-up driver(240) drives in response to the output signal of a following stage by being connected to a low level port.

Description

Displacement register and display device with displacement register

BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a gate driver for generating a scan signal in a display device, and more particularly to a shift register capable of operating with a reduced number of external bus bars in a gate driver, and using this A display device for a displacement register.

For example, an image display device of a liquid crystal display device generally has a gate driver, a glass wafer (COG), or the like using a tape carrier package (TCP). However, in this display device, it is not easy to improve the design efficiency and reduce the manufacturing cost of the gate driver circuit and the display device.

To alleviate the difficulty, for example, a gate driving technique that does not have a gate driver integrated circuit (IC) is developed. In other words, a display device has a gate drive that is not mounted in the form of an integrated circuit on the display panel, but is formed entirely on a portion of the display panel. The structure of this gate drive element is referred to herein as "less gate IC structure." In the case of fewer gate IC structures, amorphous germanium film transistors (amorphous germanium TFTs) are commonly used. An example of an amorphous germanium TFT can be found in U.S. Patent No. 5,517,542 and commonly assigned Korean Patent No. 2002-3398 (or Korean Patent Publication No. 2002-66962). A conventional gate drive component having fewer gate IC structures includes one or more shift registers to provide a scan signal to a display panel.

Figure 1 depicts a single-stage circuit diagram of a conventional shift register. Referring to FIG. 1, a conventional displacement register single stage 100 includes a pull-up element 110, a pull-down element 120, a pull-up drive element 130, and a pull-down drive element 140. Single-stage The 100 can generate a gate signal (or a scan signal) in response to a scan start signal STV or an output signal of a previous stage. In the case where the single stage 100 is the first stage of a shift register, the single stage 100 can receive the scan start signal STV to output the gate signal. In contrast, in the case where the single stage 100 is not the first stage of a shift register, the single stage 100 can receive a gate signal generated from a previous stage to output a gate signal. A displacement register having this single stage is a TFT face plate mounted on a display device.

Figure 2 depicts a block diagram of a conventional shift register including multiple stages as shown in Figure 1. Referring to Figures 1 and 2, the shift register 174 has: 'N' stages SRC ₁ - SRC _N to generate 'N' gate signals (or scan signals) GOUT _{1 -} GOUT _{N respectively} ; and a virtual stage SRC _N+1 to provide a control signal to the pre-stage. Each stage of the multi-stage SRC ₁ -SRC _N can receive the first and second clock signals CKV, CKVB, the high and ground level voltages VDD, VSS as the gate turn-off and turn-on voltages VON, VOFF, and from the next stage A control signal that is output.

In particular, the first stage may receive a scan start signal STV other than the aforementioned signal to output a first gate signal GOUT _{1 for} selecting the first gate line. The first gate signal GOUT _{1 is} also provided to an input of the second stage. In addition to the foregoing signals, the second stage SRC ₂ can receive the first gate signal GOUT ₁ from the first stage to output a second gate signal GOUT _{2 for} selecting the second gate line. The second gate signal GOUT _{2 is} also provided to the input of the third stage SRC ₃ . In a similar manner, in addition to the other clock and voltage signals, the Nth stage SRC _N can receive the (N-1)th gate signal from the (N-1)th stage and the one from the virtual stage SRC _N+1 . The control signal is output to select the Nth gate signal GOUT _N .

3 is a waveform diagram of the shift register of FIG. 1. Referring to FIG. 1-3, the first or second clock signal CKV/CKVB can be received in a single stage of the shift register 174, that is, the odd-numbered stage can receive the first clock signal CKV, and the even number The stage can receive the second clock signal CKVB, wherein the phase of the second clock signal CKVB is opposite to the first clock signal CKV. The displacement register 174 can continuously generate a gate signal of a TFT substrate gate line. The first and second clock signals CKV, CKVB can be obtained from an output signal of a timing controller (not shown). Typically, the output signal of the timing controller has an amplitude in the range from 0 volts to 3 volts and can be amplified in the range of -8 volts to 24 volts to drive the amorphous germanium TFT. The first and second clock signals can use an amplified output signal.

As described above, a conventional shift register having a small gate IC structure using an amorphous germanium transistor requires at least five bus bars: a bus bar for transmitting a scan start signal STV, and the scan start signal STV is a start signal in a horizontal direction; a bus line for transmitting a first clock signal CKV to apply a gate turn-off voltage, wherein the bus line is connected to an odd gate line; and a bus line is used to transmit a second line Clock signal CKVB to apply a gate turn-off signal, wherein the bus bar is connected to an even gate line; and some bus bars are used to provide high and ground level voltages VDD, VSS to each of the single stages . The five bus bars are connected to the gate driving IC region of a display panel via a dummy pin of the source driver integrated circuit TCP, or five bus bars are connected to the display panel, and the display surface is connected to the gate Drive area.

However, conventional displacement registers have the following problems. A separate space is needed to form a jumper to transmit signals and power to each stage. In particular, in a small narrow-face liquid crystal display panel having an increased effective display area, the bus bar space is limited. And when five or more bus lines are formed via TCP or FPC, the virtual space of the TCP and the width of the FPC increase, so the manufacturing cost increases, and the space of the bus line is limited. In addition, when an amorphous germanium transistor is used in a gate driver circuit, the amorphous germanium transistor is damaged in a DC bias state such as gate turn-on and turn-off voltages VON, VOFF. As a result, the amorphous germanium transistor fails. In addition, amorphous germanium transistors require a large voltage difference of, for example, -14 volts to 20 volts, so the metal pads of the display panel may be damaged due to large voltage differences. In particular, when the display panel is subjected to high temperatures and moisture, the metal pads are eroded, or unnecessary electrical paths may be formed between the metal blocks due to moisture.

The foregoing and its disadvantages and deficiencies of the prior art can be overcome or mitigated by the use of the displacement register and display device in accordance with the present invention. In one embodiment, the displacement register for providing a gate signal to a corresponding gate line in a display device includes a plurality of single stages to continuously generate a gate signal, wherein each stage of the single stage The method includes: a first pull-up driving component to generate a first control signal or a control signal in response to an output signal of an adjacent front stage; and a pull-up component to respond to a first clock signal and the first control signal Generating a current output signal; a second pull-up driving component to generate at least one second control signal in response to the first clock signal and a second clock signal; and a third pull-up driving component connected to a low position, ringing It should operate with an output signal from an adjacent stage. The single stage also includes a pull-down element that operates in response to the second clock signal. The displacement register can be formed entirely in the selected area of the display panel and the display panel.

The second pull-up driving component includes: a first transistor having a gate receiving the gate signal and a conducting path connected between receiving the first clock signal end and receiving the second clock signal, wherein one a second transistor is coupled between the receiving first clock signal terminal and the first transistor, the second transistor operates as a diode; and a third transistor having a second clock signal received The gate is coupled to a conduction path between the first and second transistor common nodes receiving the first clock signal end and the second pull-up driving element, wherein the common node is coupled to the third pull-up driving element. The third pull-up driving component includes: a first transistor having two ends connected to the first control signal; and a second transistor having a gate and a connection connected to a common node of the second pull-up driving component a conduction path between the first transistor and the second clock signal; a third transistor having a gate connected to the output signal of the adjacent subsequent stage and a connection between the pull-up element and the low-level end a conductive path; and a capacitor connected between the pull-up element and the current output signal.

In another embodiment, the second pull-up driving component includes: a first transistor having a gate receiving the gate signal and connected to receive the first clock signal end and receive the second clock signal a conductive path between the signal terminals; a second transistor having a gate receiving a second transistor control signal end and a first transistor connected to the first clock signal terminal and the second pull-up driving component a conductive path between the first and second transistors of the second pull-up driving element connected to the first pull-up driving element Holding a gate of the transistor; a third transistor having a gate receiving the second clock signal and first and second transistors connected to the first clock signal end and the second pull-up driving element a conductive path between the common nodes; a fourth transistor having a gate receiving the gate signal and a conducting path connected between the receiving the first clock signal end and receiving the second clock signal end; a five-electrode connected between the first clock signal receiving the first clock signal end and the fourth transistor of the control member, wherein the fifth transistor operates as a diode and a common node of the fourth and fifth transistors is connected a gate to the second transistor; and a sixth transistor having a gate connected to the second node and conducting between the first clock signal receiving terminal and the fourth and fifth transistor common node path.

In another embodiment, the second pull-up driving component includes: a first transistor having a gate receiving the gate signal and connected to receive the first clock signal end and receive the second clock signal a conductive path between the signal terminals; a second transistor having a gate receiving a second transistor control signal and a first transistor connected to the first clock signal terminal and the second pull-up driving component a conductive path between the first and second transistors of the second pull-up driving element connected to the gate of the first pull-up driving element holding the transistor; a third transistor having the receiving a gate of the second clock signal and a conduction path connected between the first and second transistor common nodes receiving the first clock signal end and the second pull-up driving element; a fourth transistor having a gate for receiving the gate signal and a conduction path connected between the first clock signal receiving end and the receiving second clock signal end; a fifth transistor connected to receive the first clock signal end and controlling Piece Between the four transistors, wherein the fifth transistor operates as a diode, and a common node of the fourth and fifth transistors is connected to the gate of the second transistor; a sixth transistor having a connection a gate of the second node and a conduction path connected between the first clock signal terminal and the fourth and fifth transistor common nodes; and a seventh transistor having a fourth and fifth electricity connection A gate of the common node of the crystal and a conduction path connected between the first node and an output gate signal terminal.

In still another specific embodiment, the second pull-up driving component includes a first transistor having a gate receiving the gate signal and connecting between receiving the first clock signal terminal and receiving the second clock signal terminal a conductive path; a second transistor having a gate receiving a second transistor control signal and a gate connected between the first transistor receiving the first clock signal end and the second pull-up driving component a conductive path, wherein a common node of the first and second transistors of the second pull-up driving element is connected to a gate of the first pull-up driving element that holds the transistor; and a third transistor that has a second receiving time a gate of the pulse signal and a conduction path connected between the first node of the first clock signal and the first and second transistors of the second pull-up driving element; a fourth transistor having a receiving gate a gate of the pole signal is connected to a conduction path between the receiving first clock signal end and receiving the second clock signal end; a fifth transistor is connected to receive the first clock signal end and the fourth of the control member Between the transistors, the fifth of which The body works like a diode, and a common node of the fourth and fifth transistors is connected to the gate of the second transistor; a sixth transistor having a gate connected to the second node and connected Receiving a conduction path between the first clock signal end and the fourth and fifth transistor common nodes And a seventh transistor having a gate connected to the common node of the first and second transistors and a conduction path connected between the first node and an output gate signal terminal.

These and other objects, features and advantages of the present invention will become apparent from

DETAILED DESCRIPTION OF THE INVENTION The specific embodiments are disclosed herein. However, the specific structural and functional details disclosed herein are merely illustrative of the specific embodiments of the invention.

4 is a block diagram depicting a shift register in accordance with an embodiment of the present invention. The shift register includes: 'N' level ASRC ₁ -ASRC _{N for} generating a gate signal (or scan signal) GOUT ₁ -GOUT _{N respectively} ; and a virtual stage ASRC _N+1 for generating a control The signal is supplied to a virtual gate signal GDUMMY of the pre-stage ASRC _N.

When a display panel (for example, a liquid crystal display panel) is formed, the displacement register is formed on the phase plane. The display plane has switching means formed on the gate line (or scan line) and the area defined by the data line. The shift register can output gate signals GOUT ₁ -GOUT _N , each of which is provided as a scan signal to a corresponding one of the switching devices.

In the shift register, each of the ASRC ₁ -ASRC _N stages has first and second clock terminals CK ₁ , CK ₂ for receiving externally provided first and second clock signals CKV, CKVB. Each of the first and second clock signals CKV, CKV is inverted from each other. The relative stages ASRC ₁ -ASRC _N also have first to third control signals CT ₁ -CT ₃ for receiving corresponding control signals and an output terminal OUT to generate relative gate signals GOUT ₁ -GOUT _N .

In particular, the first stage ASRC ₁ receives the first and second clock signals CKV, CKVB via the first and second clock terminals CK ₁ , CK ₂ , respectively. The first stage ASRC ₁ also receives a scan start signal STV via the first and third control terminals CT ₁ , CT ₃ and a second gate signal GOUT generated from the next stage ASRC ₂ via the second control terminal CT ₂ . ₂ . Then, the first stage ASRC ₁ can output the first gate signal GOUT ₁ to select the first gate line. The first gate signal GOUT _{1 is} also supplied to the first control terminal CT _{1 of the} second stage ASRC ₂ .

The second stage ASRC ₂ receives the first and second clock signals CKV, CKVB via the second and first clock terminals CK ₂ , CK ₁ , respectively. The second stage is the ASRC ₂ receives the first gate signal GOUT generated from the first single-stage ASRC ₁ via a first control terminal CT _{1 1} to produce a _second ASRC ₃ and from the third stage via a second control terminal CT Three gate signal GOUT ₃ . ₂ also via the third control terminal of the second stage ASRC CT ₃ receives the scan start signal STV. Then, the second stage ASRC ₂ can output the second gate signal GOUT ₂ to select the second gate line. The second gate signal GOUT ₂ is supplied to the first control terminal CT _{1 of the} third stage ASRC ₃ .

In a similar manner, the Nth stage ASRC _N can receive the first and second clock signals CKV, CKVB via the second and first clock terminals CK ₂ , CK ₁ , respectively. The Nth stage ASRC _N can receive the virtual gate signal GDUMMY generated from the virtual stage ASRC _N+1 via the second control terminal CT ₂ . The Nth stage ASRC _N also receives the scan start signal STV via the third control terminal CT ₃ . The Nth stage ASRC _N can output the Nth gate signal GOUT _N to select the Nth gate line. The Nth gate signal GOUT _{N is} also provided to a first control terminal CT _{1 of the} virtual stage ASRC _{N+ 1} .

In this embodiment of the invention, the shift register only needs three bus bars to receive the scan start signal STV and the first and second clock signals CK, CKVB to output the gate for selecting the gate line. The pole signal GOUT ₁ -GOUT _N . In other words, the displacement register does not require the bus bar to receive the ground level and high level voltage required in the conventional shift register.

By reducing the number of bus bars in a shift register, the noise of the coupling between the bus bars can be reduced, and the margin for designing the gate drive circuit (or scan drive circuit) can be obtained. Moreover, the damage of the connection pad caused by moisture can be reduced.

FIG. 5 depicts a single stage circuit diagram of the shift register of FIG. 4, and FIG. 6 depicts a shift register circuit diagram having a single stage of FIG. Referring to Figures 5 and 6, the displacement register stage 200 includes a pull-up element 210, a pull-down element 220, and first, second, and third pull-up drive elements 230, 250, 240. The pole 200 can output a gate signal (or a scan signal) by using the scan start signal STV and the output signals of the previous stage and the next stage.

The pull-up element 210 includes a first NMOS transistor M1, a drain (or a second current electrode) is electrically connected to a first clock electrical terminal CK1; a source (or first current electrode) is electrically connected to the Output GOUT. The pull-up element 210 outputs a gate signal GOUT[N].

The pull-down element 220 includes second and third NMOS transistors M2, M3. The second NMOS transistor M2 has a drain and a gate, and the two electrodes are electrically connected to the output terminal GOUT. The third NMOS transistor M3 has: a drain electrically connected to a source of the second NMOS transistor M2; a source pole electrically connected to the drain of the first NMOS transistor M1; and a gate, It is electrically connected to the second clock signal terminal CK2. In the pull-down element 220, the second NMOS Crystal M2 is operated like a diode.

The first pull-up driving element 230 includes a fourth NMOS transistor M4. The gate and the drain of the fourth NMOS transistor M4 are electrically connected to a first control terminal CT1. A source of the fourth NMOS transistor M4 is electrically connected to the capacitor C of the first node N1.

The second pull-up driving part 250 includes eighth to tenth NMOS transistors M8-M10. The eighth NMOS transistor M8 includes a source electrically connected to the second clock signal terminal CK2 and a gate via the second node N2, which is electrically connected to the output terminal GOUT. The ninth NMOS transistor M9 includes a drain and a gate connected in common to the first clock signal terminal CK1. A source of the ninth NMOS transistor M9 is electrically connected to the drain of the eighth NMOS transistor M8. The tenth NMOS transistor M10 includes: a drain electrically connected to the first clock signal terminal CK1; a gate electrically connected to the second clock signal terminal CK2; and a source electrically connected to the first The drain of the NMOS transistor M8 and the source of the ninth NMOS transistor M9.

In this embodiment, the eighth NMOS transistor M8 has a larger size than the ninth NMOS transistor M9. In other words, the eighth NMOS transistor M8 has a ratio of the channel width (W) to the channel length (L) (W/L) which is greater than the ratio of the ninth NMOS transistor M9. When the gate signal GOUT _N is in a high level state, the eighth NMOS transistor M8 and the ninth NMOS transistor M9 may be simultaneously turned on. In this case, a low level input needs to be maintained on the gate of the sixth NMOS transistor M6 to perform the hold function. In order to achieve this, the W/L ratio of the eighth NMOS transistor M8 is larger than the W/L ratio of the ninth NMOS transistor M9.

The third pull-up driving element 240 includes a capacitor C and fourth to seventh NMOS transistors M5-M7. The capacitor C is electrically connected to a gate of the first NMOS transistor M1 and an output terminal GOUT. The drain and gate of the fifth NMOS transistor M5 are electrically connected to the capacitor C at the first node N1. A drain of the sixth NMOS transistor M6 is electrically connected to a source of the fifth NMOS transistor M5. A gate of the sixth NMOS transistor M6 is electrically connected to the first clock signal terminal CK1. A source of the sixth NMOS transistor M6 is electrically connected to a second node N2, wherein the second node N2 is connected to a second clock signal terminal CK2.

A drain of the seventh NMOS transistor M7 is electrically connected to the capacitor C at the first node N1. A gate of the seventh NMOS transistor M7 is electrically connected to a second control terminal CT2. A source of the seventh NMOS transistor M7 is electrically coupled to a low level CT3 or STV signal. In the third pull-up driving element 240, the fourth and fifth NMOS transistors M5 operate as a diode.

When the first NMOS transistor M1 is implemented using an amorphous germanium transistor, it has a low electron mobility, so the first NMOS transistor M1 needs to have a sufficient size to provide a gate scan signal with a display device, wherein The scan signals have a high voltage difference in the range of, for example, from about 20 volts to about -14 volts. For example, in the case of a liquid crystal display device having a size of about 12.1 Å (30.734 cm), the parasitic capacitance of a gate line is from about 250 pF to about 300 pF. In the case where the first NMOS transistor M1 is implemented using an amorphous germanium transistor designed according to the 4 micron minimum design rule, the first NMOS transistor M1 requires a channel length (L) of about 4 micrometers and a channel width of about 5500 micrometers ( W). Therefore, the gate and the 汲 of the first NMOS transistor M1 The parasitic capacitance between the poles will increase.

In the case where the parasitic capacitance between the gate and the drain of the first NMOS transistor M1 is about 3 pF, since the parasitic capacitance is electrically coupled with the clock signals CKV, CKVB ranging from about 20 volts to about -14 volts. Therefore, the first NMOS transistor M1 will not operate correctly, and it operates as the same coupling capacitor, so that a gate signal can be applied to the first NMOS transistor M1. If there is no device to maintain the coupling capacitor with the gate-off voltage VOFF, a gate voltage of the first NMOS transistor M1 may range from about 20 volts to about -14 volts, and the first NMOS transistor M1 can produce '20 An output of the volt-Vth' maximum (here, Vth is a gate threshold voltage of the first NMOS transistor M1). When this output is supplied to the gate line of a liquid crystal display panel, the display quality is deteriorated.

The displacement register of the present invention solves this problem by using the sixth NMOS transistor M6 and the third NMOS transistor M3 to maintain the gate-off voltage VOFF on the gate of the first NMOS transistor M1. The sixth NMOS transistor M6 performs a holding operation of maintaining the gate of the first NMOS transistor M1 at the gate-off voltage VOFF. Moreover, in a time other than the first NMOS transistor M1 generating an active gate signal to excite a corresponding pixel time period, the third NMOS transistor M3 will output the gate signal GOUT from the first NMOS transistor M1. [N] Pull down to the gate turn-off voltage VOFF level (or ground voltage level).

During operation, the previous gate signal GOUT[N-1] supplied from a previous stage is applied to the fourth NMOS transistor M4 operating as a diode. The fourth NMOS transistor M4 can receive the previous gate signal as the same carrier signal GOUT[N-1]. The eighth NMOS transistor M8 can be turned on with a high level of the current gate signal GOUT[N]; as a result, the sixth NMOS transistor M6 is turned off. On the other hand, when the current gate signal GOUT[N] is inactive (ie, a low level), the eighth NMOS transistor M8 will be in a closed state. In this case, the ninth NMOS transistor M9 operates as a diode, so a high level signal can be applied to the sixth NMOS transistor M6. When the first clock signal CK1 is in a low level state, and the second clock signal CK2 is in a high level state, the tenth NMOS transistor M10 is turned on, so a low level signal can be applied to the sixth NMOS battery. Crystal M6. As a result, the second pull-up driving element 240 can supply a control signal having the same phase as the first clock signal CK1 to the sixth NMOS transistor M6.

Due to the large capacitance of the NMOS transistor, the first NMOS transistor M1 can perform a function of maintaining a low level. When the first clock signal CKV changes from a low level state to a high level state, the sixth NMOS transistor M6 can perform a holding operation to prevent a gate voltage of the first NMOS transistor M1 from becoming a higher threshold voltage. . Specifically, when the first clock signal CKV changes from a low level state to a high level state, the current gate signal GOUT[N] will be in a high level state, and the eighth NMOS transistor M8 is turned on. Therefore, since the gate of the sixth NMOS transistor M6 is in a low level state, the sixth NMOS transistor M6 electrically connected to the drain of the eighth NMOS transistor M8 is turned off.

The seventh NMOS transistor M7 can receive the next gate signal GOUT[N+1] via its gate and discharge the capacitor C to the gate turn-off voltage level in response to the next gate signal GOUT[N+1] Quasi VOFF. When the seventh NMOS transistor When M7 is turned on, the scan start signal STV of the gate turn-off voltage level VOFF can be applied to the source of the seventh NMOS transistor M7.

As described above, the displacement register having the amorphous germanium transistor can generate a gate signal without a separate voltage line that can supply the gate turn-off voltage VOFF and the gate turn-on voltage VON.

FIG. 7 is a single-stage circuit diagram of a shift register according to another embodiment of the present invention, and FIG. 8 is a circuit diagram of a shift register including a single stage of FIG. In FIG. 7, the same elements as those shown in FIG. 5 are denoted by the same reference numerals, and a repetitive description may be avoided, and thus, a detailed description will not be given.

Referring to FIGS. 7 and 8, a single stage of a displacement register of the present invention includes a pull-up element 210, a pull-down element 220, a first first pull-up driving element 230, a second pull-up driving element 350, And a third pull-up driving element 240. The single stage 300 can output a gate signal (or a scan signal by using a scan start signal STV, a previous output signal GOUT[N-1] of the previous stage, and a next output signal GOUT[N+1] of the next stage. ). In this embodiment, the pull-up element 210, the pull-down element 220, the first pull-up driving element 230, and the third pull-up driving element 240 have a pull-up element 210, a pull-down element 220, and a first pull-up driving element, respectively. 230, substantially the same function and structure as the third pull-up driving element 240 of FIG. Therefore, further description regarding the pull-up element 210, the pull-down element 220, and the first pull-up driving element 230 of FIG. 7 will be omitted.

The second pull-up driving element 350 includes eighth to thirteenth NMOS transistors M8-M13. The eighth NMOS transistor M8 includes: a source electrically connected to the second node N2, and the second node N2 is connected to the second clock signal end CK2; and a gate electrically connected to the output terminal GOUT. The ninth NMOS transistor M9 includes: a drain electrically connected to the first clock signal terminal CK1; and a source electrically connected to a drain of the eighth NMOS transistor M8. The tenth NMOS transistor M10 includes: a drain electrically connected to the first clock signal terminal CK1; a gate electrically connected to the second clock signal terminal CK2; and a source electrically connected to the first The drain of the NMOS transistor M8 and the source of the ninth NMOS transistor M9.

The eleventh NMOS transistor M11 includes: a source electrically connected to the second clock signal terminal CK2; and a gate electrically connected to the gate of the eighth NMOS transistor M8. The twelfth NMOS transistor M12 includes: a drain and a gate connected to the first clock signal terminal CK1 in common; and a source electrically connected to the gate of the ninth NMOS transistor M9 and the eleventh NMOS The drain of the transistor M11. The thirteenth NMOS transistor M13 includes: a drain electrically connected to the first clock signal terminal CK1; a gate electrically connected to the second clock signal terminal CK2; and a source electrically connected to The drain of the eleventh NMOS transistor M11 and the source of the twelfth NMOS transistor M12.

In operation, when the current gate signal GOUT[N] is in an active state (ie, a high level state), the sixth NMOS transistor M6 is maintained in a closed state when the eighth NMOS transistor M8 is turned on. In this case, a low voltage is applied to the gate of the ninth NMOS transistor M9. Specifically, since the gates of the eighth NMOS transistor M8 and the eleventh NMOS transistor M11 can receive the electrical current output signal GOUT[N], they are turned on. Therefore, the ninth NMOS transistor M9 electrically connected to the drain of the eighth NMOS transistor M8 and the drain of the eleventh NMOS transistor M11 is turned off, thereby increasing the channel resistance. anti. Therefore, even when the ninth NMOS transistor M9 and the eighth NMOS transistor M8 are simultaneously turned on, a low level signal can be applied to the sixth NMOS transistor M6.

When the current gate signal GOUT[N] is in an inactive state (ie, a low level state), the eighth NMOS transistor M8 is in a Veter state, and the sixth NMOS transistor M6 can be on its gate. A control signal is received, and the phase of the control signal is the same as the first clock signal CKV. Specifically, since the second clock signal terminal CK2 is in an active state, the tenth NMOS transistor M10 and the thirteenth NMOS transistor M13 electrically connected to the second clock signal terminal CK2 are turned on. Therefore, the gate of the ninth NMOS transistor M9 is at a low level, so that the sixth NMOS transistor M6 is turned off.

In this embodiment, the second pull-up driving element 350 having the eighth to thirteenth NMOS transistors M8-M13 can generate a control signal that turns on the sixth NMOS transistor M6 to perform a holding operation.

The first NMOS transistor M1 can perform a function of sampling the first clock signal CKV. In other words, the first NMOS transistor M1 can perform a function of maintaining a low level of the first clock signal CKV through the parasitic capacitance. Moreover, when the first clock signal CKV is changed from a low level to a high level, the sixth NMOS transistor M6 performs a holding operation. In other words, the sixth NMOS transistor M6 can prevent the gate of the first NMOS transistor M1 from exceeding the threshold voltage of the first NMOS transistor M1.

When the W/L ratio of the ninth NMOS transistor M9 is increased, the time constant for turning on the sixth NMOS transistor M6 is reduced. In this embodiment, the W/L ratio of the ninth NMOS transistor M9 is greater than the eighth NMOS transistor. M8, thus reducing the time constant of the sixth NMOS transistor M6.

9 is a single-stage circuit diagram of a shift register in accordance with another embodiment of the present invention, and FIG. 10 depicts a shift register circuit diagram including a single stage of FIG. Referring to FIGS. 9 and 10 , the single stage 400 includes a pull-up element 210 , a pull-down element 220 , a first pull-up drive component 430 , a second pull-up drive component 440 , and a third pull-up drive component 450 . . The single stage 400 can receive the first and second clock signals CKV, CKVB, the gate signals of the preamplifier and the next stage GOUT[N-1], GOUT[N+1], and the scan start signal STV to output the gate Signal GOUT[N]. In this embodiment, the functions and structures of the pull-up element 210 and the pull-down element 220 are substantially the same as the pull-up element 210 and the pull-down element 220 of FIG. 5, and thus, a detailed description is omitted.

The first pull-up driving component 430 includes a sixth NMOS transistor M6, a seventh NMOS transistor M7, and a capacitor C. The fifth NMOS transistor M5 of the third pull-up driving element 240 of FIG. 5 is not included in the specific embodiment of FIG. 9 as compared to the register stage of FIG.

In the third pull-up driving element 450, the fourth NMOS transistor M4 has: a gate and a drain, which are commonly connected to the first control signal CT1 to receive the previous gate signal GOUT[N-1] and a source, It is electrically connected to the first node N1, and the first node N1 is connected to the gate of the first NMOS transistor M1 in the pull-up element 210. The sixth NMOS transistor M6 includes: a drain electrically connected to the first node N1; a source electrically coupled to the output terminal GOUT and a gate to receive a signal from the second pull-up driving component 440.

The seventh NMOS transistor M7 includes: a drain electrically connected to the first node N1; a source electrically connected to the third control terminal CT3 to receive the scan The start signal STV; and a gate connected to the second control terminal CT2 to receive the next gate signal GOUT[N+1] from the next stage. The capacitor C is electrically connected between the first node N1 and the output terminal GOUT.

The second pull-up driving element 440 includes eighth, ninth, and tenth NMOS transistors M8, M9, M10. The eighth NMOS transistor M8 includes: a source electrically connected to the second node N2, and the second node N2 is coupled to the second clock signal terminal CK2 to receive the second clock signal CKVB; and a gate It is electrically connected to the output terminal GOUT and the source of the sixth NMOS transistor M6.

The ninth NMOS transistor M9 includes a source electrically connected to a drain of the eighth NMOS transistor M8, and a drain and a gate connected in common to the first clock signal terminal CK1 to receive the first clock. Signal CKV. The tenth NMOS transistor M10 includes: a drain electrically connected to the first clock signal terminal CK1; a gate electrically connected to the second clock signal terminal CK2; and a source electrically connected to the first The drain of the NMOS transistor M8 and the source of the ninth NMOS transistor M9. The source of the tenth NMOS transistor M10 is also electrically connected to the gate of the sixth NMOS transistor M6.

In operation, the eighth NMOS transistor M8 can be turned on or off in response to the current gate signal GOUT[N]. When the current gate signal GOUT[N] is in an active state (ie, a high level), the eighth NMOS transistor M8 will be in a conducting state, so the sixth NMOS transistor M6 will be turned off. On the other hand, when the current gate signal GOUT[N] is in an inactive state (ie, a low level), the eighth NMOS transistor M8 will be in a closed state. In this case, a control signal having the same phase as the first clock signal CKV can be applied to the sixth NMOS transistor from the second pull-up driving element 440. M6. In other words, since the ninth NMOS transistor M9 can operate as a diode, when the first clock signal CKV is in a high level state, a high level signal can be applied to the sixth NMOS transistor M6. When the first clock signal CKV is in a low level state, the second clock signal CKVB inverted from the first clock signal CKV is in a high level state, so the tenth NMOS transistor M10 is turned on. As a result, a low level signal can be applied to the sixth NMOS transistor M6. Therefore, the second pull-up driving element 440 can supply a control signal having the same phase as the first clock signal CKV to the gate of the sixth NMOS transistor M6.

In this embodiment, when the sixth NMOS transistor M6 is maintained in the off state, a high level voltage is applied to the source of the sixth NMOS transistor M6, and when the sixth NMOS transistor M6 is maintained in the on state, A low level voltage is applied to the source of the sixth NMOS transistor M6.

11 is a single-stage circuit diagram depicting a shift register in accordance with another embodiment of the present invention, and FIG. 12 depicts a shift register circuit diagram including a single stage of FIG. Referring to FIGS. 11 and 12, the single stage 500 includes a pull-up component 210, a pull-down component 220, a first pull-up drive component 430, a second pull-up drive component 350, and a third pull-up drive component 440. The single stage 500 can receive the first and second clock signals CKV, CKVB, the gate signals output from the previous stage and the next stage GOUT[N-1], GOUT[N+1], and the scan start signal STV to output Gate signal GOUT[N].

In this particular embodiment, the function and structure of pull-up element 210 and pull-down element 220 are substantially the same as pull-up element 210 and pull-down element 220 of FIG. The first pull-up driving element 430 of FIG. 11 and the third pull-up pull-up driving element 440 The function and structure are substantially the same as the first pull-up driving element 430 and the third pull-up driving element 450 of FIG. The function and structure of the second pull-up drive element 350 of FIG. 11 is substantially the same as the second pull-up drive element 350 of FIG. Therefore, a detailed description of the pull-up element 210, the pull-down element 220, the first pull-up driving element 430, and the third pull-up driving element 440 will be omitted.

In this embodiment, the size of the ninth NMOS transistor M9 (ie, the W/L ratio) is larger than the eighth NMOS transistor M8. This is because if the size of the ninth NMOS transistor M9 is smaller than that of the eighth NMOS transistor M8, the time constant for turning on the sixth NMOS transistor M6 is increased. Therefore, the size of the ninth NMOS transistor M9 is larger than the size of the eighth NMOS transistor M8 to reduce the time constant.

Figure 13 is a single stage circuit diagram depicting a shift register in accordance with another embodiment of the present invention, and Figure 14 depicts a shift register circuit diagram including a single stage of Figure 13. Referring to FIGS. 13 and 14, the single stage 600 includes a pull-up element 210, a pull-down element 220, a first pull-up drive component 230, a second pull-up drive component 640, and a third pull-up drive component 240. . The single stage 600 can receive the first and second clock signals CKV, CKVB, the gate signals output from the previous stage and the next stage GOUT[N-1], GOUT[N+1], and the scan start signal STV to output the gate The pole signal GOUT[N].

In this embodiment, the functions and structures of the pull-up element 210, the pull-down element 220, the first pull-up driving element 230, and the third pull-up driving element 240 are substantially the same as the pull-down element 220 of FIG. 5, and the first pull-up driving. Element 230 is identical to a three pull-up drive element 240. Therefore, the detailed description will be omitted to avoid redundancy.

The second pull-up driving element 640 includes eighth to fourteenth NMOS transistors M8-M14. The eighth NMOS transistor M8 includes a source electrically connected to the second node, and the second node is connected to the second clock signal terminal CK2 to receive the second clock signal CKVB; and a gate electrically connected To the output GOUT. The ninth NMOS transistor M9 includes: a drain electrically connected to the first clock signal terminal CK1 to receive the first clock signal CKV and a source electrically connected to a drain of the eighth NMOS transistor M8 . The tenth NMOS transistor M10 includes: a drain electrically connected to the first clock signal terminal CK1; a gate electrically connected to the second clock signal terminal CK2 of the second node N2; and a source, It is electrically connected to the drain of the eighth NMOS transistor M8 and the source of the ninth NMOS transistor M9. The source of the tenth NMOS transistor M10 is also connected to the gate of the sixth NMOS transistor M6.

The eleventh NMOS transistor M11 includes: a source electrically connected to the second clock signal terminal CK2; and a gate electrically connected to the gate of the eighth NMOS transistor M8. The twelfth NMOS transistor M12 includes: a source electrically connected to the gate of the ninth NMOS transistor M9 and the drain of the eleventh NMOS transistor M11; and the drain and the gate, which are connected to the first One clock signal terminal CK1.

The thirteenth NMOS transistor M13 includes: a drain electrically connected to the first clock signal CK1; a gate electrically connected to the second clock signal CK2; and a source electrically connected to the first A drain of the eleven NMOS transistor M11 and a source of the twelfth NMOS transistor M12. The fourteenth NMOS transistor M14 includes: a drain electrically connected to the first node N1; a gate electrically connected to the sources of the twelfth and thirteenth NMOS transistors M12, M13, and The gate of the nine NMOS transistor M9; and a source, the electrical connection To the output GOUT.

As shown in FIG. 13, even when a voltage applied to the gate of the fourteenth NMOS transistor M14 is electrically connected to the output terminal GOUT is different from the voltage applied to the gate of the sixth NMOS transistor M6, the sixth NMOS transistor is made. A voltage that is turned on by M6 can be generated.

In this embodiment, the first NMOS transistor M1 can perform the function of sampling the first clock signal CKV. In other words, due to a capacitance of the NMOS transistor, the first NMOS transistor M1 can perform a sampling function to maintain a low level. When the first clock signal CKV changes from a low level to a high level, the sixth NMOS transistor M6 can perform a holding operation, for example, to prevent the gate of the first NMOS transistor M1 from exceeding the threshold voltage of the first NMOS transistor M1.

Figure 15 is a single stage circuit diagram depicting a shift register in accordance with another embodiment of the present invention, and Figure 16 depicts a shift register circuit diagram including a single stage of Figure 15.

Referring to FIGS. 15 and 16, the single stage 700 includes a pull-up element 210, a pull-down element 220, a first pull-up drive element 230, a second pull-up drive element 740, and a third pull-up drive element 240. The single stage 700 can receive the first and second clock signals CKV, CKVB, the gate signals output from the previous stage and the next stage GOUT[N-1], GOUT[N+1], and the scan start signal STV to output the gate Signal GOUT[N]. In this embodiment, the functions and structures of the pull-up element 210, the pull-down element 220, the first pull-up driving element 230, and the third pull-up driving element 240 are substantially the same as the pull-up element 210 and the pull-down element 220 of FIG. The first pull-up driving element 230 is the same as the third pull-up driving element 240. Therefore, the detailed description will be omitted to avoid redundancy.

The second pull-up driving element 740 includes eighth to fourteenth NMOS transistors M8-M14. The eighth NMOS transistor M8 includes: a source electrically connected to the second clock signal terminal CK2; and a gate electrically connected to the output terminal GOUT. The ninth NMOS transistor M9 includes: a drain electrically connected to the first clock signal terminal CK1; and a source electrically connected to a drain of the eighth NMOS transistor M8.

The tenth NMOS transistor comprises: a drain electrically connected to the first clock signal terminal CK1; a gate electrically connected to the second clock signal terminal CK2; and a source electrically connected to the eighth The drain of the NMOS transistor M8 and the source of the ninth NMOS transistor M9. The eleventh NMOS transistor M11 includes a source electrically connected to the second clock signal terminal CK2 and a gate electrically connected to the gate of the eighth NMOS transistor M8.

The twelfth NMOS transistor M12 includes: a source electrically connected to the gate of the ninth NMOS transistor M9; and a drain and a gate connected in common to the first clock signal terminal CK1. The thirteenth NMOS transistor M13 includes: a drain electrically connected to the first clock signal terminal CK1; a gate electrically connected to the second clock signal terminal CK2; and a source electrically connected to The drain of the eleventh NMOS transistor M11 and the source of the twelfth NMOS transistor M12.

The fourteenth NMOS transistor M14 includes: a drain electrically connected to the output terminal GOUT; a gate electrically connected to the sources of the ninth and tenth NMOS transistors M9 and M10; and a source, It is electrically connected to the third pull-up driving element and the fourth NMOS transistor M4 of the end portion of the capacitor (C).

As shown in FIG. 15, even when a voltage applied to the gate of the fourteenth NMOS transistor M14 electrically connected to the output terminal GOUT[N] is different from the gate applied to the sixth NMOS transistor M6, wherein the first The six NMOS transistor M6 is electrically coupled to a fifth NMOS transistor M5 that operates as a diode to generate a voltage that turns on the sixth NMOS transistor M6.

In this embodiment, the first NMOS transistor M1 can perform the function of sampling the first clock signal CKV. In other words, due to a capacitance of the NMOS transistor, the first NMOS transistor M1 can perform a sampling function to maintain a low level. When the first clock signal CKV changes from a low level to a high level, the sixth NMOS transistor M6 can prevent the gate of the first NMOS transistor M1 from exceeding the threshold voltage.

Figure 17 is a circuit diagram depicting a shift register in accordance with another embodiment of the present invention. Referring to FIG. 17, the shift register includes an 'N' level BSRC ₁ -BSRC _N and a virtual level BSRC _N+1 . BSRC ₁ -BSRC _N outputs a gate signal (or scan signal) GOUT ₁ -GOUT _N , respectively, and a virtual stage BSRC _N+1 generates a virtual gate signal GDUMMY.

The first stage BSRC ₁ can receive the first and second clock signals CKV, CKVB from an external device via the first and second clock signal terminals CK ₁ , CK ₂ , respectively. The first stage BSRC ₁ also receives a scan start signal STV via the first and third control terminals CT ₁ , CT ₃ . A second gate signal of the first stage also BSRC ₁ via the second control terminal CT ₂ generated from the received second stage BSRC ₂ GOUT _2. Then, the first stage BSRC ₁ can generate the first gate signal GOUT ₁ via the output terminal OUT. The first gate signal GOUT _{1 is} also supplied to the first control terminal CT _{1 of the} second stage BSRC ₂ .

The second stage BSRC ₂ can receive the first and second clock signals CKV, CKVB generated from the external device via the second and first clock signal terminals CK ₂ , CK ₁ , respectively. A first gate signal of a second stage via a first BSRC ₂ also receives a control terminal CT ₁ generated from the first stage BSRC ₁ GOUT _1. The second stage BSRC ₂ also receives the third gate signal GOUT ₃ generated from the third stage BSRC ₃ via a second control terminal CT ₂ . The second stage also BSRC ₂ via the third control terminal CT ₃ receives a gate-off voltage VOFF. Then, the second stage BSRC ₂ can generate the second gate signal GOUT ₂ via the output terminal OUT. The second gate signal GOUT _{2 is} also supplied to the first control terminal CT _{1 of the} third stage BSRC ₃ .

In a similar manner, the Nth stage BSRC _N can receive the first and second clock signals CKV, CKVB from an external device via the first and second clock signal terminals CK ₁ , CK ₂ . Also the RSRC stage N _N first control terminal CT ₁ receives the gate signal from the preceding stage via. The Nth stage BSRC _N also receives the virtual gate signal GDUMMY generated from the virtual stage BSRC _N+1 via a second control terminal CT ₂ . The Nth stage BSRC _N also receives the gate off voltage VOFF via a third control terminal CT ₃ . Then, the Nth stage BSRC _N can generate the Nth gate signal GOUT _N via the output terminal OUT, and the gate signal GOUT _{N is} supplied to a first control terminal CT _{1 of the} virtual stage BSRC _{N+ 1} .

In this embodiment, the shift register receives only the scan start signal STV, the first and second clock signals CKV, CKVB, and the gate turn-off voltage signal VOFF to output a gate signal for selecting the gate line. . By using the displacement register of this embodiment, the number of bus lines is reduced because the number of external voltage lines is reduced. In addition, there is an advantage that the margin of the design of the gate driving circuit (or scan driving circuit) can be provided in the display panel, and Reduce or avoid any damage to the connection pads due to moisture.

In this particular embodiment, the single stage of the displacement register can be implemented using any of the stages of Figures 5 through 16 described above. The case of the stage shown in Fig. 5 is that the shift register of Fig. 17 is used, and each of the second to (N+1)th stages can receive the gate turn-off voltage VOFF instead of the scan start signal STV.

Figure 18 depicts a circuit diagram of a display panel including a single stage of the present invention. Referring to FIG. 18, the display panel 1000 includes a display area DA and a peripheral area PA. The display panel 1000 can display an image on the display area DA. The driver circuit for driving the display panel 1000 is disposed in the peripheral area PA. The liquid crystal display panel 1000 also includes a lower substrate and an upper substrate facing each other, and a liquid crystal layer is interposed between the lower substrate and the upper substrate.

The plurality of data lines DL and the gate lines GL are formed in the display area DA. The data line DL is configured in a first direction, and the gate line GL is disposed in a second direction, wherein the second direction is substantially perpendicular to the first direction. A thin film transistor 1100 operating as a switching device is electrically connected to each of the data lines DL and each of the gate lines GL. The switching device 1100 includes: a drain electrically connected to a pixel electrode 1200; a gate electrically connected to a corresponding one of the gate lines GL; and a source electrically connected to the data lines One of the DL's. The image data can be transmitted to the prime electrode 1200 via the data line DL and the switching device 1100.

A data driving element 1400 is disposed in the peripheral area PA. The data driving element 1400 is electrically connected to the data line DL to apply image data to the source of the switching device 1100. A gate driving element 1300 is also disposed in the peripheral area PA. The gate driving element 1300 is temporarily stored, for example, through the displacement shown in FIG. 4 or FIG. Implemented. The gate driving element 1300 is electrically connected to the gate line GL, so the gate driving signal from the gate driving element 1300 can be applied to the corresponding switching device 1100.

The gate drive component (i.e., a shift register) 1300 includes a plurality of single stages. Each of the single stages is electrically connected to a corresponding one of the gate lines GL, so a scan signal (or gate drive signal) output from a single stage can pass through the gate lines GL. One is applied to a gate 1100 corresponding to one of the switching devices. When the scan signal is applied to the gate of the switching device 1100, the data driving element 1400 can supply the image data to the corresponding pixel electrode 1200 in response to the scan signal. The displacement register 1300 of the display panel has a single stage of any of the specific embodiments described above with respect to Figures 5-16.

In addition, the aforementioned shift register can be used for an organic electroluminescent display panel and a liquid crystal display panel without a gate IC structure.

Specific embodiments of the displacement register and display device are described in accordance with the present invention, and modifications and variations will be apparent to those skilled in the art in view of the foregoing. Therefore, it is to be understood that the invention may be practiced otherwise than as described herein.

100,200,300,400,500,600,700‧‧‧Displacement register single stage

130‧‧‧ Pull-up drive components

110,210‧‧‧ Pull-up components

120,220‧‧‧ Pull-down components

140‧‧‧ Pull-down drive components

230,430‧‧‧First pull-up drive component

250,350,640,740‧‧‧Second pull-up drive components

240‧‧‧ Third pull-up drive component

1000‧‧‧ display panel

1100‧‧‧film transistor

1400‧‧‧ data drive components

1200‧‧‧pixel electrode

1300‧‧‧ gate drive components

The present invention will be described in detail below with reference to the accompanying drawings in which: FIG. 1 illustrates a single-stage circuit diagram of a conventional displacement register; FIG. 2 depicts a block diagram of a conventional displacement register; FIG. 3 is a displacement of FIG. a register waveform diagram of a register; FIG. 4 is a block diagram depicting a shift register in accordance with an embodiment of the present invention; 5 is a single-stage circuit diagram of the displacement register of FIG. 4; FIG. 6 is a circuit diagram of the displacement register of FIG. 4; FIG. 7 is a single-stage circuit diagram for describing a displacement register according to another embodiment of the present invention; 8 is a circuit diagram of a displacement register including a single stage of FIG. 7; FIG. 9 is a single-stage circuit diagram for describing a displacement register according to another embodiment of the present invention; FIG. 10 is a diagram showing a displacement of a single stage including FIG. FIG. 11 is a single-stage circuit diagram of a shift register according to another embodiment of the present invention; FIG. 12 is a circuit diagram of a shift register including a single stage of FIG. 11; FIG. 13 is a circuit diagram of a shift register including a single stage of FIG. Another embodiment shows a single-stage circuit diagram of a shift register; FIG. 14 depicts a shift register circuit diagram including a single stage of FIG. 13; and FIG. 15 depicts a displacement temporary storage according to another embodiment of the present invention. Figure 16 depicts a shift register circuit diagram including a single stage of Figure 15; Figure 17 is a single stage circuit diagram depicting a shift register in accordance with another embodiment of the present invention; and Figure 18 depicts 17 single-stage one-position register Road map.

(no component symbol)

Claims (22)

A shift register for providing a gate signal to a corresponding gate line in a display device, the shift register respectively comprising a plurality of single stages for continuously generating the gate signals, the single-stage Each includes: a first pull-up driving component responsive to an output signal of a neighboring pre-stage or a control signal to generate a first control signal; a pull-up component responsive to a first clock signal and the a first control signal to generate a current output signal; a second pull-up driving component responsive to the first clock signal applied to the pull-up element and responsive to a second clock signal to generate at least a second control And a third pull-up drive component coupled to a low level terminal for operation in response to an output signal of an adjacent subsequent stage. The shift register of claim 1, further comprising a pull-down element responsive to the second clock signal operation. The shift register of claim 2, wherein the second pull-up driving component comprises: a first transistor having a gate receiving the gate signal and being connected to receive the first clock signal end And a conductive path between the signal receiving the second clock signal; a second transistor connected between the terminal for receiving the first clock signal and the first transistor, the working of the second transistor Like a diode; and a third transistor having a gate receiving the second clock signal And a conductive path connected between the first and second transistor common nodes for receiving the first clock signal end and the second pull-up driving element, wherein the common node is connected to the third pull-up driving element. The displacement register of claim 3, wherein the third pull-up driving element comprises: a first transistor having two ends connected to the first control signal; and a second transistor having a second transistor a gate connected to the common node of the second pull-up driving component and a conductive path connected between the first transistor and the second clock signal; a third transistor having a connection to the adjacent a gate of the stage output signal and a conduction path connected between the pull-up element and the low level terminal; and a capacitor connected between the pull-up element and the current output signal. The shift register of claim 4, wherein the low level terminal is connected to a ground level signal (VSS) or a scan start (STV) signal. The shift register of claim 5, wherein the pull-up element comprises a first transistor, the first transistor having a gate receiving the first control signal and being connected to receive the first clock signal A conduction path between the terminal and the output signal terminal. For example, the displacement register of claim 6 of the patent scope, wherein the pull-down component comprises: a first transistor having two ends connected to the output gate signal terminal; and a second transistor having a gate connected to the second clock signal and a conduction path connecting the second transistor to the first clock signal. The shift register of claim 7, wherein the first clock signal supplied to the odd-numbered stages has a phase opposite to the first clock supplied to the even-numbered stages. The shift register of claim 8 wherein the second clock signal supplied to the odd stage and the second clock signal supplied to the even stage have opposite phases to each other. For example, the displacement register of claim 1 is wherein the control signal is an STV signal. The shift register of claim 2, wherein the second pull-up driving component comprises: a first transistor having a gate receiving the gate signal and receiving the first clock signal end Receiving a conduction path of the connection between the ends of the second clock signal; a second transistor having a gate receiving the second transistor control signal and receiving the first clock signal end and the second pull-up driving component a conductive path connecting the first transistors, the first and second transistor common nodes of the second pull-up driving component are connected to the first pull-up driving component to maintain a gate of the transistor; a third a crystal having a gate receiving the second clock signal And a conductive path connected between the first clock signal terminal and the first and second transistor common nodes of the second pull-up driving component; a fourth transistor having a gate receiving the gate signal And a conductive path connected between receiving the first clock signal end and receiving the second clock signal end; a fifth transistor connected to receive the first clock signal end and the second pull-up driving component Between the four transistors, the fifth transistor operates as a diode, and a common node of the fourth and fifth transistors is connected to the gate of the second transistor; and a sixth transistor having And connecting a gate of the second clock signal to a conductive path connecting the first clock signal end and the fourth and fifth transistor common nodes. The shift register of claim 2, wherein the second pull-up driving component comprises: a first transistor having a gate receiving the gate signal and being connected to receive the first clock signal And a conductive path between the terminal and the receiving end of the second clock signal; a second transistor having a gate receiving the second transistor control signal and connected to the receiving the first clock signal end and the second a conductive path between the first transistors of the pull-up driving component, wherein the common node of the first and second transistors of the second pull-up driving component is connected to a gate of the first pull-up driving component that holds the transistor a third transistor having a gate receiving the second clock signal and connected to the receiving first clock signal end and the second pull-up driving element a conductive path between the first and second transistors of the common node; a fourth transistor having a gate receiving the gate signal and connected to the receiving the first clock signal end and the receiving second a conduction path between the pulse signal ends; a fifth transistor connected between the first transistor receiving the first clock signal end and the fourth transistor of the second pull-up driving element, the fifth transistor working as a diode, and a common node of the fourth and fifth transistors is connected to the gate of the second transistor; a sixth transistor having a gate connected to the second clock signal and connected Receiving a conduction path between the first clock signal end and the common node of the fourth and fifth transistors; and a seventh transistor having a gate and a connection connected to the common node of the fourth and fifth transistors a conduction path between the first pull-up driving component and an output gate signal terminal. The shift register of claim 2, wherein the second pull-up driving component comprises: a first transistor having a gate receiving the gate signal and being connected to receive the first clock signal end And a conductive path between the receiving end of the second clock signal; a second transistor having a gate receiving a second transistor control signal and connected to the receiving the first clock signal end and the second Pulling a conductive path between the first transistors of the driving element, the first and second transistors of the second pull-up driving element are commonly connected to a gate of the first pull-up driving element that holds the transistor; a third transistor having a gate receiving the second clock signal and being connected between the receiving first clock signal terminal and the first and second transistor common nodes of the second pull-up driving component a conductive path; a fourth transistor having a gate receiving the gate signal and a conduction path connected between the receiving first clock signal end and the second clock signal end; a fifth transistor Connected between the first clock signal receiving end and the fourth transistor of the second pull-up driving element, the fifth transistor operates as a diode, and one of the fourth and fifth transistors a common node is connected to the gate of the second transistor; a sixth transistor having a gate connected to the second clock signal and connected to the fourth clock signal terminal and the fourth a conductive path between the common nodes of the fifth transistor; and a seventh transistor having a gate connected to the common node of the first and second transistors and being connected to the first pull-up driving component A conduction path between the output signal terminals. A display device for displaying an image on a display panel, comprising: a plurality of pixels each having a switching element scanned via a scan signal; and a shift register for providing a gate signal a corresponding gate line of the display panel, the shift register includes a plurality of single stages to continuously generate gate signals respectively, each of the single stages comprising: a first pull-up driving element, which responds to one phase Output signal of the adjacent front stage a first control signal is generated by a signal or a control signal; a pull-up element generates a current output signal in response to a first clock signal and the first control signal; and a second pull-up driving element responsive to the application And generating, by the first clock signal of the pull-up element, at least one second control signal in response to a second clock signal; and a third pull-up driving component, the third pull-up driving component is connected to a low position The quasi-end operates in response to an output signal of an adjacent subsequent stage. The display device of claim 14, further comprising a pull-down element operative in response to the second clock signal. The display device of claim 15, wherein the second pull-up driving component comprises: a first transistor having a gate receiving the gate signal and being connected to receive a first clock signal end and a Receiving a conduction path between the ends of the second clock signal; a second transistor connected between the first clock signal and the first transistor, the second transistor working as a diode; and a third transistor having a gate receiving the second clock signal and being connected between the receiving first clock signal terminal and the first and second transistor common nodes of the second pull-up driving component a conduction path, wherein the common node is coupled to the third pull up drive element. The display device of claim 16, wherein the third pull-up driving element comprises: a first transistor having two connected to the first control signal a second transistor having a gate connected to a common node of the second pull-up driving component and a conducting path connected between the first transistor and the second clock signal; a crystal having a gate connected to the output signal of the adjacent subsequent stage and a conduction path connected between the pull-up element and the low-level terminal; and a capacitor connected to the pull-up element and the current output Between the signals. The display device of claim 17, wherein the pull-up element comprises a first transistor having a gate receiving the first control signal and connected to receive a first clock signal end and an output gate a conduction path between the signal terminals, and the pull-down element includes: a first transistor having two ends connected to an output gate signal end; and a second transistor having a second clock connected thereto a gate of the signal and a conduction path connected between the second transistor and the first clock signal. The display device of claim 18, wherein the first clock signal supplied to the odd-numbered stage and the first clock signal supplied to the even-numbered stage have phases opposite to each other, and the second clock is supplied to the odd-numbered stage The clock signal and the second clock signal supplied to the even-numbered stages have opposite phases to each other. The display device of claim 15, wherein the second pull-up driving component comprises: a first transistor having a gate and a connection for receiving the gate signal Connected to a conductive path between the receiving first clock signal end and a receiving second clock signal; a second transistor having a gate receiving a second transistor control signal and being connected to the receiving a conduction path between a clock signal end and a first transistor of the second pull-up driving component, a common node of the first and second transistors of the second pull-up driving component being connected to the first pull-up a gate of the driving element holding the transistor; a third transistor having a gate for receiving the second clock signal and connected to the receiving first clock signal end and the second pull-up driving element a conductive path between the common nodes of the first and second transistors; a fourth transistor having a gate receiving the gate signal and connected to the receiving first clock signal end and the receiving second clock a conductive path between the signal terminals; a fifth transistor connected between the receiving first first clock signal end and the fourth transistor of the second pull-up driving element, the fifth transistor working as two a polar body, and a common one of the fourth and fifth transistors a point connected to the gate of the dry second transistor; and a sixth transistor having a gate connected to the second clock signal and connected to the first clock signal terminal and the fourth pair A conduction path between the common nodes of the fifth transistor. The display device of claim 15, wherein the second pull-up driving component comprises: a first transistor having a gate for receiving the gate signal and a receiving terminal for receiving the first clock signal and receiving Second clock signal end a conductive path; a second transistor having a gate receiving a second transistor control signal and being coupled between the first transistor receiving the first clock signal and the first transistor of the second pull-up driving component a conductive path, a common node of the first second transistor of the second pull-up driving component is connected to the first pull-up driving component to maintain the gate of the transistor; and a third transistor having the second receiving a gate of the clock signal and a conduction path connected between the first node of the first clock signal and the common node of the first and second transistors of the second pull-up driving element; a fourth transistor; The device has a gate for receiving the gate signal and a conduction path connected between the receiving the first clock signal end and receiving the second clock signal end; a fifth transistor connected to the receiving first Between the clock signal end and the fourth transistor of the second pull-up driving element, the fifth transistor operates as a diode, and a common node of the fourth and fifth transistors is connected to the second electrode a gate of a crystal; a sixth transistor having a connection a gate of the second clock signal and a conduction path connected between the receiving first clock signal end and the fourth and fifth transistors common node; and a seventh transistor having a fourth connection a gate of the common node of the fifth transistor and a conduction path connected between the first pull-up driving component and an output gate signal terminal. The display device of claim 15, wherein the second pull-up driving component comprises: a first transistor having a gate for receiving the gate signal and a conduction path connected between receiving the first clock signal end and receiving the second clock signal; a second transistor having a receiving a gate of a second transistor control signal and a conduction path connected between the receiving first clock signal terminal and the first transistor of the second pull-up driving component, the second pull-up driving component a common node of the first and second transistors is coupled to a gate of the first pull-up driving element that holds the transistor; a third transistor having a gate and a connection for receiving the second clock signal Receiving a conduction path between the first clock signal end and a common node of the first and second transistors of the second pull-up driving element; a fourth transistor having a gate for receiving the gate signal And a conductive path connected between the receiving first clock signal end and the receiving second clock signal end; a fifth transistor connected to the receiving first clock signal end and the second pull-up The fifth transistor between the fourth transistors of the driving element Working as a diode, and a common node of the fourth and fifth transistors is connected to the gate of the second transistor; a sixth transistor having a gate connected to the second clock signal And a conductive path connected between the receiving first clock signal end and the fourth and fifth transistors common node; and a seventh transistor having a gate connected to the common node of the first and second transistors The pole is connected to a conduction path between a first pull-up driving component and an output gate signal terminal.