KR100478341B1 - Driving Circuit For Liquid Crystal Display Device - Google Patents

Abstract

The present invention includes a level shifter unit having first and second input terminals and an output terminal and configured as a differential input pair; A first switch connected to the first input terminal of the level shifter; A second switch connected to the second input terminal of the level shifter; A buffer unit connected to an output terminal of the level shifter; A shift register coupled to the buffer unit; A control logic unit connected to the buffer unit; A third switch connected to the control logic unit; And a level shifter power supply voltage unit supplying power to the level shifter through the third switch, wherein the first to third switches provide driving circuits for ON / OFF control simultaneously by the control logic unit. .

Description

Driving circuit for liquid crystal display {Driving Circuit For Liquid Crystal Display Device}

The present invention relates to a liquid crystal display, and more particularly, to a level shifter used in a driving circuit of a liquid crystal display.

Recently, with the rapid development of the information society, the need for a flat panel display having excellent characteristics such as thinning, light weight, and low power consumption has emerged.

Such a flat panel display can be divided according to whether it emits light by itself or not. A light emitting display device displays light by itself and displays an image by using an external light source. It is called a display device. The light emitting display includes a plasma display panel, a field emission display, an electroluminescence display, and the like. The light receiving display includes a liquid crystal display. crystal display).

Among them, liquid crystal displays have excellent resolution, color display, image quality, and the like, and are being actively applied to notebooks and desktop monitors.

In general, a liquid crystal display device is formed by arranging two substrates on which electric field generating electrodes are formed so that the surfaces on which two electrodes are formed face each other, injecting a liquid crystal material between the two substrates, and then applying voltage to the two electrodes. By moving the liquid crystal molecules by an electric field, the device expresses an image by the transmittance of light that varies accordingly.

1 is a configuration diagram of a conventional liquid crystal display device.

As shown in the drawing, the liquid crystal panel 80 is connected to a plurality of gate wirings 1 and data wirings 3, gate wirings 1, and data wirings 3 that cross and define a pixel region P. As shown in FIG. A switching element (not shown) and a liquid crystal capacitor (not shown) located in the pixel region P and connected to the switching element.

Meanwhile, the driving circuit unit includes an interface 10, a timing controller 20, a gamma power supply unit 40, a gate driver integrated circuit 50, hereinafter referred to as an IC, and a data driver IC 60.

Here, the interface 10 is a portion in which a video signal source is initially transmitted from the outside, and the video signal source includes various clock signals and RGB signals.

Next, the timing controller 20 generates synchronized gate control signals and data control signals through these various clock signals and RGB signals, the gate control signals to the gate driver IC 50, and the data control signals to the data driver IC ( 60).

Next, the gamma power supply unit 40 properly selects an image signal to be transmitted to each pixel P through the RGB signal, and transmits the image signal to the data driver IC 60.

In this case, the gate driver IC 50 is positioned at one edge of the liquid crystal panel 80 so as to connect one end of the plurality of gate wires 1, and the gate signal for each frame is transmitted through the gate control signal. To scan.

On the other hand, the data driver IC 60 is located at the other side edge of the liquid crystal panel 80 adjacent to the gate driver IC 50 so as to connect one end of the plurality of data wires 3, and the data driver IC 60 is connected to each other through the data control signal and the image signal. The data signal corresponding to the gate signal is transmitted to the plurality of data wires 3.

Here, the gate driver IC 50 and the data driver IC 60 include a level shifter, a shift register, and a latch. The level shifter receives a low voltage signal from an external source. A circuit for generating waveforms of high voltage required for driving a liquid crystal panel. A shift register is a circuit for sequentially distributing a signal received from a level shifter to each gate wiring, and a latch can store each data signal for a predetermined period of time. It is a circuit to make sure.

The level shifter used for the driving circuit of such a liquid crystal display will be described in detail with reference to the drawings.

2 is a circuit diagram showing a level shifter of a conventional driving circuit for a liquid crystal display device.

As shown in FIG. 2, the level shifter includes two positive-thin film transistors (P1, P2) and two negative-thin film transistors (N1, N2).

Here, the first N-TFT (N1) and the first P-TFT (P1) are connected to each other to form a first inverter, the second N-TFT (N2) and the second P-TFT (P2) are also connected to each other 2 Make an inverter. That is, the source terminal of the first N-TFT (N1) is grounded, the drain terminal of the first N-TFT (N1) is connected with the drain terminal of the first P-TFT (P1), and the first P-TFT (P1) The source terminal of is connected to the power supply voltage VDD. The second N-TFT (N2) and the second P-TFT (P2) also have the same configuration. This configuration is such that the output of the first inverter 130 becomes the input 140 of the second inverter and the output 120 of the second inverter becomes the input 110 of the first inverter. When it loses its connection with the device, it acts as a kind of memory.

Looking at the connection between these two inverters and the outside, the gate terminals of the first N-TFT (N1) and the first P-TFT (P1) is connected to the first switch (SW1) and the third switch (SW3) and the second Gate terminals of the N-TFT N2 and the second P-TFT P2 are connected to the second switch SW2 and the fourth switch SW4. The first switch SW1 is connected to a low voltage clock A signal and the second switch SW2 is a clock B signal opposite to the clock A signal input to the first switch. Connected with The third and fourth switches SW3 and SW4 are connected to a power supply voltage.

The output of the level shifter includes a first node 110 and a second N-TFT (N2) and a second P-TFT (P2) connected to gate terminals of the first N-TFT (N1) and the first P-TFT (P1). From the second node 120, and the first and second nodes 110 and 120 are connected to an external shift register via a buffer, and at the same time the first to fourth switches SW1, SW2, SW3, It is also connected to control logic that controls SW4).

The operation of the level shifter will be described.

When a start pulse is input to the control logic, the control logic turns on the first to fourth switches SW1, SW2, SW3, and SW4. Accordingly, the clock A (Clock A), which is a low voltage signal, is input to the gate terminals of the first N-TFT (N1) and the first P-TFT (P1) through the first switch SW1, and the clock A (Clock A) Clock B, the opposite signal, is input to the gate terminals of the second N-TFT N2 and the second P-TFT P2. When clock A is at a low level, the first N-TFT N1 is turned off and the first P-TFT P1 is turned on. Therefore, a high level is output to the third node 130. On the other hand, since the clock B has a high level, the second N-TFT N2 is turned on and the second P-TFT P2 is turned off. Therefore, the low level is output to the second node 120 and input to the buffer.

Similarly, when clock A has a high level, a high level is output from the second node 120 and input to the buffer.

Here, the first to fourth switches SW1, SW2, SW3, and SW4 are turned on while the rear shift register is operating. When the shifter register is not operated, the first to fourth switches SW1 and SW2 are controlled through control logic. OFF, SW3, SW4). When the first to fourth switches SW1, SW2, SW3, and SW4 are turned off, no further input signal is input to the level shifter, but the level shifter serves as a memory and thus maintains the previous output.

As for the level shifter of the above structure, while the 1st-4th switches SW1, SW2, SW3, SW4 are OFF, the input of the clock A and the clock B to the level shifter is disconnected. Therefore, there is an advantage that the power consumption can be somewhat reduced, but since the power supply voltage VCC of the level shifter is continuously applied, there is a disadvantage in that static power of the level shifter itself is continuously consumed.

In addition, the first and second N-TFTs (N1, N2) and the first and second P-TFTs (P1) forming a level shifter on two clock A (Clcok A) and clock B (Clock B) signals which are opposite to each other. , Respectively, are inputted to the gate electrode of P2, so the load on the two signals is large, and thus, the response speed of the level shifter becomes a problem in high speed driving.

In order to improve the above-mentioned problems, an object of the present invention is to provide a driving circuit for a liquid crystal display device in which static power consumption is reduced by employing a switch capable of interrupting the power supply voltage of the level shifter itself.

In order to achieve the above object, the present invention includes a level shifter unit having a first input and a second input terminal and an output terminal and configured as a differential input pair; A first switch connected to the first input terminal of the level shifter; A second switch connected to the second input terminal of the level shifter; A buffer unit connected to an output terminal of the level shifter; A shift register coupled to the buffer unit; A control logic unit connected to the buffer unit; A third switch connected to the control logic unit; And a level shifter power supply voltage unit supplying power to the level shifter through the third switch, wherein the first to third switches provide driving circuits for ON / OFF control simultaneously by the control logic unit. .

The control logic unit controls the third switch to be turned off when the shift register does not operate, a first input signal is input to a first input terminal of the level shifter, and the first input signal is input to a second input terminal of the level shifter. A second input signal having a potential opposite to the input signal is input.

The level shifter includes first and second positive-thin film transistors (P-TFTs) and first and second negative-thin film transistors (N-TFTs), and a first input terminal of the level shifter is the first P A gate terminal of the TFT, a second input terminal of the level shifter is a gate terminal of the second P-TFT, and an output terminal of the level shifter is a node between the second P-TFT and the second N-TFT to be.

Source terminals of the first and second P-TFTs are connected to the third switch, drain terminals of the first P-TFT are connected to drain terminals of the first N-TFT, and The source terminal is grounded, the drain terminal of the second P-TFT is connected to the drain terminal of the second N-TFT, and the source terminal of the second N-TFT is grounded.

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Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

3 is a circuit diagram of a level shifter for a liquid crystal display according to an exemplary embodiment of the present invention.

As shown in Fig. 3, the level shifter of the present invention uses a differential input pair including two P-TFTs and two N-TFTs.

The gate terminal of the first P-TFT P11 is connected to the first switch SW11 and the gate of the second P-TFT P12 is connected to the second switch SW12.

The source terminal of the first P-TFT P11 is connected to the third switch SW13 and the drain terminal of the first P-TFT P11 is connected to the drain terminal of the first N-TFT N11. The source terminal of the N-TFT N11 is grounded.

Similarly, the source terminal of the second P-TFT P12 is connected to the third switch SW13 and the drain terminal of the second P-TFT P12 is connected to the drain terminal of the second N-TFT N12. The source terminal of the 2N-TFT N12 is grounded.

Meanwhile, the first node 210 between the first P-TFT P11 and the first N-TFT N11 is connected to the gate terminals of the first and second N-TFTs N11 and N12, and the second The second node 220 between the P-TFT P12 and the second N-TFT N12 is connected to a buffer. The buffer is connected to external shift registers and control logic.

The operation of the level shifter will be described.

When a start pulse is input to the control logic, the control logic turns on the first to third switches SW11, SW12, and SW13. Accordingly, the clock C, which is a low voltage signal, is input to the gate terminal of the first P-TFT P11 through the first switch SW11 and is another low voltage signal that is opposite to the clock C. D (Clock D) is input to the gate terminal of the second P-TFT (P12). When clock C is at a low level, the first P-TFT P11 is turned on so that the first node 210 is at a high level. A high level of one node is input to the gate terminals of the first and second N-TFTs N11 and N12 to turn on the first and second N-TFTs N11 and N12. In this case, since the clock D has a high level, the second P-TFT P12 is turned off. Therefore, a low level signal is output to the second node 220 and input to the shift register through a buffer.

Similarly, when clock C has a high level, a high level signal is output from the second node 220 and input to the shift register through a buffer. In addition, the signal output from the buffer is input to the control logic unit and used to control the first to third switches SW11, SW12, and SW13.

For example, the first to third switches SW11, SW12, and SW13 are controlled to be turned ON while the rear shift register is operating, that is, when the signal output from the buffer is at a high level, and the shifter register is not operated. In other words, when the signal output from the buffer is at a low level, the first to third switches SW11, SW12, and SW13 are controlled to be turned off through the control logic.

Here, the third switch SW13 is connected to the power supply voltage VDD of the level shifter. When the third switch SW13 is turned off, the power supply input to the level shifter is stopped. Therefore, when the output of the level shifter is not used for the operation of the next shift register, that is, when the shift register is not operated and it is not necessary to operate the level shifter, the clock shifter of the clock C (Clcok C) and the clock D (Clock D) The input to the level shifter is not only cut off by the OFF control of the first and second switches SW11 and SW12, but also the supply of the power supply voltage of the level shift itself is cut off by the OFF control of the third switch SW13. Accordingly, it is possible to reduce the static power consumption of the level shifter. In that case, the level shifter's output always remains OFF.

In other words, in the driving circuit for the liquid crystal display according to the present invention, power consumption can be reduced by employing a switch to switch off the power supply of the level shifter when the shift register does not operate.

On the other hand, in the level shifter composed of the differential input pair of FIG. 3, two opposite input signals (Clock C, Clock D) are gate electrodes of two first and second P-TFTs (P11, P12), respectively. Is entered. That is, since only one gate electrode is connected to each of the two input signals Clock C and Clock D, the load on each of the input signals Clock C and Clock D is smaller than in the related art. Therefore, the response speed problem is improved and can be used without any delay even in high speed driving.

The driving circuit for the liquid crystal display device according to the present invention is not limited to the above embodiments, and various changes and modifications can be made by those skilled in the art without departing from the spirit of the present invention. It is apparent that such changes and modifications belong to the present invention through the appended claims.

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As described above, the driving circuit for the liquid crystal display according to the present invention can reduce power consumption by configuring a switch capable of stopping the supply of the power supply voltage of the level shifter when the shift register is not operated. In addition, since only one gate electrode is connected to the input signal of the level shifter, the response speed is fast and smoothly applicable to high speed driving.

1 is a block diagram of a conventional liquid crystal display device.

Fig. 2 is a circuit diagram showing a level shifter of a conventional drive circuit for a liquid crystal display device.

3 is a circuit diagram of a level shifter for a liquid crystal display according to an embodiment of the present invention.

<Description of Symbols for Major Parts of Drawings>

P11: first P-TFT P12: second P-TFT

N11: first N-TFT N12: second N-TFT

210: first node 220: second node

SW11: first switch SW12: second switch

SW13: third switch

Claims (9)

A level shifter portion having first and second input terminals and an output terminal and configured as a differential input pair; A first switch connected to the first input terminal of the level shifter; A second switch connected to the second input terminal of the level shifter; A buffer unit connected to an output terminal of the level shifter; A shift register coupled to the buffer unit; A control logic unit connected to the buffer unit; A third switch connected to the control logic unit; A level shifter power supply voltage unit for supplying power to the level shifter through the third switch. Wherein the first to third switches are ON / OFF controlled simultaneously by the control logic unit. The method of claim 1, And the control logic unit controls the third switch to be turned off when the shift register is not operated. The method of claim 1, A first input signal is input to the first input terminal of the level shifter, and a second input signal having a potential opposite to the first input signal is input to the second input terminal of the level shifter; Driving circuit. The method of claim 1, And said level shifter comprises first and second positive-thin film transistors (P-TFTs) and first and second negative-thin film transistors (N-TFTs). The method of claim 4, wherein The first input terminal of the level shifter is a gate terminal of the first P-TFT, the second input terminal of the level shifter is a gate terminal of the second P-TFT, and the output terminal of the level shifter is the second terminal. And a second node between the P-TFT and the second N-TFT. The method of claim 5, wherein Source terminals of the first and second P-TFTs are connected to the third switch, drain terminals of the first P-TFT are connected to drain terminals of the first N-TFT, and A source terminal is grounded, a drain terminal of the second P-TFT is connected to a drain terminal of the second N-TFT, and a source terminal of the second N-TFT is grounded Circuit. delete delete delete