TWI404000B - Driver for use in flat panel display - Google Patents

Abstract

A driver for use in a flat panel display, the driver adapted to drive segment lines by using a current, the current being generated by referring to a reference current outputted from a reference current source, the driver includes a driving block selector for selecting a reference current driving block to be activated according to a reference current value with respect to the reference current; and a plurality of reference current driving blocks for transferring the reference current value to a part where the segment lines are driven.

Description

Flat panel display driver

The present invention relates to a driver for outputting image data as a corresponding current in a flat panel display, and more particularly to an OLED of an organic electroluminescence (EL) device.

In a flat panel display, luminosity is usually represented by gradation and luminosity. Luminosity means the intensity of light per unit area of the screen, while gradation means the degree of brightness within a set of luminosities, which is displayed based on a video material that is input to the pixel unit.

An organic electroluminescence (EL) is a self-luminous device whose degree of emittance is controlled in proportion to the amount of current supplied. Therefore, in order to control the illumination and level of the organic EL display, a current mirror is used to control a current driver, and one of the pixels output to the flat panel display is controlled by controlling the average current amount by adjusting the switching interval of the output line. Electricity flow.

1 is a block diagram of a flat panel display using a conventional organic electroluminescent LED (OLED).

Referring to FIG. 1, a flat panel display using an OLED includes a display panel having a plurality of unit pixels xy disposed in a matrix, a segment line controller for controlling a segment line, and a common line controller for controlling a common line.

The display panel includes a plurality of segment lines arranged in a longitudinal direction and a plurality of common lines arranged in a lateral direction. One unit pixel xy is arranged at each intersection of the segment line and the common line. Here, the segment line is referred to as a source line, and the common line is referred to as a scan line.

The unit pixel formed at the intersection of the segment line and the common line is arranged in a matrix, and one unit pixel xy is composed of one OLED and one capacitor. One node of the OLED and one node of the capacitor are connected to a segment line, and other nodes of the OLED and other nodes of the capacitor are connected to a common line.

If a predetermined voltage is applied to the common line and current is supplied through the segment line, the OLED emits light. Accordingly, the output of the image material is performed by selecting the common line and then supplying the current corresponding to the pixel material.

The drive used to configure the slice line controller's flat panel display is called the source driver. In the case of an organic EL device, the source driver employs a current driver configuration that supplies the same current (including output image data) as the reference current to each segment line. The output current drive stage that corresponds one-to-one with the segment lines in the source driver is called a channel.

If a high-quality display is used, the number of segment lines and shared lines increases. This problem is negligible for long shared lines that only send switching signals. However, for a segment line that transmits pixel data, as the number of segment lines increases, it is difficult for pixel data to be sent to the actual pixel.

When the drive output current corresponding to the same data is supplied to the segment line, the current and voltage applied to the channel are different due to the difference in resistance of the connection line from the reference current source to the segment line.

To solve this problem, a method of reducing the number of channels managed by a reference current generator is suggested. That is, the number of channels managed by one reference current generator can be reduced by distributing a plurality of reference current generators throughout the wafer. However, this method increases the wafer area. Therefore, reducing the wafer area requires the use of another improved method to compromise channel driveability.

At the same time, a current mirror can be used to match the drive current of individual channels. 2 shows an example of a conventional current mirror in which a current of the same reference current is supplied to the source line channel.

The current mirror is implemented using a high voltage PMOS transistor. Here, the current offset is removed using a PMOS transistor that is higher than the PMOS transistor Mref11 (placed at the source of the diode connection reference current).

However, if the reference current increases in the high-luminance/high-level mode, the voltage difference between the drain and the gate of the reference transistor Mref11 becomes too large, so that the gate voltage (Vg1) is lowered. The drop in the gate voltage (Vg1) of the output transistor Mn11 causes a drop in the voltage within the source of the output transistor Mn11, causing the output voltage (Vout1) to decrease. That is, if the reference current is increased to increase the output current, the output voltage will drop. Therefore, it is difficult to supply sufficient power to the LEDs.

Specifically, since the reference transistor Mref11 is a high voltage transistor having a low current increment with respect to voltage, the voltage drop of Vg1 is large, but the voltage rise due to the gate-source threshold voltage of the low voltage output transistor The height is small.

In order to solve this problem, the applicant of the present application has proposed a driver for a flat panel display, which is disclosed in Korean Patent Application No. 2003-82601 filed by the present applicant.

A flat panel display driver drives a flat panel display by mapping reference currents generated by reference current blocks at a plurality of channels.

Referring to FIG. 3, the driver for the flat panel display includes a reference current block 110 and a plurality of channels 150. The reference current block 110 includes a first current mirror 130 that is configured with a low voltage MOS transistor. The reference current source 112 generates a reference current, and the first current mirror 130 receives a first mapping current generated by mapping a reference current through the input terminal. The first mapping current passes through the first current mirror 130. The reference current region is disposed within the reference current block 110. The channel 150 is configured using a high voltage MOS transistor. Channel 150 includes a second current mirror 151 that outputs a second mapping current as an output signal. Here, the second mapping current is generated by mapping the first mapping current.

According to the above invention, since the reference current and the drive current are not directly mapped, the output voltage does not decrease even if the reference current increases. Also, in the second current mirror 151, two high voltage transistors Mph151 and Mph152 for mapping operations are disposed near the output channel position. Therefore, the possibility of mismatch due to mapping transistor process errors is less likely. Furthermore, since the first current mirror 130 is implemented with a low voltage transistor having a low process error, the current offset is reduced.

Although the low voltage transistor occupies a small area and has a low program error, the operating area is small. Therefore, there is a problem that the input range of the reference current that can be mapped by the first current mirror is narrow.

Accordingly, it is an object of the present invention to provide a driver for a flat panel display that is capable of reducing current drift due to process errors.

Another object of the present invention is to provide a driver for a flat panel display that is capable of supplying a sufficient voltage, i.e., high luminance intensity, to the output stage even in a high current output mode.

Another object of the present invention is to provide a driver for a flat panel display in which a wide range of reference currents can be applied.

According to one aspect of the invention, a driver for a flat panel display is provided that is adapted to drive a segment line by using a current that is generated by reference to a reference current output from a reference current source. The driver includes: a driving block selector for selecting a reference current driving block activated according to a reference current value with respect to a reference current; and a plurality of reference current driving blocks for transmitting a reference current to a portion of the driving segment line value.

Preferably, the reference current drive block includes a first current mirror for mapping the reference current to generate a map current, and the channel includes a second current mirror for mapping the map current to generate an output current.

The invention will be described in detail below with reference to the accompanying drawings.

4 and 5 are circuit diagrams of a driver for a flat panel display in accordance with a preferred embodiment of the present invention.

Referring to Figures 4 and 5, a flat panel display driver drives a flat panel display by mapping a reference current at a plurality of channels. The driver includes a reference current source 12, a drive block selector 14, a reference current drive block 30, and a plurality of channels 50.

The drive block selector 14 selects a reference current drive block that is activated in accordance with the input reference current. The reference current drive block 30 includes a first current mirror in a low voltage MOS transistor configuration. The first current mirror maps the reference current input through the reference current input stage. The plurality of channels 50 include a second current mirror configured in a high voltage MOS transistor. The second current mirror maps the mapped current input through the selected reference current drive block and outputs it as an output signal.

Although the driver includes a plurality of channels that correspond one-to-one with the individual segment lines of the panel, the present invention can be implemented with a channel that is commonly connected to all of the segment lines. In this case, it is preferred to additionally include a segment line selector for selecting the segment line to transmit the channel output. The segment line selector can be implemented using known techniques. For example, the segment line selector can be implemented with a switch that switches the channel output and the segment line.

The invention is applicable to a driver for driving a flat panel display using an OLED.

Figure 4 shows the entire structure of the driver. Figure 5 shows a reference current drive block and a channel. The portion showing a reference current drive block and a channel is the same as the prior art shown in FIG.

The reference current source 12 produces a current corresponding to the intensity of the luminance of the input pixel data. Since the input pixel data is digital and the output of the reference current source is an analog signal, a digital analog converter (DAC) must be provided. However, since the digital analog conversion is familiar with the technique, the description is omitted.

In one embodiment, a reference current drive block 30 includes a first current mirror configured using a pair of low voltage NMOS transistors. The first current mirror is configured by using a first NMOS transistor Mn31 and a second NMOS transistor Mn32. The first NMOS transistor Mn31 has a drain for receiving a reference current, a gate connected to the drain, and a source of the ground, and a second The NMOS transistor Mn32 has a gate connected to the gate of the first NMOS transistor Mn31, a source of the ground, and a drain of the output mapping current Im1.

In one embodiment, a channel 50 includes a second current mirror configured with a pair of high voltage PMOS transistors. The second current mirror is configured by a first PMOS transistor Mph51 and a second PMOS transistor Mph52. The first PMOS transistor Mph51 has a source connected to a high voltage, a gate connected to the drain, and a drain receiving the mapping current Im1. The second PMOS transistor Mph52 has a source connected to a high voltage, a gate connected to the gate of the first PMOS transistor Mph51, and a drain outputting an output current.

Here, the low voltage device is a MOS transistor designed to be driven only in a lower voltage (for example, 2.5-3V) environment, and the high voltage device is designed to be in a lower voltage environment and a higher voltage (for example, about 18V) environment. Drive MOS transistor. The transistor has a low voltage characteristic and a high voltage characteristic by controlling the ratio of the channel width to the channel length when fabricating the MOS transistor.

Although the high voltage device has an advantage in that the operating range is wide and a large amount of power can be supplied to the output terminal, it is disadvantageous in that it occupies a large area on the semiconductor substrate and causes a large number of process errors.

The driver for driving the organic EL panel receives the digital image and the control signal, and activates the scan line, and then generates an output current corresponding to the pixel data of the segment line. The driver includes a structure for driving a reference current based on the pixel data, and a structure for driving an output current corresponding to the one-to-one correspondence with the segment line.

Typically, the reference substrate region 100 of the component for driving the reference current is placed at the center of the semiconductor substrate. An element for driving the output current to the segment line is placed in the channel substrate region 500 adjacent to the reference substrate region 100. In one embodiment, reference current drive block 30 and reference current selector 14 are formed on reference substrate region 100, and channel 50 is formed on channel substrate region 500.

The reference current drive block 30 for generating a reference current supplied to the channel can be configured with a low voltage device. The low voltage device occupies less area than the high voltage device. Thus, the operational range can be extended by forming a plurality of reference current drive blocks on the reference substrate region 100 in which the high voltage device is placed in the prior art.

Only one of the multi-level reference current drive blocks 30 must be driven. This can be made possible by the drive block selector 14 selecting a reference current drive block based on the current supplied from the reference current source.

The image data used in a personal computer (PC) is digital data, and the driver performs digital analog conversion on the image data to convert it into a reference current value. Accordingly, although the drive block selector 14 can be implemented to determine the reference current and turn on the corresponding reference current drive block, it is preferred to select the reference current drive by using the digital pixel data value (which is related to the input data of the driver chip). Block. The selection of the reference current drive block is achieved by grouping the range of digital pixel data values into a predetermined number and transmitting an enable signal to the designated drive block selector upon input of the digital value of the packet range. The range of input digit values is wider than the output digit value. The input digit values are grouped into a predetermined number (output value range) and one output value is assigned to a group. Since this procedure can be implemented using known techniques, such as the use of a multiplexer (MUX), the description is omitted.

In a specific embodiment, a channel switch portion for selecting a channel to be activated may be further included. The channel switch section selects a segment to be driven in the segment line of the shared startup scan line. The channel switch portion includes a MOS transistor Mnh51 having a gate receiving the on/off control signal, a drain connected to the drains of the first and second PMOS transistors of the second current mirror, and an input of the first current mirror The source of the terminal connection. Here, it is preferable to configure the MOS transistor Mnh51 using a high voltage device.

Hereinafter, the operation of the driver for the flat panel display will be described with reference to FIGS. 4 and 5.

The case where the channel switch portion is additionally included corresponds to the case where the channel is selected to turn on the switch, and thus is the same as the case of the channelless switch portion.

Input digital image data into the drive. Next, the driver determines the pulse width to drive the scan line based on the luminosity and level and/or the magnitude of the current output to the segment line. In the program for determining the current magnitude (reference current value), the drive block selector 14 selects a reference current drive block suitable for the drive operation.

If the scan line is activated, the reference current is generated from the reference current source 12 of the driver. The reference current is input to the selected reference current drive block 30.

If the reference current flows from the power supply voltage VDD to the ground voltage in the selected reference current driving block 30, the first and second NMOS transistors Mn31 and Mn32 of the first current mirror are turned on, and are generated by the second NMOS transistor Mn32. The first mapping current Im1 generated by the mapping reference current.

A channel switch Mnh51 is provided to activate only the channel corresponding to the position of the display pixel. If the first mapping current Im1 flows through the channel input PMOS transistor Mph51 of the channel 50 selected by the channel switch Mnh51, the segment driving PMOS transistor Mph52 is also turned on, and a second mapping current Im2 is generated. As described above, the second mapping current Im2 is the output signal of the driver of the flat panel display, which is supplied as a current to the segment line of the flat panel display by the OLED.

Although the reference current region is configured with two NMOS transistors, other components may be further included.

Similarly, although the corresponding current input/output system has been illustrated as being from the reference current source to the reference current drive block, from the reference current drive block to the channel, and from the channel to the segment line, the current input can be the receiver and the current output can be the source. vice versa.

In accordance with the present invention, a driver for a flat panel display can supply sufficient power to a corresponding segment line, or a mirror transistor current misalignment can be prevented by implementing a channel drive current mirror using a transistor having the same specifications as an adjacent transistor.

The present application contains the subject matter related to Korean Patent Application No. 2004-31392, filed on May 4, 2004, in the Korean Patent Office, the entire contents of which is incorporated herein by reference.

While the invention has been described with respect to the specific embodiments of the present invention, it is understood that various changes and modifications may be made without departing from the spirit and scope of the invention as defined by the following claims.

12‧‧‧Reference current source

14‧‧‧Drive block selector

30‧‧‧Reference current drive block

50‧‧‧Multiple channels

100‧‧‧Reference substrate area

110‧‧‧Reference current block

112‧‧‧Reference current source

130‧‧‧First current mirror

150‧‧‧Multiple channels

151‧‧‧second current mirror

500‧‧‧channel substrate area

Mn11‧‧‧ output transistor

Mn31‧‧‧First NMOS transistor

Mn32‧‧‧second NMOS transistor

Mph151‧‧‧High Voltage Transistor

Mph152‧‧‧High voltage transistor

Mnh51‧‧‧MOS transistor/channel switch

Mph51‧‧‧First PMOS transistor

Mph52‧‧‧Second PMOS transistor

Mref11‧‧‧ reference transistor

The above and other objects and features of the present invention will become apparent from the embodiments of the invention, wherein <RTIgt; <RTIgt; </RTI> Figure 1 is a block diagram of a flat panel display using a conventional organic electroluminescence (EL); a circuit diagram of a mirror in which a current is supplied to a segment line shown in FIG. 1; FIG. 3 is a circuit diagram of another conventional current mirror in which a current is supplied to a segment line shown in FIG. 1; FIG. 4 is a conventional current mirror A circuit diagram in which current is supplied to all of the segment lines shown in FIG. 1; and FIG. 5 is a circuit diagram of a current mirror in accordance with a preferred embodiment of the present invention, in which current is supplied to a segment line shown in FIG.

12‧‧‧Reference current source

14‧‧‧Drive block selector

30‧‧‧Reference current drive block

50‧‧‧Multiple channels

100‧‧‧Reference substrate area

500‧‧‧channel substrate area

Mn31‧‧‧First NMOS transistor

Mn32‧‧‧second NMOS transistor

Mph51‧‧‧First PMOS transistor

Mph52‧‧‧Second PMOS transistor

Mnh51‧‧‧MOS transistor/channel switch

Claims (7)

A driver for a flat panel display, the driver comprising: a plurality of reference current driving blocks, each reference current driving block comprising a first current mirror, the first current mirror comprising a pair of low voltage NMOS transistors for Mapping a reference current from a reference current source to generate a first mapping current; a plurality of driving block selectors for selecting one of the reference current driving blocks to be activated according to an enable signal And a voltage NMOS transistor for transmitting the reference current to the selected reference current driving block, wherein the turn-on signal is generated by grouping a range of digital pixel data into a predetermined number, and when the input grouping range is a one-bit value, the turn-on signal is transmitted to a designated drive block selector; at least one channel, each channel includes a second current mirror, the second current mirror includes a high voltage PMOS transistor, wherein the first Mapping current from one of the low voltage NMOS transistors to the associated transistor of the high voltage PMOS transistor, to generate a second And a current switch; and at least one channel switch coupled between the first current mirror and the second current mirror to select a segment line from the plurality of segment lines, wherein the low voltage NMOS transistors are The equal-voltage PMOS transistor occupies a small area, wherein the reference current driving block and the driving block selector are formed on a reference substrate area, and the reference substrate area is disposed in a a central portion of the segment line controller, wherein the channel is formed on a channel substrate region, the channel substrate region is located on both sides of the reference substrate region, wherein a high voltage PMOS transistor has a low current increment with respect to the voltage, and One of the low voltage NMOS transistors has a high current increment with respect to the voltage. The driver of claim 1, wherein the driving block selector receives a digital value of one pixel data, and selects one of the reference current driving blocks to reference a current driving block, wherein the digital value of the pixel data has not been converted. Is the reference current value. A driver as claimed in claim 1, wherein the low voltage NMOS transistor operates in the range of about 2.5V to 3.0V. The driver of claim 1, wherein the high voltage PMOS transistor operates in a range of about 18V. The driver of claim 1, wherein the first current mirror comprises: a first NMOS transistor having a drain receiving one of the reference currents, a gate connected to the drain, and a ground source; and a second NMOS transistor having a gate connected to the gate of the first NMOS transistor, a ground source, and one drain of the mapping current. The driver of claim 1, wherein the second current mirror comprises: a first PMOS transistor having a source connected to a high voltage, receiving a drain of the first mapping current, and connecting to the drain One of the gates; a second PMOS transistor having a source connected to the high voltage, a gate connected to the gate of the first PMOS transistor, and a drain outputting the second mapping current. The driver of claim 1, wherein the channel switch comprises a channel switching transistor having a gate for receiving an on/off control signal, a gate coupled to the second current mirror, and a coupling To one of the sources of the first current mirror.