JP2000020006A - Drive circuit for display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce whole power consumption by effectively preventing a situation in which a through current is made to flow in a high voltage output section constituted by connecting first and second high breakdown strength MOS transistors complementary in a push-pull state. SOLUTION: A PMOSFET 12 in high voltage output sections 11-1 to 11-n is turned on by a divided voltage signal Vd outputted from a voltage divider circuit 15 in an on-state of an NMOSFET 16 in voltage level conversion sections 14-1 to 11-n. An on-off state of the NMOSFET 16 is controlled by a gate control signal Sg from a gate control circuit 17. An on-off state of an NMOSFET 13 in a high voltage output section 17 is controlled by a gate control signal/Sg from the gate control circuit 17. A PMOSFET 19 is turned on with timing being earlier by the prescribed margin time than output stop timing of the gate control signal Sg for turning off the PMOSFET 12, and the PMOSFET 12 is forcedly turned off by short-circuiting a gate and a source of the PMOSFET 12 in an on-state.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a first and second high breakdown voltage M of a complementary structure for applying a high voltage to a scanning electrode or a data electrode of a matrix type display device.
The present invention relates to a display device driving circuit provided with a high-voltage output portion formed by push-pull connection of an OS transistor.

[0002]

2. Description of the Related Art As disclosed in, for example, JP-A-8-137433, in a driver IC for driving an EL panel of a matrix display, a driver IC for applying a high voltage to scanning electrodes and data electrodes of the EL panel is used. A voltage output circuit as shown in FIG. 3 is used as a circuit element.

That is, FIG. 3 shows only one circuit element for applying a high voltage, and a high breakdown voltage PMOS is provided between a power supply terminal + V to which a high voltage is applied and a ground terminal.
A high-voltage output unit 3 in which an FET 1 and a high-voltage NMOSFET 2 are connected in series is provided.
Has a push-pull circuit configuration having an output terminal 4 between each MOSFET 1 and 2. Voltage level converter 5
Is a voltage dividing circuit 6 including a plurality of resistors R1 and R2 and a high breakdown voltage NMOSF between a power supply terminal + V and a ground terminal.
ET7 is connected in series, and its NMO
When the SFET 7 is on, a relatively high voltage level (P from the output voltage of the power supply terminal + V) is output from the output terminal 6a of the voltage dividing circuit 6.
(Lower than the gate threshold voltage of MOSFET1)
Is output. Therefore, in a state where the divided signal is output, a voltage higher than the gate threshold voltage is applied between the gate and the source of the PMOSFET 1, so that the PMOSFET 1 is turned on.

In this case, a gate control signal Sg is input to an input terminal 8 connected to the gate of the NMOSFET 7, and a gate control signal / Sg (is input to an input terminal 9 connected to the gate of the NMOSFET 2. However,
“/” Is a symbol representing a NOT (NOT) logic: an overline is input in FIG. 3 and FIG. 4 described later.

Accordingly, as shown in the timing chart of FIG. 4, at a timing t1, the gate control signal Sg applied to the input terminal 8 is inverted to the "H" level (the gate control signal / Sg applied to the input terminal 9 becomes "H"). When the voltage is inverted to the "L" level), the NMOSFET 7 is turned on by the gate control signal Sg, and the voltage dividing signal is output from the voltage dividing circuit 6, so that the PMOSFET 1 is turned on. It is turned off by the gate control signal / Sg. As a result, a voltage output corresponding to the voltage level of the power supply terminal + V is obtained from the output terminal 4.

Thereafter, at timing t2, when the gate control signal Sg is inverted to "L" level (gate control signal / Sg is inverted to "H" level), the NMO
Since the gate and the source of the PMOSFET 1 have the same potential in response to the turning off of the SFET 7, the PMOSFET 1 is turned off, and the NM is controlled by the gate control signal / Sg.
OSFET2 is turned on. As a result, a voltage output at the ground potential level is obtained from the output terminal 4.

[0007]

In the circuit configuration using the voltage level converter 5 as described above, the PMO controlled by the output (voltage division signal) from the voltage level converter 5 is used.
There is a situation that the on / off speed of the SFET 1 is delayed by the time τ and τ ′ as shown in FIG. Such a delay in the operation speed of the PMOSFET 1 is caused by the PMOSF
This is caused by a stray capacitance component such as the gate capacitance of the ET1. When the capacitor is turned on and off, the charge and discharge of the capacitance component are performed through the resistors R1 and R2. The off delay times τ and τ ′ will occur.

In particular, from the timing when the gate control signal Sg is inverted to the "L" level, that is, from the state where the PMOSFET 1 is turned on and the NMOSFET 2 is turned off,
At timing t2 when the MOSFET 1 is turned off and the NMOSFET 2 is turned on, the PMOSF
Since a delay occurs before the ET1 is completely turned off, a through current flows through the high-voltage output unit 3 during the delay period, which causes a problem that power consumption increases. In order to reduce the through current, a method of increasing the switching speed of the PMOSFET 1 by reducing the resistance values of the resistors R1 and R2 is considered.
2, the power consumption of the voltage level converter 5 increases with the reduction of the resistance value, and the above-mentioned problem cannot be solved.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a high-impedance circuit in which first and second high-voltage MOS transistors having a complementary structure are connected by push-pull. It is an object of the present invention to provide a display device driving circuit that can effectively prevent a situation in which a through current flows in a voltage output unit, thereby realizing low power consumption as a whole.

[0010]

In order to achieve the above-mentioned object, a configuration as described in claim 1 can be adopted. In this configuration, when a high voltage is applied between the scanning electrode and the data electrode of the matrix type display device, a high voltage is applied to the first power supply terminal and a lower voltage (0 V or 0 V) is applied to the second power supply terminal. (Including the case of a minus level).

In such a connection state, the driving means (17)
When the first control signal is output from the controller, the semiconductor switching element (16) in the level converter (14-1 to 14-n) is turned on by the first control signal. Within 1 to 14-n), a resistive voltage dividing circuit (15) divides a high voltage applied between the first and second power supply terminals and divides the high voltage from the output voltage of the first power supply terminal. A divided signal having a voltage level lower by a predetermined amount is supplied to a first high voltage MOS transistor in a high voltage output section (11-1 to 11-n).
The gate signal of the transistor (P-channel type) (12) is output and the MOS transistor (1) is output.
2) is turned on. In the driving means (17), since the output of the second control signal is stopped in the output state of the first control signal, the high voltage output units (11-1 to 11-
The second high voltage MOS transistor (N-channel type) (13) in (n) is off. Thereby, the output terminals (P1 to Pn) of the high-voltage output units (11-1 to 11-n).
Is connected to the first power supply terminal via the first high voltage MOS transistor (12), and the output terminals (P1 to Pn) output a high voltage output corresponding to the voltage level of the first power supply terminal. Is obtained.

On the other hand, when stopping the high voltage output state as described above, the driving means (17) stops outputting the first control signal and outputs the second control signal. At a timing earlier by a predetermined margin time than the output stop timing of the first control signal, an ON command signal for turning on the auxiliary semiconductor switching element (19) is output from the control means (20). By this ON command signal, the auxiliary semiconductor switching element (19)
Is turned on, the gate and source of the first high voltage MOS transistor (12) are short-circuited.
The MOS transistor (12) is turned off. At this time, since the second high-voltage MOS transistor (13) in the high-voltage output section (11-1 to 11-n) is turned on by the second control signal, the high-voltage output section (11-1) is turned on. To 11-n) are connected to the corresponding M
The state is connected to the second power supply terminal via the OS transistor (13), and the high voltage output state from the output terminals (P1 to Pn) is stopped.

In this case, the margin time is changed from the time point when the ON command signal is output to the time when the auxiliary semiconductor switching element (19) is turned on by the first high voltage MOS transistor (12).
Is set to be equal to or longer than the time required for turning off the first high voltage MOS transistor (12), the timing before the second high voltage MOS transistor (13) is turned on by the second control signal. Can cause a through current to flow through the high voltage output sections (11-1 to 11-n) formed by push-pull connection of the first and second high voltage MOS transistors (12, 13). And power consumption is reduced.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment in which the present invention is applied to a driver IC for driving an EL panel will be described below with reference to FIGS. FIG. 1 shows a main part of a driver IC for driving an EL panel, specifically, a part of a drive circuit for applying a high voltage to a signal electrode of the EL panel, for example.

In FIG. 1, the number of high voltage output units 11-1 to 11-n provided in accordance with the number of signal electrodes to be driven (for example, n) is a power supply terminal + V (the first terminal in the present invention). A PMOSFET 12 (also equivalent to a first high voltage MOS transistor) and an NMOSFET 1 between a power supply terminal and a ground terminal (also equivalent to a second power supply terminal).
3 (similarly, a second high-voltage MOS transistor) are connected in series.
And 13 connect their common connection point to the high voltage output section 11-1.
Push-pull configuration connected to the output terminals P1 to Pn of .about.11-n respectively. The PMOSFET 1
2 and the NMOSFET 13 are, for example, LDMOS (Lateral Double-diffused MOS) so as to obtain a sufficient withstand voltage.
: Horizontal double diffusion MOSFET).

A voltage level converter 14-1 provided so as to correspond to each of the high voltage output units 11-1 to 11-n on a one-to-one basis.
.About.14-n (corresponding to the level conversion means in the present invention) is a resistor voltage dividing circuit 15 composed of voltage dividing resistors R1 and R2 between the power supply terminal + V and the ground terminal.
An NMOSFET 16 (corresponding to a semiconductor switching element in the present invention) composed of a DMOS is connected in series. When the NMOSFET 16 is turned on, a divided voltage signal Vd is generated from an output terminal 15a of the voltage dividing circuit 15. Thus, it is provided to the PMOSFET 12 as a gate signal. The voltage level of the divided signal Vd is
It is configured to be lower than the output voltage of the power supply terminal + V by the gate threshold voltage of the PMOSFET 12 or more.

The gate control circuit 17 (corresponding to the driving means in the present invention) is constituted by combining a shift register, a latch, a decoder, and the like. The NMOSFET 16 in the voltage level conversion units 14-1 to 14-n is provided. Output terminals Q1 to Qn for supplying gate control signals Sg to
And NMOS FEs in the high voltage output units 15-1 to 15-n.
T13 has output terminals / Q1 to / Qn for supplying a gate control signal / Sg, respectively. Note that “/” is a symbol (not shown in FIG. 1 and FIG.
(Indicated by an overline in the figure).

In this case, the "H" level gate control signal Sg corresponds to the first control signal of the present invention, and the "H" level gate control signal / Sg corresponds to the second control signal of the present invention. Is what you do. Each of the NMOSFETs 16 in the voltage level converters 14-1 to 14-n is in a state where the first control signal is output from the corresponding output terminal Q1 to Qn, that is, when the gate control signal Sg is at the "H" level. At each time, the NMOSFETs 13 in the high voltage output units 11-1 to 11-n are connected to the corresponding output terminals / Q1 to / Q
n is turned on when the second control signal is output from n, that is, when the gate control signal / Sg is at the “H” level.

Although not specifically shown, the gate control circuit 17 receives a data signal and a shift signal from a display control circuit 18 (corresponding to control means in the present invention), which will be described later, provided separately from the driver IC. A clock, a data latch clock, a blank signal, an output enable signal, and the like are input.
Gate control signals Sg and / Sg are selectively output from 1 to Qn and / Q1 to / Qn.

The P in the high voltage output units 11-1 to 11-n
The MOSFET 12 is provided with a PMOSFET 19 (corresponding to an auxiliary semiconductor switching element in the present invention) so as to correspond to this one-to-one.
ET19 is the corresponding PMOSFET1 in the ON state.
2 are short-circuited between the gate and source (both ends of the resistor R1).

Each of the PMOSFETs 19 is simultaneously turned on and off by a gate signal from the same signal generation circuit 20. More specifically, the signal generating circuit 20 includes a voltage dividing circuit 21 of a resistance voltage dividing type including voltage dividing resistors R3 and R4 between a power supply terminal + V and a ground terminal.
And an NMOSFET 22 made of, for example, an LDMOS connected in series.
A voltage division signal Vd 'is generated from the output terminal 21a of the voltage division circuit 21 when the voltage 22 is turned on, and is supplied to each PMOSFET 19 as a gate signal. The voltage level of the divided signal Vd 'is configured to be lower than the output voltage of the power supply terminal + V by the gate threshold voltage of the PMOSFET 19 or more.

The display control circuit 18 has a function of outputting a low voltage level ON command signal Son to the NMOSFET 22 in the signal generation circuit 20. In this case, the display control circuit 18 outputs the ON command signal Son to the gate. Control circuit 17
The gate control signal Sg from the output terminals Q1 to Qn is output at a timing earlier by a predetermined margin time .DELTA.t than the timing at which the gate control signal Sg is inverted to the "L" level (output stop timing of the first control signal).

Here, when the ON command signal Son as described above is given to the NMOSFET 22,
When the SFET 22 is turned on, the divided voltage V
d 'is output. As a result, a voltage equal to or higher than the gate threshold voltage is applied between the gate and the source of the PMOSFET 19, so that the PMOSFET 19 is turned on, and accordingly, the high voltage output units 11-1 to 11-1
The gate-source of the PMOSFET 12 in -n is short-circuited, and the PMOSFET 12 is forcibly turned off. In this case, after the ON command signal Son is output and before the PMOSFET 19 is turned on, the PMO
Although there is a stray capacitance component such as a gate capacitance of the SFET 19 and a delay time due to the existence of the resistors R3 and R4, the margin time Δt is different from the ON command signal Son.
Is set to be equal to or longer than the time required until the PMOSFET 12 is turned off in response to the turning on of the PMOSFET 19 after the signal is output. The display control circuit 18 outputs the ON command signal Son to output terminals / Q1 to / Q1 of the gate control circuit 17.
The output is stopped at a predetermined timing after the gate control signal / Sg from n is inverted to the “H” level (after the output of the second control signal is started).

According to the configuration of the present embodiment, the following operations and effects can be obtained. Now, as shown in the timing chart of FIG.
, The gate control signal Sg output from the output terminal Q1 of the gate control circuit 17 is inverted to the "H" level (the gate control signal / Sg output from the output terminal / Q1).
Is inverted to the “L” level), the gate control signal Sg causes the NMOSF in the voltage level conversion unit 14-1 to change.
Since the ET 16 is turned on and the voltage dividing signal Vd is output from the voltage dividing circuit 15, the PMOSFET 12 is turned on, and at this time, the NMOSFET 13 is turned off by the gate control signal / Sg. This allows
The output terminal P1 of the high voltage output section 11-1 is connected to the PMOSFE
It is connected to the power supply terminal + V via T12,
A high voltage output corresponding to the voltage level of the power supply terminal + V is obtained from the output terminal P1.

On the other hand, when stopping the high voltage output state as described above, the gate control signal Sg output from the output terminal Q1 of the gate control circuit 17 is inverted to the "L" level at the timing t3 (output terminal). The gate control signal / Sg output from / Q1 is inverted to the "H" level). However, at the timing t2 earlier than the output inversion timing t3 by a predetermined margin time .DELTA.t, the display control circuit 18 An ON command signal Son is output and provided to NMOSFET 22. Then, as described above, the NMOSFET 22 and the PMOSFET 1
9 are sequentially turned on, and the PMOS in the high voltage output unit 11-1 is turned on.
Since the gate and source of the FET 12 are short-circuited, the PMOSFET 12 is turned off. At the timing t3, the NMOS FE in the high voltage output unit 11-1 is controlled by the "H" level gate control signal / Sg.
Since T13 is turned on, the output terminal P1 of the high voltage output unit 11-1 is connected to the ground terminal via the NMOSFET 13, and the high voltage output state from the output terminal P1 is stopped. Become.

In this case, the margin time .DELTA.t is determined from the output timing t2 of the ON command signal Son from the PMOSFET 19.
Is set to be longer than the time required for the PMOSFET 12 to be turned off in response to the turning-on (time indicated by the symbol T in FIG. 2), and as shown in FIG.
The PMOSFET 12 is turned off at a time before the timing t3 when T13 is turned on by the gate control signal / Sg. As a result, the PMOSFET 12 and the NMO
This eliminates the risk of a through current flowing through the high voltage output section 11-1 formed by the push-pull connection of the SFET 13, and reduces power consumption. Of course, such a power consumption reduction effect can be obtained in the other high voltage output units 11-2 to 11-n in the same manner, and as a result, reduction of the whole power consumption can be realized. Further, since the driving of the PMOSFET 19 is performed by the single signal generation circuit 20, the power required for driving the PMOSFET 19 can be suppressed as much as possible.

In addition, the present invention is not limited to the above-described embodiment, but can be modified or expanded as described below. N in the voltage level converters 14-1 to 14-n
The MOSFET 16 can be replaced with another semiconductor switching element such as an IGBT. Although the PMOSFET 19 is provided as the auxiliary semiconductor switching element, this can be replaced with another semiconductor switching element such as an IGBT.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation.

FIG. 3 is a diagram corresponding to FIG. 1 showing a conventional configuration.

FIG. 4 is a diagram corresponding to FIG. 2;

[Explanation of symbols]

11-1 to 11-n are high voltage output units, P1 to Pn are output terminals, 12 is a PMOSFET (first high voltage MOS transistor), and 13 is an NMOSFET (second high voltage MOS transistor).
Transistors), 14-1 to 14-n are voltage level conversion units (level conversion means), 15 is a voltage dividing circuit, and 16 is an NMOS
FET (semiconductor switching element), 17 is a gate control circuit (drive means), 18 is a display control circuit (control means),
Reference numeral 19 denotes a PMOSFET (auxiliary semiconductor switching element), and reference numeral 20 denotes a signal generation circuit.

 ────────────────────────────────────────────────── ─── Continuing from the front page (72) Inventor Tetsuo Hirano 1-1-1 Showa-cho, Kariya-shi, Aichi F-term in DENSO Corporation (reference) 5C080 AA11 BB05 DD26 FF03 FF09

Claims (4)

[Claims] A high-voltage MOS transistor (12) for applying a high voltage to a scan electrode or a data electrode of a matrix-type display device, wherein the first high-voltage MOS transistor (12) is a P-channel type between first and second power supply terminals. ) And an N-channel type second high-voltage MOS transistor (13) by push-pull connection.
3) a plurality of high voltage output units (11-1 to 11-n) for generating a voltage output through output terminals P-1 to P-n; and a plurality of high voltage output units (11-1 to 11-n). ) Are provided in a one-to-one correspondence with the semiconductor switching element (16) and the first state when the semiconductor switching element (16) is turned on.
And a resistive voltage dividing circuit (15) that divides a voltage between the second power terminals to output a voltage dividing signal having a voltage level lower than the output voltage of the first power terminal by a predetermined amount, The divided signal from the voltage dividing circuit (15) is
Level converting means (14-1 to 14-n) for giving a gate signal to the high voltage MOS transistor (12), a first control signal of a low voltage level for turning on the semiconductor switching element (16), and High withstand voltage M of 2
A driving unit for selectively outputting one of a low voltage level second control signal for turning on the OS transistor; and a driving unit for selectively outputting one of the second control signals, the plurality of high voltage output units. 11-1 to 11-n) are provided in a one-to-one correspondence with the first high withstand voltage MOS transistors (12), and have a gate / source of the corresponding first high withstand voltage MOS transistor (12) in the ON state. An auxiliary semiconductor switching element (19) for short-circuiting between them, and an ON command signal for turning on the auxiliary semiconductor switching element (19) at a timing earlier than the output stop timing of the first control signal by a predetermined margin time. A driving circuit for a display device, comprising: a control unit (18). 2. The display device driving circuit according to claim 1, wherein the control means stops outputting the ON command signal after the output of the second control signal is started. 3. The first high withstand voltage MOS according to the turning on of the auxiliary semiconductor switching element (19) after the ON command signal for the auxiliary semiconductor switching element (19) is output, Transistor (12)
3. The display device driving circuit according to claim 1, wherein the driving time is set to be equal to or longer than a required time until the switch is turned off. 4. The semiconductor device according to claim 1, wherein the plurality of auxiliary semiconductor switching elements are P-channel MOS transistors (1).
9) a signal generating circuit (20) for generating a gate signal for simultaneously turning on the plurality of MOS transistors (19) in response to an ON command signal from the control means (18). The driving circuit for a display device according to claim 1, wherein: