JPH11150452A - Level conversion circuit and liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a level conversion circuit in which current consumption is reduced, an output delay time is reduced, and a margin of a voltage level of an input signal (input margin) can be widened. SOLUTION: This level conversion circuit is provided with a level conversion section 1, consisting of PMOS transistors(TR) Q1, Q2 and NMOS TRs Q3, Q4 and with a bias circuit 2 consisting of resistors R11, R12, R13 and a PMOS TR Q5. The resistors R11-R13 in the bias circuit 2 are connected in series between a positive voltage VDD and a ground voltage VSS, and the TR Q5 at connected in parallel with the resistor R12. An input signal DI is fed to a gate terminal of the TR Q5 and a voltage (bias voltage) Vbias at a connecting point between the resistors R12, R13 is fed to a gate terminal of the PMOS TR Q1. Depending on the logic of the input signal, a voltage level of the bias voltage Vbias fed to the level conversion section 1 is changed so as widen the input margin of the level conversion section 1, thereby reducing current consumption.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a level conversion circuit for converting an input voltage to a different voltage level, and more particularly to a so-called ratio type circuit for performing level conversion by turning on and off two types of transistors having different conductivity types. Targets level conversion circuits.

[0002]

2. Description of the Related Art A power supply voltage supplied to a driving circuit for driving a liquid crystal panel and a power supply voltage supplied to a liquid crystal panel are defined by:
For example, the drive circuit is supplied with a power supply voltage on the low side (0 V) on the high side (5 V) and a liquid crystal panel is supplied with a power supply voltage on the low side (−20 V) on the high side (20 V). . Therefore, when a signal is sent from the drive circuit to the liquid crystal panel, it is necessary to provide a level conversion circuit to convert the voltage level.

FIG. 4 is a block diagram of a liquid crystal display having such a level conversion circuit. The liquid crystal display device of FIG. 4 includes a plurality of data lines X1 to Xn and scanning lines Y1 to Y15.
0, a liquid crystal panel 11 arranged in a matrix, a scanning line driving circuit 12 for driving each scanning line, and a data line driving circuit 13 for driving each data line. LCD panel 1
1 is low side VL (about -20V) and high side VH (about 20V)
, While the scanning line driving circuit 12 and the data line driving circuit 13 operate on the low side (0 V) and the high side (5 V).
V).

The scanning lines Y and the data lines X on the liquid crystal panel 11
TFTs 21 are arranged in rows near each intersection of
The gate electrode is connected to the scanning line Y, one of the source electrode and the drain electrode is connected to the data line X, and the other is connected to the liquid crystal layer 22.
And the auxiliary capacitance 23.

As shown in FIG. 5, the scanning line driving circuit 12 includes a level conversion circuit 31 for converting a voltage level of an input signal DI input from the outside, and a voltage of a system clock CP input from the outside. A level conversion circuit 32 for converting the level, a shift register 33 for shifting and outputting the level-converted input signal DIA, and an output control circuit 34 for controlling the output timing of the shift register 33
And The shift register 33 has a plurality of clocked inverters 35 therein, and these clocked inverters 35 have a level-converted system clock CP.
A and CPA bars are input. In this specification, a signal having a bar above a symbol in the drawings is represented by adding a "bar" after the symbol.

FIG. 6 is an operation timing chart of the scanning line driving circuit 12. The level conversion circuit 31 receives an input signal DI which goes high for one cycle every 150 cycles of the system clock CP. The voltage level of the input signal DI is (0 V) on the low side and (5 V) on the high side.
The level conversion circuit 31 converts the level of the input signal DI to a low side (−20 V) and a high side (5 V) input signal D.
Output IA.

Similarly, the level conversion circuit 32 converts the level of the low-side (0 V) high-side (5 V) system clock CP to the low-side (-20 V) high-side (5 V) system clock CPA. , And outputs its inverted signal CPA bar.

The shift register 33 is provided with a level conversion circuit 3
The input signal DIA whose level has been converted by 1 is shifted by one clock and output in synchronization with the system clocks CPA and CPA bar. Based on the output logic of the shift register 33, the output control circuit 34 sets the high level to V1 and the low level to V3, or sets the high level to V
2. A voltage whose low level is V4 is applied to each of the scanning lines Y1 to Y15.
Feed to 0. The reason for switching between the high-level side voltage and the low-level side voltage is to perform liquid crystal driving by a frame inversion method, a line inversion method, or a dot inversion method.

FIG. 7 is a circuit diagram showing a detailed configuration of a general level conversion circuit for switching the amplitude of an input voltage.
The level conversion circuit of (a) uses a positive voltage (for example, 0V to 2V).
0V), and the level conversion circuit of FIG. 7B outputs a negative voltage (for example, −20 V to 5 V). -20V to 20V by combining these two types of level conversion circuits
Can be generated.

An inverter INV for inverting an input voltage is provided in the level conversion circuits shown in FIGS. 7A and 7B. FIG. 8 is a diagram showing a cross-sectional structure of the inverter of FIG. The illustrated inverter includes an N-channel transistor 52 formed on a P-type Si substrate 51 and a P-type Si substrate 51.
And a P-channel transistor 54 formed in an N-well region 53 therein.
Are applied with a voltage of 0 V to 5 V. The substrate voltage is set to (−20) V, and a voltage VDD (= 5 V) is applied in the N-well region.

In FIG. 8, for example, when a voltage of 5 V is applied to the gate terminals of both transistors, the N-channel transistor 52 turns on and the P-channel transistor 54
Is turned off, so that the inverter operates normally. on the other hand,
When a voltage of 0 V is applied to the gate terminals of the transistors 52 and 54, the N-channel transistor 52 should normally be turned off and the P-channel transistor 54 should be turned on, but the substrate voltage in FIG. (−20) V, the N-channel transistor 52 is also turned on. For this reason, it does not operate as an inverter.

As described above, the level conversion circuit of FIG. 7 does not operate properly depending on the level of the input voltage. Therefore, in the liquid crystal display device shown in FIG. 4, a ratio type level conversion circuit as shown in FIG. 9 must be used. There are many.

The level conversion circuit 31 shown in FIG. 9 includes a level conversion section 1 composed of PMOS transistors Q1 and Q2 and NMOS transistors Q3 and Q4, and a bias circuit 2 composed of resistors R1 and R2. The PMOS transistor Q1 and the NMOS transistor Q3 in the level converter 1 are connected in series between the positive voltage VDD and the negative voltage VEE, and similarly, the PMOS transistor Q2 and the NMOS transistor Q4 are also connected to the positive voltage VDD.
And the negative side voltage VEE.

The resistors R1 and R2 in the bias circuit 2
Are connected in series between the positive voltage VDD and the ground voltage VSS. The voltage Vbias at the connection point between the resistors R1 and R2 is applied to the gate terminal of the PMOS transistor Q1, the input signal DI to be level-converted is applied to the gate terminal of the PMOS transistor Q2, and the gate of the NMOS transistor Q4 The gate terminal and the drain terminal of the NMOS transistor Q3 are connected to the terminal. The level-converted input signal DIA is output from between the PMOS transistor Q2 and the NMOS transistor Q4.

FIG. 10 is an operation timing chart of the level conversion circuit 31 of FIG. 9. The operation of the level conversion circuit 31 of FIG. 9 will be described below with reference to FIG. When the bias voltage Vbias applied to the gate terminal of the PMOS transistor Q1 is set to a predetermined voltage, the drain-source of the NMOS transistor Q4 has a certain resistance. Therefore, when the input signal DI is at a low level (time T1 to T2 in FIG. 10), the output DIA becomes substantially equal to the positive voltage VDD, and when the input signal is at a high level (time T2 to T3 in FIG. 10). , The output DIA becomes substantially equal to the negative voltage VEE.

Regardless of the logic of the input signal DI, a constant bias voltage Vbias is always applied to the gate terminal of the PMOS transistor Q1, so that a constant through current Ib always flows between the resistors R1 and R2. A constant through current I1 always flows through the NMOS transistor Q3.
When the input signal DI is at a low level, a through current I2 flows through the PMOS transistor Q2 and the NMOS transistor Q4.

[0017]

The input signal DI input to the level conversion circuit 31 shown in FIG.
It goes high for one cycle every 150 cycles. That is, since the input signal DI is much longer in the low level period than in the high level period, the PMOS transistors Q2 and NM
The period during which the through current I2 flows through the OS transistor Q4 also becomes longer. Therefore, the through current I2 is only consumed wastefully, and as a result, the current consumption of the level conversion circuit 31 in FIG. 9 increases.

As a method of reducing the current consumption, it is conceivable to invert the input signal DI once with an inverter and then input the inverted signal to the level conversion circuit 31, but as described above, depending on the level of the input signal DI, It is not preferable to use the inverter because the inverter does not operate normally.

As another method of reducing the current consumption, a method of increasing the bias voltage Vbias can be considered. When the bias voltage Vbias is increased, the PMOS transistor Q1 operates in the direction of turning off, the current I1 passing through the PMOS transistor Q1 and the NMOS transistor Q3 decreases, and NM
Since the gate voltage VB of the OS transistor Q4 also decreases and the NMOS transistor Q4 operates in the off direction, the PM
The current I2 passing through the OS transistor Q2 and the NMOS transistor Q4 is also reduced. FIG. 11 is a diagram showing how the consumption current IDD of the circuit of FIG. 9 changes according to the bias voltage Vbias. As is apparent from FIG. 11, the higher the bias voltage Vbias, the lower the current consumption IDD.

However, when the through current I2 is reduced, the margin of the voltage level of the input signal DI (input margin) is reduced, and as a result, the operation of the PMOS transistor Q2 and the NMOS transistor Q4 is delayed.

FIG. 12 shows how the input margin of the level conversion circuit 31 in FIG. 9 changes. The horizontal axis represents the bias voltage Vbias, and the vertical axis represents the output voltage of the level conversion circuit 31. A solid line VIH is a gate-drain voltage of the PMOS transistor Q2 when the input signal DI is at a high level, a solid line VIL is a gate-drain voltage of the PMOS transistor Q2 when the input signal DI is at a low level, and a dotted line VHSPEC
Is a threshold voltage VHSPEC for turning off the PMOS transistor Q2, and a dotted line VLSPEC is a threshold voltage VHSPEC for the PMOS transistor Q2.
Is a threshold voltage VLSPEC for turning on.
In FIG. 12, (VHSPEC-VIH) represents the input margin on the high level side, and (VIL-VLSPEC) represents the input margin on the low level side.

As shown in FIG. 12, the bias voltage Vbias
Becomes higher, the input margin on the high level side decreases, and conversely, the input margin on the low level side increases. Also, as the bias voltage Vbias decreases, the input margin on the high level increases, and conversely, the input margin on the low level decreases. That is, as the bias voltage Vbias increases, the voltage level on the high level side of the input signal DI becomes more severe, and conversely, as the bias voltage Vbias decreases, the voltage level on the low level side of the input signal DI decreases. It becomes severe.

However, conventionally, the bias voltage Vbias was not set in consideration of the input margin.
Depending on the voltage level of the input signal DI, level conversion may not be performed normally.

FIG. 13 shows the level conversion circuit 31 of FIG.
FIG. 7 is a diagram showing how the output delay time tpdout changes according to the bias voltage Vbias, and the horizontal axis represents the bias voltage Vbi.
and the vertical axis represents the output delay time tpdout. FIG.
As shown in (2), the output delay time tpdout increases as the bias voltage Vbias increases. Therefore, if the bias voltage Vbias is increased in order to reduce the current consumption, the delay time until the level-converted voltage is output becomes longer.

The present invention has been made in view of such a point, and an object of the present invention is to reduce current consumption and
An object of the present invention is to provide a level conversion circuit capable of shortening an output delay time and expanding a margin (input margin) of a voltage level of an input signal.

[0026]

According to a first aspect of the present invention, there is provided a level conversion circuit for converting a voltage level of an input signal and outputting the converted signal, wherein the input signal has a first logic level. A first transistor that is turned on to output a first voltage; an output terminal connected to an output terminal of the first transistor; and a second voltage output when the input signal has a second logic. And a bias circuit that variably controls the voltage of the gate terminal or the base terminal of the second transistor according to the logic of the input signal.

The invention according to claim 1 will be described with reference to FIG. 1, for example. The "first transistor" is a PMOS transistor Q2, the "second transistor" is an NMOS transistor Q4, and the "bias circuit" is a bias circuit. It corresponds to the circuit 2 respectively. Further, “first logic” is, for example, low level, “second logic” is, for example, high level, and “first logic” is “first logic”.
Is the positive voltage VDD, and the “second voltage” is the negative voltage V
EE.

The invention of claim 3 will be described with reference to FIG. 1, for example. "A plurality of resistors" are resistors R11, R12, R13.
The "division ratio adjusting circuit" corresponds to the PMOS transistor Q5.

The invention of claim 4 will be described with reference to FIG. 1, for example. The "switch element" is a PMOS transistor Q
Corresponding to 5.

The invention of claim 5 will be described with reference to FIG. 1, for example. The "first transistor" is a PMOS transistor Q2, the "second transistor" is an NMOS transistor Q4, and the "third transistor". Is a PMOS transistor Q1, and a "fourth transistor" is an NMOS transistor Q1.
3, the "first resistor" corresponds to the resistor R11, the "second resistor" corresponds to the resistor R12, the "third resistor" corresponds to the resistor R13, and the "fifth transistor" corresponds to the PMOS transistor Q5. I do.

According to a sixth aspect of the present invention, there is provided a liquid crystal panel section having a plurality of scanning lines and signal lines, and a plurality of switching elements connected to these scanning lines and signal lines for driving liquid crystal of each pixel; A shift register that shifts the pulse signal according to a clock signal, and an output control circuit that switches a voltage level of the scanning line based on each output of the shift register. 6. A liquid crystal display device which drives a liquid crystal by turning on / off a switching element, wherein a voltage level of the pulse signal is converted according to a power supply voltage supplied to the liquid crystal panel unit. And a first level conversion unit including a level conversion circuit for converting the voltage level of the clock signal according to a power supply voltage supplied to the liquid crystal panel unit. And a second level conversion unit consisting of the level conversion circuit according to claim 1,
The shift register shifts the level-converted pulse signal output from the first level converter based on the level-converted clock signal output from the second level converter.

The invention of claim 6 will be described with reference to FIGS. 4 and 5, for example.
In addition, the “liquid crystal panel unit” is in the liquid crystal panel 11, the “shift register” is in the shift register 33, the “output control circuit” is in the output control circuit 34, the “first level conversion unit” is in the level conversion circuit 31, The “second level conversion circuit” corresponds to the level conversion circuit 32, respectively.

[0033]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a level conversion circuit to which the present invention is applied will be specifically described with reference to the drawings. Hereinafter, the level conversion circuit in FIG. 5 used in the liquid crystal display device shown in FIG. 4 will be described as an example.

FIG. 1 shows a level conversion circuit 31a according to the present invention.
FIG. 3 is a circuit diagram of one embodiment of the present invention. In FIG. 1, the same components as those in FIG. 9 are denoted by the same reference numerals, and the following description will focus on the differences.

The level conversion circuit shown in FIG. 1 comprises a level conversion section 1 composed of PMOS transistors Q1, Q2 and NMOS transistors Q3, Q4, resistors R11, R12, R13 and a PMOS.
And a bias circuit 2 including a transistor Q5.

The PMOS transistor Q2 in the level converter 1
The positive terminal VDD is applied to the source terminal of the NMOS transistor Q2, the drain terminal of the PMOS transistor Q2 is connected to the drain terminal of the NMOS transistor Q4, and the negative terminal VEE is applied to the source terminal of the NMOS transistor Q4.
The input signal DI is applied to the second gate terminal. The positive side voltage VDD and the negative side voltage VEE are set according to the operating voltage of the liquid crystal panel 11 shown in FIG.
DD is set to (5V), and the negative voltage VEE is set to (-20V).

The positive terminal VDD is applied to the source terminal of the PMOS transistor Q1 in the level conversion section 1,
The drain terminal of the transistor Q1 is connected to the drain terminal of the NMOS transistor Q3.
Is applied with a negative voltage VEE. NMOS
The gate terminal of the transistor Q4 and the NMOS transistor Q
3 and the drain terminal of the PMOS transistor Q1 are commonly connected. The configuration of the level converter 1 described above is the same as the conventional circuit shown in FIG. In FIG. 1, in order to avoid the substrate bias effect, the substrate voltage and the source voltage of each of the transistors Q1 to Q4 are equalized, but it is not necessary to take measures against the substrate bias effect.

The resistors R11 to R13 in the bias circuit 2 are connected in series between the positive voltage VDD and the ground voltage VSS, and the PMOS transistor Q5 is connected in parallel with the resistor R12. An input signal D is applied to the gate terminal of the PMOS transistor Q5.
I is applied, and the voltage (bias voltage) Vbias at the connection point between the resistors R12 and R13 is applied to the gate terminal of the PMOS transistor Q1.

FIG. 2 is an operation timing chart of the level conversion circuit 31a of FIG. 1. Hereinafter, the operation of the level conversion circuit 31a of FIG. 1 will be described with reference to FIG. When the input signal DI is at a low level (time T1 to T2 in FIG. 2), the PMOS transistor Q5 in the bias circuit 2 is turned on, and when the input signal DI is at a high level (time T2 to T3 in FIG. 2). Means that the PMOS transistor Q5 in the bias circuit 2 is turned off. When the PMOS transistor Q5 is turned on, the impedance between both ends of the resistor R12 decreases, and the bias voltage Vbias increases accordingly. Therefore, the bias voltage V
The bias has a higher voltage level when the input signal DI is at a low level than when the input signal DI is at a high level. When the input signal DI is at a low level, the PMOS transistor Q
2 is turned on, the level conversion output DIA becomes the positive side voltage V
The voltage becomes almost equal to DD.

As shown in FIG. 3, the bias voltage Vbias gradually decreases as the voltage of the input signal DI increases, and the voltage of the input signal DI is a certain voltage (3 to 4 V).
When it becomes, it drops sharply.

As the bias voltage Vbias is lower, the PMOS transistor Q1 and the NMOS transistor Q4 operate in the direction of turning on, and the current IB passing through the PMOS transistor Q1 and the NMOS transistor Q3 and the current IOUT passing through the NMOS transistor Q4 increase. . However, the circuit 31 of FIG.
In FIG. 7A, the bias voltage Vbias is lowered only during the period when the input signal DI is at the high level, and the input signal DI becomes high at 150 cycles of the system clock CP.
Times, and only one cycle period of the system clock CP. Therefore, even if the current consumption increases a little during this period, the power consumption of the whole circuit does not increase.

When the bias voltage Vbias becomes low,
As shown in FIG. 12, although the input margin on the low level decreases, the input signal DI always goes to the high level when the bias voltage Vbias decreases in the circuit 31a of FIG. Even if the input margin decreases, it is not affected. That is, as shown in FIG. 12, the lower the bias voltage Vbias, the higher the input margin on the high level side. Therefore, as shown in the circuit 31a of FIG. 1, when the bias voltage Vbias becomes low, the input signal DI becomes high. If the level is set, the input margin becomes wider, and the level conversion operation can be performed stably.

On the other hand, when the bias voltage Vbias increases,
As shown in FIG. 12, the input margin on the high level side decreases, but in the circuit 31a of FIG. 1, when the bias voltage Vbias increases, the input signal DI always goes to the low level. Even if the input margin decreases, it is not affected. That is, as shown in FIG. 12, as the bias voltage Vbias is higher, the input margin on the low level is increased. Therefore, as shown in the circuit 31a of FIG.
If I is set to low level, the level conversion operation can be performed stably.

When the bias voltage Vbias increases,
Since the PMOS transistor Q1 and the NMOS transistor Q4 operate in the off direction, the above-described through currents IB and IOUT
Are both reduced, and current consumption can be reduced. In particular, in the circuit 31a of FIG. 1, since the period during which the bias voltage Vbias is high, that is, the period when the input signal DI is at a low level is very long, reducing the current consumption during this period reduces the power consumption as a whole circuit. It can be significantly reduced.

The output delay time tpdout of the circuit of FIG.
When the input signal DI is at a high level, the bias voltage Vbias decreases, the PMOS transistor Q1 and the NMOS transistor Q4 operate in a direction of turning on, and the response speed of the PMOS transistor Q2 increases accordingly. The output delay time of the circuit of FIG. on the other hand,
While the input signal DI is at the low level, the bias voltage Vbi
Since as becomes high, the PMOS transistor Q1 and the NMOS transistor Q4 operate in the direction of turning off, and accordingly, the PMOS transistor Q1 and the NMOS transistor Q4 operate accordingly.
The response speed of the transistor Q2 decreases, and the output delay time tpdout of the circuit of FIG. 1 increases. However, the input signal D
I is important only when it becomes high level,
Even if the output delay time of the circuit of FIG. 1 is slightly longer at the low level, there is no practical problem.

As described above, in the circuit of FIG.
Since the voltage level of the bias voltage Vbias supplied to the level conversion unit 1 is switched according to the logic of I,
The level conversion operation can be stabilized by expanding the input margin of the input signal DI, the delay time of the level conversion output can be shortened, and the current consumption can be reduced.

In the circuit of FIG. 1, a PMOS transistor and an NMOS
Although a transistor is used, a circuit may be formed using a bipolar transistor.

In the circuit of FIG. 1, the resistor R12 is connected in parallel.
The example in which the PMOS transistor Q5 is connected to adjust the bias resistance has been described. Instead of the PMOS transistor Q5 and the resistor R12, a variable resistor whose resistance value can be adjusted in a programmable manner is provided, and the resistance value of this resistor is input to the input signal. Switching may be performed according to the logic of DI. In FIG. 1, three types of resistors are connected in series to divide the resistance, but the number of resistors connected in series is not limited as long as it is two or more.

In the above-described embodiment, the level conversion circuit used for driving the scanning lines of the liquid crystal panel 11 has been described. However, the level conversion circuit of the present invention is used for various purposes, and is used for level conversion. Also, the voltage after the level conversion is not limited to the voltage value described in the above embodiment. Further, the present invention can be applied to a case where data lines of the liquid crystal panel 11 are driven.

[0050]

As described in detail above, the present invention provides
In a so-called ratio-type level conversion circuit, a first transistor is turned on / off according to a logic of an input signal, and a voltage obtained by level-converting the input signal is output from a connection point of the first and second transistors. Since the gate voltage of the second transistor or the voltage of the base terminal is variably controlled according to the logic of the input signal, the margin of the voltage level of the input signal (input margin) can be increased, and the input signal can be increased. , The delay time from when the signal is input to when the level conversion output signal is output can be shortened, and the current consumption in the level conversion circuit can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an embodiment of a level conversion circuit.

FIG. 2 is an operation timing chart of the level conversion circuit of FIG. 1;

FIG. 3 is a diagram showing how a bias voltage Vbias changes according to an input voltage DI.

FIG. 4 is a block diagram of a liquid crystal display device.

FIG. 5 is a block diagram illustrating a detailed configuration of a scanning line driving circuit.

FIG. 6 is an operation timing chart of a scanning line driver circuit.

FIG. 7 is a circuit diagram showing a configuration of a conventional general level conversion circuit.

FIG. 8 is a sectional view of an inverter in the circuit of FIG. 7;

FIG. 9 is a conventional circuit diagram showing a detailed configuration of a level conversion circuit.

FIG. 10 is an operation timing chart of the level conversion circuit.

FIG. 11 is a diagram showing how the current consumption of the level conversion circuit shown in FIG. 9 changes according to a bias voltage Vbias.

FIG. 12 is a diagram showing how the input margin of the level conversion circuit shown in FIG. 9 changes.

FIG. 13 is a diagram showing how the output delay time of the level conversion circuit shown in FIG. 9 changes according to a bias voltage Vbias.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Level conversion part 2 Bias circuit 11 Liquid crystal panel 12 Scan line drive circuit 13 Data line drive circuit 31, 32 Level conversion circuit 33 Shift register

Claims (6)

[Claims] 1. A level conversion circuit for converting a voltage level of an input signal and outputting the voltage, wherein a first transistor which is turned on and outputs a first voltage when the input signal has a first logic, and an output terminal Is connected to the output terminal of the first transistor,
A second transistor that outputs a second voltage when the input signal has a second logic, and variably controls a voltage of a gate terminal or a base terminal of the second transistor in accordance with the logic of the input signal. And a bias circuit. 2. The method according to claim 1, wherein the bias circuit sets a voltage of a gate terminal or a base terminal of the second transistor in a direction in which the second transistor is turned off when the input signal has the first logic. 2. The level converter according to claim 1, wherein when the input signal has the second logic, a voltage of a gate terminal or a base terminal of the second transistor is set in a direction in which the second transistor is turned on. circuit. 3. A bias circuit comprising: a plurality of resistors connected in series between two different voltage terminals; a voltage dividing ratio adjusting circuit for adjusting a voltage dividing ratio of the plurality of resistors according to a logic of the input signal; 3. The level conversion circuit according to claim 1, wherein a voltage corresponding to a divided voltage between the plurality of resistors is applied to a gate terminal or a base terminal of the second transistor. 4. 4. The voltage dividing ratio adjusting circuit includes a switch element connected in parallel with any one of the plurality of resistors, and the bias circuit switches the switch element when the input signal has the first logic. Turning on the second transistor to turn off the second transistor; and when the input signal has the second logic, turning off the switch element and turning on the second transistor. The level conversion circuit according to claim 3, wherein 5. A level conversion circuit for converting a voltage level of an input signal and outputting the voltage, wherein a first voltage is applied to a source terminal, the input signal is applied to a gate terminal, and an output terminal is connected to a drain terminal. A first transistor of a first conductivity type, a second transistor of a second conductivity type having a drain terminal connected to the output terminal, and a source terminal to which a second voltage lower than the first voltage is applied. A third transistor of a first conductivity type in which the first voltage is applied to a source terminal and a gate terminal of the second transistor is connected to a drain terminal; and the third transistor is connected to a gate terminal and a drain terminal. A second conductive type fourth transistor having a gate terminal connected to the second transistor and a source terminal to which the second voltage is applied, and a serially connected series between two different voltage terminals First, second, and third resistors, and a fifth transistor of the first conductivity type, which is connected in parallel to both ends of the second resistor and that is turned on / off according to the logic of the input signal. A level conversion circuit for applying a voltage at a connection point between the second and third resistors to a gate terminal of the third transistor. 6. A liquid crystal panel section having a plurality of scanning lines and signal lines, a plurality of switching elements connected to these scanning lines and signal lines to drive liquid crystal of each pixel, and a clock signal having a predetermined period. A shift register that shifts according to a signal; and an output control circuit that switches a voltage level of the scanning line based on each output of the shift register. A liquid crystal display device that drives a liquid crystal by turning off the liquid crystal panel, wherein the voltage level of the pulse signal is converted in accordance with a power supply voltage supplied to the liquid crystal panel unit. A first level conversion unit configured to convert a voltage level of the clock signal according to a power supply voltage supplied to the liquid crystal panel unit. A second level conversion unit comprising the level conversion circuit according to any one of the above, wherein the shift register is configured to output the first level conversion signal based on a level-converted clock signal output from the second level conversion unit. A liquid crystal display device, which shifts a level-converted pulse signal output from a level converter.