JP2004258103A - El display driving device and printer head of optical printer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an EL display driving device that realizes constitution wherein an EL display is driven at a high speed by switching the reference voltage of a scanning-side driving circuit without using any photocoupler. <P>SOLUTION: The driving device which drives the EL display to illuminate is characterized in that when a plus scanning voltage is outputted from a scanning-side driver IC, an FET arranged at its output stage is turned on or off and when a negative scanning voltage is outputted, an FET constituting a reference voltage switching circuit is turned on or off to set the reference voltage of the scanning-side driver IC to a negative potential. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

そして、ＥＸＯＲゲート２４の出力レベルがハイになると、図示しないドライバを介してデータ電極９は０Ｖになり、出力レベルがローになるとデータ電極９には５０Ｖが印加される。
尚、走査側ドライバＩＣ５における走査電極８の選択も図５と略同様のロジックで行なわれる。
【００３５】
次に、本実施例の作用について図１，図６及び図７をも参照して説明する。図１は、各信号のタイミングチャートである。
（正フィールド）
コントローラ４は、基準電圧切替え回路７に出力する制御信号ＣＯＭＰ−Ｐをハイ，ＣＯＭＰ−Ｎをローにする（▲１▼）。すると、インバータゲート１８の出力端子はローレベルになり、コンデンサカップリングされているＦＥＴ１５のゲートは瞬間的に−５Ｖになるので、ＦＥＴ１５はオンする。一方、ＦＥＴ１６はオフとなる。
【００３６】
この場合、走査側ドライバＩＣ５の基準電圧ＶＳＳはＦＥＴ１５を介してＧＮＤに接続され、電源電圧ＶＤＤは２１６Ｖとなる。従って、走査側ドライバＩＣ５の基準電圧ＶＳＳはコントローラ４のＧＮＤに一致するので、コントローラ４は、走査側ドライバＩＣ５にデータ信号Ｄ，クロック信号ＣＬＫ，極性制御信号ＰＣをそのまま伝送可能となる。
【００３７】
そして、データ信号Ｄをハイにして（▲２▼）クロック信号ＣＬＫの立上がりでラッチさせることで走査電極８（１）を選択する（▲３▼）。この時点では、極性制御信号ＰＣはローであるから（▲４▼）走査側ドライバＩＣ５のＦＥＴ１５がオンになり、走査電極８（１）は基準電圧ＶＳＳ＝ＧＮＤレベルとなっている。尚、選択されないその他の走査電極８（２）〜８（Ｎ）は、ＦＥＴ１４，１５が何れもオフとなりハイインピーダンス状態となる。
【００３８】
この状態から、極性制御信号ＰＣがハイになると（▲５▼）、走査側ドライバＩＣ５のＦＥＴ１４がオン，ＦＥＴ１５がオフに切替わり、走査電極８（１）は高電圧ＶＤＤ＝２１６Ｖとなる。
【００３９】
一方、データ側ドライバＩＣ６は、前述した動作を、極性制御信号ＰＣがハイになる時点▲５▼の以前に完了しており、発光対象のデータ電極９を０Ｖにすると共に、それ以外のデータ電極９を５０Ｖにする。すると、発光対象のＥＬ素子１の両端には合成電圧２１６Ｖが印加されて発光し、それ以外のＥＬ素子１の両端には合成電圧（２１６−５０＝）１６６Ｖが印加される。
【００４０】
それから、コントローラ４は、極性制御信号ＰＣをローに戻す（▲６▼）。すると、時点▲４▼と同様に、ＦＥＴ１４がオフ，ＦＥＴ１５がオンに切替わり、走査電極８（１）は基準電圧ＶＳＳとなる。
【００４１】
（負フィールド）
この場合、後述するように、走査側ドライバＩＣ５の基準電圧ＶＳＳはコントローラ４のＧＮＤに一致しなくなる。そのため、コントローラ４は、走査側ドライバＩＣ５に対する制御信号を正フィールドの状態のまま保持しておき、基準電圧切替え回路７側の切り替え制御を行う。即ち、コントローラ４は、基準電圧切替え回路７に出力する制御信号ＣＯＭＰ−Ｐをロー，ＣＯＭＰ−Ｎをハイにする（▲７▼）。すると、ＦＥＴ１５はオフ、ＦＥＴ１６はオンとなる。
【００４２】
この場合、走査側ドライバＩＣ５の電源ＶＤＤはＦＥＴ１６を介してＧＮＤに接続されるため、基準電圧ＶＳＳは−２１６Ｖとなる。ここで、図２を参照する。コントローラ４と走査側ドライバＩＣ５との間にダイオード１０、反転バッファ１１及びプルアップ抵抗１２が存在しない場合を想定すると、基準電圧ＶＳＳが負電圧に大きく低下した場合、コントローラ４の出力端子からは過剰な電流が流出して走査側ドライバＩＣ５が破壊に至るおそれがある。
【００４３】
そのような事態を防止するために、ダイオード１０、反転バッファ１１及びプルアップ抵抗１２が配置されている。即ち、逆方向のダイオード１０は、出力端子からの電流流出を素子し、プルアップ抵抗１２は、反転バッファ１１の入力端子をハイレベルに設定する。従って、反転バッファ１１が出力する信号レベルはローに固定される。
【００４４】
再び、図１を参照する。時点▲７▼において基準電圧ＶＳＳが−２１６Ｖ、即ち負極性の走査電圧に設定されたことで、走査電極８（１）には−２１６Ｖが印加される。また、データ側ドライバＩＣ６より出力される信号レベルは、反転信号ＲＥＶがローになることで反転する。その結果、発光対象のデータ電極９には５０Ｖが印加され、それ以外のデータ電極９は０Ｖとなる。すると、発光対象のＥＬ素子１の両端には合成電圧（−２１６−５０＝）−２６６Ｖが印加されて発光し、それ以外のＥＬ素子１の両端には合成電圧−２１６Ｖが印加される。
【００４５】
最後に、時点▲１▼と同様に、コントローラ４は、制御信号ＣＯＭＰ−Ｐをハイ，ＣＯＭＰ−Ｎをローにする（▲８▼）。すると、走査側ドライバＩＣ５の基準電圧ＶＳＳはＧＮＤに接続され、電源電圧ＶＤＤは２１６Ｖとなる。この時、−２１６Ｖに充電されているＥＬ素子１は、走査側ドライバＩＣ５のＦＥＴ１５の寄生ダイオードを介してグランドより充電されて、０Ｖになる。以上で、負フィールドの動作が終了する。
【００４６】
コントローラ４は、１つの走査電極８（１）について、正，負フィールドを交互に繰り返し実行してＥＬ素子１を連続的に発光させる。そして、所定回数の発光が終了すると、クロック信号ＣＬＫがハイに変化し、その立ち上がりで走査側の制御は走査電極８（２）に移行する。尚、選択されないその他の走査電極８（１）、８（３）〜８（Ｎ）は何れもハイインピーダンス状態となる。そして、走査電極８（２）について上記と同様の制御を行い、最後の走査電極８（Ｎ）について制御を終了すると、再び走査電極８（１）から同様の処理を繰り返す。
【００４７】
尚、図６には、ＥＬ素子のＱＶ特性を示す。ＱＶ特性は、ＥＬ素子に印加する合成電圧Ｖと、ＥＬ素子に蓄積された電荷Ｑとの関係を示すものである。
まず、ＥＬ素子に対して電圧が全く印加されていない状態を原点▲１▼とする。この状態から発光電圧２１６Ｖを印加すると、蓄積電荷量Ｑは▲２▼を経て状態▲３▼に至る。状態▲１▼−▲２▼間は、ＥＬ素子の発光層に伝導電流は流れず発光しない。そして、ＥＬ素子は状態▲２▼でクランプし（ＥＬ素子が容量的な特性から抵抗体的な特性に変化する）、状態▲２▼−▲３▼間では、ＥＬ素子の発光層に伝導電流が流れて発光する。この場合の伝導電流の大きさは、クランプ後の電荷量（移動電荷量）で大凡決まる。
【００４８】
次に、状態▲３▼から電圧を０Ｖにすると状態▲４▼に遷移する。即ち、伝導電流が流れたことで分極電荷が発光層の両端に発生しており、ＥＬ素子は発光層が絶縁層に挟み込まれた二重絶縁膜構造のキャパシタンスをなしているから、発生した分極電荷は消滅せず、０Ｖに戻っても正電荷が残留している。それから、負側の発光電圧−２６６Ｖを印加すると、残留分極電荷の影響により状態▲５▼でクランプし、状態▲６▼に至る。状態▲４▼−▲５▼間では、ＥＬ素子の発光層に伝導電流が流れず発光しないが、状態▲５▼−▲６▼間では伝導電流が流れて発光する。
【００４９】
そして、状態▲６▼から電圧を０Ｖにすると状態▲７▼に遷移する。この場合、負側の発光電圧を正側よりも大きくしたので、状態▲４▼よりも多い負電荷が残留する。そして、状態▲７▼から再び正の発光電圧２１６Ｖを印加すると、残留分極電荷の影響により状態▲８▼でクランプし、状態▲２▼を経て状態▲３▼に至る。
【００５０】
以降は、上記の状態▲３▼より開始されるプロセスを繰り返す。このように、無機ＥＬ素子は、電圧が印加されると分極電荷が発生し、その影響によってＱＶ特性が平行四辺形を描くように変化する。尚、これらの図では、右半分側が正フィールドに対応し、左半分側が負フィールドに対応する。
【００５１】
即ち、本実施例では、正フィールド，負フィールドにおける発光電圧を非対称にしたことによって、移動電荷量を増加させることができ、ＥＬ素子をより高輝度で発光させている。例えば、±２１６Ｖのように発光電圧を対称にすると、移動電荷量は図６に示すようにΔｑにしかならない。それに対して、本実施例の移動電荷量はΔＱに大きく増加する。
【００５２】
また、斯様に印加電圧が正負で非対称になるとしても、ＥＬ素子の発光輝度は、実効的には±（選択電圧＋（データ電圧）／２）の交流電圧を印加した場合と同じになる（即ち、図６において太い破線で示す特性）。これは、一方の極性で電圧を印加してＥＬ素子を発光させると素子の内部で分極電荷が発生し、その状態から逆極性で電圧を印加してＥＬ素子を発光させる場合は、前記分極電荷と逆極性電界との差に応じて移動電荷が発生するためである。従って、見かけ上の印加電圧が正負で非対称であるとしても、分極電荷と逆極性電界との差に応じた移動電荷量は略対称に発生することになる。
【００５３】
故に、本実施例では、負フィールドにおいて発光対象外のＥＬ素子１に−２１６Ｖが印加され、最初の負フィールドだけは従来と同様に移動電荷量Δｑに応じた輝度で発光する。しかし、その後の負フィールドについてはその前の正フィールドにおける印加電圧が１６６Ｖとなるため、移動電荷量は略ゼロとなって発光しなくなるので、実質的（積分的）な発光輝度は略ゼロとなる。
【００５４】
ここで、走査電極８の配線抵抗ｒを適切に設定するための条件について、図７を参照して説明する。走査電圧（発光電圧）をＶ，走査側ドライバＩＣ５を構成するＦＥＴ１３又は１４の耐圧をＶ０，ＥＬ素子１の容量をＣ，ＥＬ素子１の放電時間をｔとした場合に、走査電極８の配線抵抗ｒを、
Ｖ・ｅｘｐ（−ｔ／（Ｃ・Ｒ））＋Ｖ≦Ｖ０ ・・・（１）
を満たす抵抗値Ｒの値に基づいて設定すると良い。
【００５５】
即ち、ＥＬ素子１は容量性負荷としての性質を有する。そして、電圧Ｖで充電され抵抗値Ｒの抵抗に接続されている容量Ｃを時間ｔだけ放電させた場合の電圧Ｖｄ（ｔ）は（１）式の左辺第１項で表され、その電圧Ｖｄ（ｔ）に電圧Ｖを加えたものがＦＥＴ１３，１４の耐圧Ｖ０以下であれば良い。
【００５６】
図７に示す等価回路で、より具体的に説明する。例えば、ＥＬ素子１を発光させた後、走査側ドライバＩＣ５のＦＥＴ１３，１４を何れもオフにすると、走査電極８の抵抗ｒ及びその他の回路抵抗ｒ’を介してＥＬ素子１が放電しようとする。そして、その放電に伴ってＦＥＴ１３又は１４に印加される電圧は、配線抵抗に応じた値となる。従って、Ｒ＝ｒ＋ｒ’とし、（１）式を解いて得られる抵抗値Ｒに基づいて許容される配線抵抗ｒを決定する。
【００５７】
具体数値例として、Ｖ＝２１６，Ｖ０＝２３０、Ｃ＝０．１５ｎ，ｔ＝０．３２μとして（１）式を解く。尚、放電時間ｔ＝０．３２μ（秒）は、充電電荷Ｑについての（２）式より算出する。但し、走査側ドライバＩＣの出力電流Ｉは１００ｍ（Ａ）とする。
Ｑ＝Ｉ×ｔ＝Ｃ・Ｖ ・・・（２）
この（２）式よりｔ＝０．３２μ（秒）が得られ、（１）式を計算すると、Ｒ≦８００（Ω）が得られる。そして、その他の回路抵抗ｒ’＝３９０Ωであれば、
ｒ≦８００−３９０＝４１０（Ω）
に設定すれば良い。
【００５８】
以上のように本実施例によれば、ＥＬディスプレイ２の駆動装置３において、走査側ドライバＩＣ５より正極性の走査電圧を出力させる場合は、出力段に配置されるＦＥＴ１３，１４のオンオフを切替え、負極性の走査電圧を出力させる場合は、基準電圧切替え回路７を構成するＦＥＴ１５，１６のオンオフを切替えて、走査側ドライバＩＣ５の基準電圧を負電位に設定した。
【００５９】
具体的には、コントローラ４は、正極性の選択電圧を出力する場合は、基準電圧切替え回路７のＦＥＴ１５のみをオンして基準電圧ＶＳＳの電位をグランド電位とし、走査側ドライバＩＣ５のＦＥＴ１３のみをオンにする。また、負極性の選択電圧を出力する場合は、走査側ドライバＩＣ５のＦＥＴ１４のみをオンして走査電極を基準電圧ＶＳＳの電位にしている状態から、基準電圧切替え回路７のＦＥＴ１６のみをオンにするように切替える。従って、従来構成のようにフォトカプラを使用してアイソレーションを図る必要がなくなり、ＥＬディスプレイ２を高速に且つ高輝度で発光させることが可能となる。
【００６０】
そして、コントローラ４と走査側ドライバＩＣ５の間に接続される信号線に、ダイオード１０、反転バッファ１１及びプルアップ抵抗１２を配置したので、走査側ドライバＩＣ５の基準電圧ＶＳＳが負電位となる場合でも、走査側ドライバＩＣ５の制御信号の状態を固定することができる。
【００６１】
また、データ側ドライバＩＣ６は、データ電圧を印加するためのロジックレベルをコントローラ４より与えられる反転信号ＲＥＶに応じて反転可能としたので、１選択期間にＥＬ素子１を複数回交流駆動するために、コントローラ４よりデータ側ドライバＩＣ６に対して反転データ全データ電極分送信する必要がなくなる。従って、制御をより簡単にすることができ、また、データの転送速度を低下させることも可能である。
【００６２】
そして、データ側ドライバＩＣ６は、走査電圧が正極性の場合は０Ｖを出力し、走査電圧が負極性の場合はデータ電圧５０Ｖを出力する。すると、ＥＬ素子１の両端には走査電圧に等しい合成電圧が印加される。一方、走査電圧が負極性の場合、ＥＬ素子１の両端には大きさが（走査電圧＋データ電圧）となる合成電圧が印加されるので、正フィールドと負フィールドとで印加する合成電圧の大きさが非対称となり印加電圧の差をより大きくすることができるので、ＥＬ素子１の発光輝度を一層向上させることができる。
【００６３】
更に、基準電圧切替え回路７を構成するＰチャネルＦＥＴ１５のゲートを、コントローラ４より出力される制御信号に対してコンデンサ１９でカップリングしたので、ソースがグランドに接続されているＰチャネルＦＥＴ１５のゲートを簡単な構成で負電位に設定してオンさせることができる。そして、ＦＥＴ１５を駆動するために別のスイッチング素子等を必要としないので、ＦＥＴ１５のスイッチングをより高速に行なうことができる。
【００６４】
また、走査電極の配線抵抗ｒを、（１）式を満たす抵抗値Ｒの値に基づいて設定するので、走査側ドライバＩＣ５の出力段を構成するＦＥＴ１３，１４が何れもＯＦＦとなった場合に、ＥＬ素子１の放電によって配線抵抗に発生する電圧も重畳されることでＦＥＴ１３又は１４が破壊に至ることを確実に防止できる。
【００６５】
（第２実施例）
図９及び図１０は本発明の第２実施例を示すものであり、第１実施例と同一部分には同一符号を付して説明を省略し、以下異なる部分についてのみ説明する。第２実施例では、図９に示すように、データ側ドライバＩＣ６に代わるデータ側ドライバＩＣ（データ側駆動回路）２５は、ＥＸＯＲゲート２４が削除されている。そして、データ側ドライバＩＣ２５のラッチ２３からの出力データは、図示しないドライバを介してデータ電極９に出力されるようになっている。
【００６６】
従って、コントローラ４は反転信号ＲＥＶを出力せず、それに代えて、データ信号ＤＡＴＡとストローブ信号ＳＴＢとを正，負の各フィールドが切替わる毎に出力するようになっている（図１０参照）。
以上のように構成される第２実施例による場合も、第１実施例と略同様の効果が得られる。
【００６７】
（第３実施例）
図１１乃至図１４は、本発明を光プリンタのプリンタヘッドに適用した場合の第３実施例であり、第１実施例と同一部分には同一符号を付して説明を省略し、以下異なる部分についてのみ説明する。図１１は、光プリンタの要部構造を概略的に示すものである。
【００６８】
感光ドラム３１は、図１１中時計回り方向に回転し、先ず、帯電部３２によって表面に負電荷の帯電が行われる。続いて、図１２に示すＥＬ素子アレイ３３及びセルフォックレンズ３４により、印刷画像データに応じた露光が行われる。ＥＬ素子アレイ３３とセルフォックレンズ３４とを組み合わせたものがプリンタヘッド６０となる。感光ドラム３１の露光が行われた部分は電位が上昇して静電潜像が形成される。次に、現像部３５において帯電している部分にトナーが付着されてトナー像が形成される。
【００６９】
感光ドラム３１の表面に形成されたトナー像は、転写部３６において用紙３７に転写され、転写された像は定着部３８において用紙３７に定着される。その後、感光ドラム３１は除電部３９において除電され、更に、クリーニング部４０においてトナーのクリーニングが行われる。
【００７０】
図１２は、プリンタヘッド６０及び感光ドラム３１を中心として示す斜視図である。ＥＬ素子アレイ３３はライン状をなす光源として構成されており、セルフォックレンズ３４はマイクロレンズアレイとして構成されている。ＥＬ素子アレイ３３が発した光は、セルフォックレンズ３４により集光されて感光ドラム３１の表面に投光されるようになっている。
【００７１】
図１３は、第１実施例におけるＥＬ素子１を用いて構成したＥＬ素子アレイ３３を示すものである。ガラス基板５１は、ＥＬ素子アレイ３３の基板を兼用するように構成されている。また、第１電極５２（走査電極は、光プリンタの光源としてはＥＬ素子１をライン状に多数配列すれば良いので、第１電極５２は１本のみ形成されている。
【００７２】
ガラス基板５１には、その他、制御回路４２、走査側ドライバＩＣ（走査側駆動回路）４３、データ側ドライバＩＣ（データ側駆動回路）４４、光プリンタ本体側の制御回路と電気的に接続を行うための外部接続端子４５などが搭載されている。そして、制御回路４２により、第１実施例のコントローラ４と同様の駆動方式によってＥＬ素子１を発光させる。
【００７３】
また、図１４は、ＥＬ素子に印加する電圧のレベルとパルス数とを変化させた場合における、ＥＬ素子の光パワーの相対強度を示すものである。即ち、印加電圧パルス数が多くなるほど、光パワーの相対強度は上昇する傾向を示している。
【００７４】
ここで、ドライバＩＣ４３，４４を共に高耐圧化するにはコストがかかるため、構造上、高耐圧化が比較的容易な走査側ドライバＩＣ４３の耐圧は約２３０Ｖ，データ側ドライバＩＣ４４の耐圧は約５５Ｖ程度としている。そして、従来は、例えば正の選択電圧を２１６Ｖ，負の選択電圧を−１６６Ｖとし、データ電圧を０Ｖ、５５Ｖとすることで、第１実施例で述べたように、ＥＬ素子を発光させる合成電圧が±２１６Ｖで対称となるように設定していた。
【００７５】
これに対して、本実施例では、走査側の選択電圧を±２１６Ｖとして非対称に発光駆動することで、ドライバＩＣ４３，４４の耐圧は従来通りとしたままで、ＥＬ素子の発光輝度を向上させることが可能となっている。
【００７６】
尚、図１４に示すように、ＥＬ素子が実質的に発光を開始する電圧は、上記選択電圧よりもかなり低いレベルにある。しかし、プリンタヘッドとして使用する場合には、感光ドラム３１に潜像を形成する印字ＯＮ、潜像を形成しない印字ＯＦＦの状態が明確に区別されるような発光パワーによるコントラスト（例えば輝度比が１０：１）を得ることができれば良い。従って、その条件を満たせば、印字ＯＦＦの状態においてＥＬ素子が発光しているとしても何等問題はない。
【００７７】
以上のように第３実施例によれば、第１実施例の駆動装置３と同様の駆動装置を備え、その駆動装置で駆動されるＥＬ素子１を光源とするプリンタヘッド６０を構成したので、高速印字が可能な光プリンタを構成することができる。
【００７８】
本発明は上記し且つ図面に記載した実施例にのみ限定されるものではなく、以下のような変形または拡張が可能である。
選択電圧やデータ電圧は、個別の設計や許容されるドライバＩＣの耐圧などに応じて適宜設定すれば良い。
必ずしも非対称駆動を行なうものに限らず、負フィールドにおいて発光対象のＥＬ素子２のデータ電圧を０Ｖにすることで±２１６Ｖで対称駆動するように構成しても良い。
ＰチャネルＦＥＴ１５のゲートを駆動する構成は、コンデンサカップリングに限ることなく、駆動用のスイッチング素子を別途配置して駆動するように構成しても良い。
第３実施例において、走査電極の構造を特願２００２−２５９９４８で提案されているようにＥＬ素子の配列方向に沿って分割して配置しても良い。
【図面の簡単な説明】
【図１】本発明をドットマトリクス型のＥＬディスプレイに適用した場合の第１実施例であり、各制御信号のタイミングチャート
【図２】ＥＬ素子を用いて構成されるドットマトリクス型のＥＬディスプレイと、その駆動装置とを示す図
【図３】走査側ドライバＩＣの出力段部分の電気的構成を１つの走査電極について示す図
【図４】基準電圧切替え回路の電気的構成を示す図
【図５】データ側ドライバＩＣの電気的構成を示す図
【図６】ＥＬ素子のＱＶ特性を示す図
【図７】配線抵抗ｒを求める計算を説明するための等価回路図
【図８】無機ＥＬ素子の構造を示す（ａ）平面図，（ｂ）は（ａ）のＡ−Ａ断面を模式的に示す図
【図９】本発明の第２実施例を示す図５相当図
【図１０】図１相当図
【図１１】本発明を光プリンタのプリンタヘッドに適用した場合の第３実施例であり、光プリンタの要部構造を概略的に示す図
【図１２】感光ドラム及びプリンタヘッドを示す斜視図
【図１３】プリンタヘッドを構成するＥＬ素子アレイを示す図
【図１４】ＥＬ素子に印加する電圧レベルとパルス数とを変化させた場合の、ＥＬ素子の光パワーの相対強度を示す図
【符号の説明】
１はＥＬ素子、２はＥＬディスプレイ、３は駆動装置、４はコントローラ（制御回路）４、５は走査側ドライバＩＣ（走査側駆動回路）、６はデータ側ドライバＩＣ（データ側駆動回路）、７は基準電圧切替え回路、８は走査電極、９はデータ電極、１０はダイオード、１１は反転バッファ（バッファ）、１２はプルアップ抵抗、１３はＰチャネルＭＯＳＦＥＴ、１４はＮチャネルＭＯＳＦＥＴ、１５はＰチャネルＭＯＳＦＥＴ、１６はＮチャネルＭＯＳＦＥＴ、２５はデータ側ドライバＩＣ（データ側駆動回路）、３３はＥＬ素子アレイ、４３は走査側ドライバＩＣ（走査側駆動回路）、４４はデータ側ドライバＩＣ（データ側駆動回路）、６０はプリンタヘッドを示す。[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a driving device that drives an EL display having inorganic EL elements as pixels by an offset driving method, and a printer head of an optical printer including the driving device and using the EL elements as a light source.
[0002]
[Prior art]
A dot matrix type EL display using an inorganic EL element is usually driven using a scanning side (row) driver IC and a data side (column) driver IC. For example, Patent Document 1 discloses that in order to increase the brightness of a thin film EL element having an MIS structure in which an insulating film is disposed only on one side, in a line-sequential operation method, positive and negative voltages are continuously applied during one selection period. A driving method of alternately applying the voltage is disclosed.
[0003]
At present, the mainstream of thin-film EL devices is a double insulating film structure in which insulating films are arranged on both sides of a light-emitting layer in order to increase the brightness and reliability of the device itself. However, there is a problem in applying the technique disclosed in Patent Document 1 to a thin film EL device having a double insulating film structure. That is, it is necessary to apply an AC voltage of about ± 220 V to cause the thin-film EL element to emit light. However, since the withstand voltage of the scanning-side driver IC is about 230 V, it is necessary to relax the voltage level by applying, for example, the technique disclosed in Patent Document 2.
[0004]
In Patent Document 2, when a positive voltage and a negative voltage are switched and output alternately, the reference voltage (VSS) of the scanning driver IC is switched by a reference voltage switching circuit. When the EL element emits light, the scanning driver IC outputs + 220V and -170V, and the data driver IC outputs 0V and 50V. With this configuration, the withstand voltage of the scanning driver IC is reduced to 220-50 = 170 (V).
[0005]
In the configuration of Patent Document 2, a signal output from a controller (control circuit) that controls the scanning-side and data-side driver ICs is a signal that always uses 0 V as a reference voltage, and the reference voltage switching circuit sets the reference voltage. It does not match the reference voltage (VSS) of the switching driver IC to be switched. Therefore, by isolating (insulating) the controller and the driver IC with a photocoupler, the logic of the control signal is correctly transmitted even when the reference voltage is different.
[0006]
[Patent Document 1]
JP-A-62-156696
[0007]
[Patent Document 2]
JP-A-9-54566
[0008]
[Problems to be solved by the invention]
However, the switching time of the photocoupler is relatively slow, which is about 0.7 μsec even in the high-speed type, so that high-speed switching cannot be performed. In particular, in order to drive the inorganic EL element at high speed to emit light and to obtain high luminance, it is necessary to cause the EL element having a short emission fall time to emit light a plurality of times during one selection period on the scanning side (see, for example, Japanese Patent Application Laid-Open No. H10-163873). 2002-72274). In order to realize such a driving method, isolation cannot be achieved by using a photocoupler.
[0009]
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an EL display driving method capable of realizing a high-speed driving of an EL display by switching a reference voltage of a scanning side driving circuit without using a photocoupler. An object of the present invention is to provide a printer head of an optical printer including an apparatus and a driving device thereof and using an EL element as a light source.
[0010]
[Means for Solving the Problems]
According to the EL display driving device of the first aspect, the control circuit switches on / off of the MOSFET arranged in the output stage when the scanning driving circuit outputs the positive scanning voltage. That is, by turning on the FET on the high voltage power supply side and turning off the FET on the reference voltage side, a positive voltage is output to the scan electrode. Thereafter, if the above-mentioned on / off pattern is reversed, the scan electrode is only at the reference voltage level and no negative voltage is output. Then, from this state, the on / off state of the MOSFET constituting the reference voltage switching circuit is switched so that the reference voltage of the scanning-side drive circuit becomes negative potential. Then, a scan voltage of negative polarity is output from the scan-side drive circuit to the scan electrode.
[0011]
That is, when a negative scan voltage is output, the switching of the reference voltage switching circuit is controlled and output without controlling the switching of the scanning drive circuit.
There is no need to use a photocoupler to achieve isolation as in the configuration. Therefore, it is possible to cause the EL display to emit light at high speed and with high luminance.
[0012]
According to the EL display driving device of the present invention, when outputting the scanning voltage of the positive polarity, the control circuit turns on only the P-channel MOSFET of the reference voltage switching circuit and sets the reference voltage potential to the ground potential. . Then, only the P-channel MOSFET of the scanning drive circuit is turned on. Then, a scanning voltage is applied to the scanning electrode from the positive terminal of the driving power supply.
[0013]
On the other hand, when a negative scan voltage is output, only the N-channel MOSFET of the reference voltage switching circuit is turned on from the state where only the N-channel MOSFET of the scan side drive circuit is turned on and the scan electrode is set to the reference voltage potential. Switch to Then, since the positive terminal of the driving power supply becomes the ground potential and the potential of the reference voltage becomes the negative scanning voltage, a negative scanning voltage is applied to the scanning electrode. Therefore, the operation and effect of the first aspect can be obtained with a simple configuration.
[0014]
According to the EL display driving device of the third aspect, when the reference voltage of the scanning side driving circuit has a negative potential, the control circuit does not need to output a control signal to the scanning side driving circuit, but the reference potential has decreased. This causes an excessive current to flow from the output terminal of the control circuit. Therefore, the current is blocked by the diode connected in the reverse direction. Then, since the input terminal side of the buffer is in a high impedance state as it is, one or two pull-up resistors and inverting buffers are arranged as necessary, so that the input terminal level of the buffer can be set to the required voltage level (high level). Or low level). Therefore, it is possible to fix the state of the control signal of the scanning drive circuit during the period when the reference voltage is at the negative potential.
[0015]
According to the EL display driving device of the fourth aspect, the data side driving circuit is configured so that the logic level for applying the data voltage can be inverted according to an inversion signal input from the outside. Therefore, in order to alternately drive the EL element a plurality of times during one selection period, the control circuit needs to transmit inversion data to the data side driving circuit for all data electrodes every time the output level of the scanning driving circuit is inverted. And only the inversion signal for giving the data inversion timing need be transmitted. Therefore, control can be simplified, and since all data has to be transferred during one selection period, the data transfer speed can be reduced.
[0016]
According to the EL display driving device of the fifth aspect, the data side driving circuit outputs 0 V to the EL element to be emitted when the scanning voltage is positive, and outputs the data voltage when the scanning voltage is negative. Is output. In addition, a data voltage is output to the EL element that is not a light emitting target when the scanning voltage is positive, and 0 V is output when the scanning voltage is negative.
[0017]
Then, when the scanning voltage has a positive polarity, a combined voltage equal to the scanning voltage is applied to both ends of the EL element to be illuminated. On the other hand, when the scanning voltage is negative, a combined voltage having a magnitude of (scanning voltage + data voltage) is applied to both ends of the EL element to be illuminated. Therefore, the magnitude of the combined voltage applied between the positive field and the negative field can be made asymmetrical to increase the difference between the applied voltages, so that the light emission luminance of the EL element can be further improved.
[0018]
According to the EL display driving device of the sixth aspect, the gate of the P-channel MOSFET constituting the reference voltage switching circuit is capacitor-coupled to the control signal output from the control circuit. Therefore, the gate of the P-channel MOSFET whose source is connected to the ground can be set to a negative potential and turned on with a simple configuration. Since another switching element or the like having a delay time is not required to drive the FET, the switching of the FET can be performed at a higher speed.
[0019]
According to the EL display driving device of the seventh aspect, the wiring resistance r of the scanning electrode is set to:
V · exp (−t / (C · R)) + V ≦ V0
Is set based on the value of the resistance value R satisfying the following.
[0020]
That is, the EL element has a property as a capacitive load. The voltage Vd (t) when the capacitor C charged with the voltage V and connected to the resistor having the resistance value R is discharged for the time t is expressed by the first term on the left side of the above equation, and the voltage Vd (t) ) May be any value as long as the sum of the voltage V and the withstand voltage V0 of the FET or less. By solving the above equation, the resistance value R can be obtained. If the allowable wiring resistance r is determined based on the resistance value R and the circuit resistance, any of the FETs constituting the output stage of the scanning drive circuit can be determined. When the switch is also turned off, even if a voltage generated in the wiring resistance due to the discharge of the EL element is superimposed, it is possible to reliably prevent the FET from exceeding the breakdown voltage and being destroyed.
[0021]
According to the printer head of the optical printer according to the present invention, since the EL element driven by the driving device according to any one of claims 1 to 7 is used as a light source, an optical printer capable of high-speed printing with high luminance is provided. Can be configured.
[0022]
BEST MODE FOR CARRYING OUT THE INVENTION
(First embodiment)
Hereinafter, a first embodiment in which the present invention is applied to a dot matrix type EL display will be described with reference to FIGS. First, the structure of the inorganic EL element 1 will be described with reference to FIG. (A) is a plan view of the EL element 1, and (b) is a view schematically showing the AA cross section of (a). The EL element 1 includes a first electrode 52 (scan electrode described later), a first insulating layer 53, a light emitting layer 54, a second insulating layer 55, and a second electrode 56 (same data electrode) on a glass substrate 51 which is an insulating substrate. Are sequentially laminated, and among the first electrode 52, the first insulating layer 53, the second insulating layer 55, and the second electrode 56, at least a light extraction side (display side) is made of a material having a light transmitting property. It is configured.
[0023]
The EL element 1 indicates a light emitting portion between one second electrode 56 and the first electrode 52 in the above configuration. Actually, there are more EL elements 1 than those shown in FIG.
[0024]
For example, the first electrode 52 is made of an ITO (Indium Tin Oxide) film, and the first insulating layer 53 is made of Al. ₂ O ₃ Layer and titanium oxide TiO ₂ Al with alternating layers ₂ O ₃ / TiO ₂ The laminated structure film (hereinafter, referred to as an ATO film), the light emitting layer 54 is an SrS: Ce film, the second insulating layer 55 is an ATO film similar to the first insulating layer 53, and the second electrode 56 is an Al film (note that For details of the manufacturing process and the like, see JP-A-2002-72274).
[0025]
FIG. 2 shows a dot matrix type EL display 2 constituted by using the EL elements 1 and a driving device 3 thereof. The drive device 3 includes a controller (control circuit) 4, a scanning driver IC (scan driver) 5, a data driver IC (data driver) 6, and a reference voltage switching circuit 7.
[0026]
The scanning driver IC 5 outputs a scanning voltage to the scanning electrodes 8 of the EL display 2, and the data driver IC 6 outputs a data voltage to the data electrodes 9. The data side driver IC 6 is supplied with a driving power supply of 50 V from a power supply circuit (not shown) for outputting a data voltage.
[0027]
The controller 4 outputs a control signal to the driver ICs 5 and 6 to display an image on the EL display 2 and also controls the reference voltage switching circuit 7. The reference voltage switching circuit 7 is configured to switch between the reference voltage VSS and the drive voltage VDD of the scanning driver IC 5.
[0028]
A diode 10 and an inverting buffer (inverter) 11 connected in the reverse direction are interposed in a signal line connecting the controller 4 and the scanning driver IC 5, and the input terminal of the inverting buffer 11 is Is pulled up to 5 V (VCC) by a pull-up resistor 12. For signals that do not need to be inverted by the inversion buffer 11, a simple buffer is connected or two inversion buffers 11 are connected in series.
[0029]
FIG. 3 shows the electrical configuration of the output stage portion of the scanning driver IC 5 for one scanning electrode 8. The output stage of the scanning-side driver IC 5 includes a P-channel MOSFET 13 and an N-channel MOSFET 14 whose sources are connected to VDD and VSS, respectively. The drains of both are commonly connected to the scanning electrode 8. The PC signals output from the controller 4 are applied to the gates of the FETs 13 and 14 via an electrode selection logic (not shown).
[0030]
FIG. 4 shows an electrical configuration of the reference voltage switching circuit 7. The reference voltage switching circuit 7 includes a P-channel MOSFET 15 and an N-channel MOSFET 16 whose sources are respectively connected to GND (circuit ground of the controller 4). The drain of the FET 15 is connected to the negative electrode of the 216 V power supply 17, and the drain of the FET 16 is connected to the positive electrode of the drive power supply 17. The positive electrode of the driving power supply 17 is connected to the voltage VDD of the scanning driver IC5, and the negative electrode is connected to the reference voltage VSS. The voltage of the driving power supply 17 is 216 V corresponding to the scanning voltage (selection voltage).
[0031]
The control signal COMP-P output from the controller 4 is supplied to the gate of the FET 15 via the inverter gate 18 and the capacitor 19, and the control signal COMP-N output from the controller 4 is directly supplied to the gate of the FET 16. I have. A resistor 20 and a diode 21 are connected in parallel between the gate and the source of the FET 15.
[0032]
FIG. 5 shows an electrical configuration of the data side driver IC 6. The data-side driver IC 6 includes a shift register 22, a latch 23, and an EXOR gate 24. The shift register 22 is supplied with the data signal DATA and the clock signal CL from the controller 4, and the shift register 22 performs serial / parallel conversion of the data signal DATA. The data signal DATA is at a low level for the data electrode 9 of the EL element 1 that emits light in the case of a positive field, and at a high level for the data electrode 9 of the EL element 1 that does not emit light. Then, when the serial / para conversion is completed, the latch 23 latches the data at the output timing of the strobe signal STB.
[0033]
The latch output of the latch 23 is connected to one terminal of the EXOR gate 24, and the other terminal is supplied with the inverted signal REV output from the controller 4. As will be described later, the driving device 3 is configured to cause the EL element 1 connected to the scanning electrode 8 to emit light a plurality of times during a period in which one scanning electrode 8 is selected once. For this purpose, the data signal DATA given from the controller 4 to the data driver IC 6 ends the transfer before the first light emission timing, and when the field is inverted thereafter, the data signal DATA according to the logical level of the inverted signal REV. Invert the level of
[0034]
That is, the level of the inverted signal REV changes to high in the positive field and to low in the negative field, and the output level of the EXOR gate 24 changes as follows, for example.

When the output level of the EXOR gate 24 becomes high, the data electrode 9 becomes 0 V via a driver (not shown), and when the output level becomes low, 50 V is applied to the data electrode 9.
The selection of the scanning electrode 8 in the scanning driver IC 5 is performed in substantially the same logic as in FIG.
[0035]
Next, the operation of the present embodiment will be described with reference to FIGS. FIG. 1 is a timing chart of each signal.
(Positive field)
The controller 4 sets the control signal COMP-P output to the reference voltage switching circuit 7 to high and COMP-N to low ((1)). Then, the output terminal of the inverter gate 18 becomes low level, and the gate of the capacitor-coupled FET 15 instantaneously becomes -5V, so that the FET 15 is turned on. On the other hand, the FET 16 is turned off.
[0036]
In this case, the reference voltage VSS of the scanning driver IC5 is connected to GND via the FET 15, and the power supply voltage VDD becomes 216V. Therefore, since the reference voltage VSS of the scanning driver IC5 matches the GND of the controller 4, the controller 4 can directly transmit the data signal D, the clock signal CLK, and the polarity control signal PC to the scanning driver IC5.
[0037]
Then, the scan electrode 8 (1) is selected by setting the data signal D high ((2)) and latching it at the rising edge of the clock signal CLK ((3)). At this time, since the polarity control signal PC is low (4), the FET 15 of the scanning driver IC 5 is turned on, and the scanning electrode 8 (1) is at the reference voltage VSS = GND level. The other scanning electrodes 8 (2) to 8 (N) that are not selected have both the FETs 14 and 15 turned off and enter a high impedance state.
[0038]
From this state, when the polarity control signal PC becomes high (5), the FET 14 of the scanning driver IC 5 is turned on and the FET 15 is turned off, and the high voltage VDD = 216 V is applied to the scanning electrode 8 (1).
[0039]
On the other hand, the data side driver IC 6 completes the above-mentioned operation before the point (5) at which the polarity control signal PC becomes high. 9 to 50V. Then, a combined voltage of 216 V is applied to both ends of the EL element 1 to be emitted, and light is emitted. A combined voltage (216-50 =) 166 V is applied to both ends of the other EL elements 1.
[0040]
Then, the controller 4 returns the polarity control signal PC to low ([6]). Then, similarly to the time point (4), the FET 14 is turned off and the FET 15 is turned on, and the scanning electrode 8 (1) becomes the reference voltage VSS.
[0041]
(Negative field)
In this case, as described later, the reference voltage VSS of the scanning driver IC5 does not match the GND of the controller 4. Therefore, the controller 4 keeps the control signal for the scanning driver IC 5 in the state of the positive field, and performs switching control on the reference voltage switching circuit 7 side. That is, the controller 4 sets the control signal COMP-P output to the reference voltage switching circuit 7 to low and COMP-N to high ([7]). Then, the FET 15 is turned off and the FET 16 is turned on.
[0042]
In this case, since the power supply VDD of the scanning driver IC5 is connected to GND via the FET 16, the reference voltage VSS is -216V. Here, reference is made to FIG. Assuming that the diode 10, the inverting buffer 11, and the pull-up resistor 12 do not exist between the controller 4 and the scanning driver IC 5, if the reference voltage VSS drops to a negative voltage, the output terminal of the controller 4 There is a possibility that a large current flows out and the scanning driver IC 5 is destroyed.
[0043]
In order to prevent such a situation, a diode 10, an inverting buffer 11, and a pull-up resistor 12 are provided. That is, the diode 10 in the reverse direction acts as an element for current flowing out of the output terminal, and the pull-up resistor 12 sets the input terminal of the inversion buffer 11 to a high level. Therefore, the signal level output from the inversion buffer 11 is fixed to low.
[0044]
FIG. 1 is referred to again. At the time point (7), the reference voltage VSS is set to −216 V, that is, the scanning voltage of the negative polarity, so that −216 V is applied to the scanning electrode 8 (1). The signal level output from the data driver IC 6 is inverted when the inverted signal REV becomes low. As a result, 50 V is applied to the data electrode 9 to be illuminated, and 0 V is applied to the other data electrodes 9. Then, a combined voltage (−216−50 =) − 266 V is applied to both ends of the EL element 1 to be emitted, and light is emitted, and a combined voltage of −216 V is applied to both ends of the other EL elements 1.
[0045]
Finally, similarly to the time point (1), the controller 4 sets the control signal COMP-P to high and COMP-N to low (8). Then, the reference voltage VSS of the scanning driver IC5 is connected to GND, and the power supply voltage VDD becomes 216V. At this time, the EL element 1 charged to −216 V is charged from the ground via the parasitic diode of the FET 15 of the scanning driver IC 5 to become 0 V. Thus, the operation of the negative field ends.
[0046]
The controller 4 alternately repeats the positive and negative fields for one scanning electrode 8 (1) to continuously emit light from the EL element 1. Then, when the light emission of the predetermined number of times is completed, the clock signal CLK changes to high, and the control on the scanning side shifts to the scanning electrode 8 (2) at the rise. The other scanning electrodes 8 (1) and 8 (3) to 8 (N) which are not selected are all in a high impedance state. Then, the same control as described above is performed for the scanning electrode 8 (2), and when the control for the last scanning electrode 8 (N) is completed, the same processing is repeated from the scanning electrode 8 (1) again.
[0047]
FIG. 6 shows the QV characteristics of the EL element. The QV characteristic indicates the relationship between the combined voltage V applied to the EL element and the charge Q stored in the EL element.
First, a state where no voltage is applied to the EL element is defined as an origin {circle around (1)}. When a light emission voltage of 216 V is applied from this state, the accumulated charge amount Q reaches state (3) via (2). During states (1) and (2), no conduction current flows through the light emitting layer of the EL element, and no light is emitted. The EL element is clamped in the state (2) (the EL element changes from a capacitive characteristic to a resistive characteristic), and between the states (2) and (3), the conduction current is applied to the light emitting layer of the EL element. Flows to emit light. In this case, the magnitude of the conduction current is roughly determined by the amount of charge (moving charge) after clamping.
[0048]
Next, when the voltage is set to 0 V from the state (3), the state transits to the state (4). That is, polarization charges are generated at both ends of the light emitting layer due to the conduction current, and the EL element has a double insulating film structure in which the light emitting layer is sandwiched between the insulating layers. The charge does not disappear, and a positive charge remains even when the voltage returns to 0V. Then, when a negative emission voltage of -266 V is applied, the state is clamped in the state (5) due to the influence of the residual polarization charge, and the state reaches the state (6). Between states (4) and (5), no conduction current flows through the light emitting layer of the EL element and no light is emitted. However, between states (5) and (6), conduction current flows to emit light.
[0049]
Then, when the voltage is changed to 0 V from the state (6), the state transits to the state (7). In this case, since the light emission voltage on the negative side is set higher than that on the positive side, more negative charges remain than in the state (4). Then, when a positive light emitting voltage of 216 V is applied again from the state (7), the state is clamped in the state (8) due to the influence of the residual polarization charge, and the state reaches the state (3) through the state (2).
[0050]
Thereafter, the process started from the above state (3) is repeated. As described above, when a voltage is applied to the inorganic EL element, a polarization charge is generated, and the QV characteristic changes so as to draw a parallelogram due to the influence of the polarization charge. In these figures, the right half corresponds to the positive field, and the left half corresponds to the negative field.
[0051]
That is, in the present embodiment, the amount of mobile charge can be increased by making the emission voltages in the positive field and the negative field asymmetric, and the EL element emits light with higher luminance. For example, when the emission voltage is symmetrical, such as ± 216 V, the amount of mobile charge is only Δq as shown in FIG. On the other hand, the amount of mobile charges in the present embodiment greatly increases to ΔQ.
[0052]
Even if the applied voltage becomes positive and negative and thus asymmetric, the emission luminance of the EL element is effectively the same as when an AC voltage of ± (selection voltage + (data voltage) / 2) is applied. (That is, the characteristic shown by the thick broken line in FIG. 6). This is because when a voltage is applied in one polarity to cause the EL element to emit light, a polarization charge is generated inside the element, and when a voltage is applied in the opposite polarity to cause the EL element to emit light, the polarization charge is generated. This is because mobile charges are generated according to the difference between the electric field and the opposite polarity electric field. Therefore, even if the apparent applied voltage is positive and negative and asymmetric, the amount of mobile charge corresponding to the difference between the polarization charge and the opposite electric field is generated substantially symmetrically.
[0053]
Therefore, in the present embodiment, -216 V is applied to the EL element 1 which is not a light emission target in the negative field, and only the first negative field emits light with a luminance corresponding to the moving charge amount Δq as in the related art. However, in the subsequent negative field, the applied voltage in the previous positive field is 166 V, so that the amount of mobile charges becomes substantially zero and no light is emitted, so that the substantial (integral) light emission luminance is substantially zero. .
[0054]
Here, conditions for appropriately setting the wiring resistance r of the scanning electrode 8 will be described with reference to FIG. When the scanning voltage (emission voltage) is V, the withstand voltage of the FET 13 or 14 constituting the scanning driver IC 5 is V0, the capacitance of the EL element 1 is C, and the discharge time of the EL element 1 is t, the wiring of the scanning electrode 8 is set. Resistance r
V · exp (−t / (C · R)) + V ≦ V0 (1)
It may be set based on the value of the resistance value R satisfying the following.
[0055]
That is, the EL element 1 has a property as a capacitive load. The voltage Vd (t) when the capacitor C charged with the voltage V and connected to the resistor having the resistance value R is discharged for the time t is expressed by the first term on the left side of the equation (1). What is necessary is that the value obtained by adding the voltage V to (t) is equal to or less than the withstand voltage V0 of the FETs 13 and 14.
[0056]
This will be described more specifically with reference to an equivalent circuit shown in FIG. For example, if both the FETs 13 and 14 of the scanning driver IC 5 are turned off after the EL element 1 emits light, the EL element 1 tries to discharge via the resistance r of the scanning electrode 8 and other circuit resistances r ′. . Then, the voltage applied to the FET 13 or 14 with the discharge has a value corresponding to the wiring resistance. Therefore, R = r + r ′, and the allowable wiring resistance r is determined based on the resistance value R obtained by solving the equation (1).
[0057]
As a specific numerical example, equation (1) is solved with V = 216, V0 = 230, C = 0.15n, and t = 0.32μ. Note that the discharge time t = 0.32 μ (sec) is calculated from the equation (2) for the charge Q. However, the output current I of the scanning driver IC is 100 m (A).
Q = I × t = C · V (2)
From equation (2), t = 0.32 μ (sec) is obtained. When equation (1) is calculated, R ≦ 800 (Ω) is obtained. And if the other circuit resistance r '= 390Ω,
r ≦ 800−390 = 410 (Ω)
Should be set to.
[0058]
As described above, according to the present embodiment, when the driving device 3 of the EL display 2 outputs the scanning voltage of the positive polarity from the scanning driver IC 5, the on / off of the FETs 13 and 14 arranged in the output stage is switched. To output a negative scanning voltage, the FETs 15 and 16 constituting the reference voltage switching circuit 7 were turned on and off, and the reference voltage of the scanning driver IC 5 was set to a negative potential.
[0059]
Specifically, when outputting the positive polarity selection voltage, the controller 4 turns on only the FET 15 of the reference voltage switching circuit 7, sets the potential of the reference voltage VSS to the ground potential, and sets only the FET 13 of the scanning driver IC 5 to the ground. turn on. When outputting the negative selection voltage, only the FET 14 of the reference voltage switching circuit 7 is turned on from the state where only the FET 14 of the scanning driver IC 5 is turned on and the scanning electrode is set to the potential of the reference voltage VSS. Switch. Therefore, it is not necessary to achieve isolation using a photocoupler as in the conventional configuration, and the EL display 2 can emit light at high speed and with high luminance.
[0060]
Since the diode 10, the inversion buffer 11, and the pull-up resistor 12 are arranged on the signal line connected between the controller 4 and the scanning driver IC 5, even when the reference voltage VSS of the scanning driver IC 5 becomes negative potential. The state of the control signal of the scanning driver IC 5 can be fixed.
[0061]
Further, since the data side driver IC 6 is capable of inverting the logic level for applying the data voltage in accordance with the inversion signal REV given from the controller 4, it is necessary to alternately drive the EL element 1 a plurality of times during one selection period. In addition, it is not necessary to transmit the inverted data for all the data electrodes from the controller 4 to the data driver IC 6. Therefore, the control can be simplified and the data transfer speed can be reduced.
[0062]
Then, the data side driver IC 6 outputs 0 V when the scanning voltage has a positive polarity, and outputs a data voltage 50 V when the scanning voltage has a negative polarity. Then, a combined voltage equal to the scanning voltage is applied to both ends of the EL element 1. On the other hand, when the scanning voltage is negative, a combined voltage having a magnitude of (scanning voltage + data voltage) is applied to both ends of the EL element 1, so that the combined voltage applied in the positive field and the negative field is large. And the difference between the applied voltages can be further increased, so that the emission luminance of the EL element 1 can be further improved.
[0063]
Furthermore, since the gate of the P-channel FET 15 constituting the reference voltage switching circuit 7 is coupled to the control signal output from the controller 4 by the capacitor 19, the gate of the P-channel FET 15 whose source is connected to the ground is connected. With a simple configuration, it can be set to a negative potential and turned on. Since another switching element or the like is not required to drive the FET 15, the switching of the FET 15 can be performed at higher speed.
[0064]
Further, since the wiring resistance r of the scanning electrode is set based on the value of the resistance value R that satisfies the expression (1), when both of the FETs 13 and 14 constituting the output stage of the scanning driver IC 5 are turned off. In addition, since the voltage generated in the wiring resistance due to the discharge of the EL element 1 is also superimposed, it is possible to reliably prevent the FET 13 or 14 from being broken.
[0065]
(Second embodiment)
FIGS. 9 and 10 show a second embodiment of the present invention. The same parts as those in the first embodiment are denoted by the same reference numerals, and the description thereof will be omitted. Only the different parts will be described below. In the second embodiment, as shown in FIG. 9, an EXOR gate 24 is omitted from a data driver IC (data driver circuit) 25 in place of the data driver IC 6. The output data from the latch 23 of the data driver IC 25 is output to the data electrode 9 via a driver (not shown).
[0066]
Therefore, the controller 4 does not output the inverted signal REV, but instead outputs the data signal DATA and the strobe signal STB each time the positive and negative fields are switched (see FIG. 10).
In the case of the second embodiment configured as described above, substantially the same effects as in the first embodiment can be obtained.
[0067]
(Third embodiment)
FIGS. 11 to 14 show a third embodiment in which the present invention is applied to a printer head of an optical printer. The same parts as those in the first embodiment are denoted by the same reference numerals and description thereof will be omitted. Will be described only. FIG. 11 schematically shows a main structure of the optical printer.
[0068]
The photosensitive drum 31 rotates clockwise in FIG. 11, and first, the surface of the photosensitive drum 31 is negatively charged by the charging unit 32. Subsequently, exposure according to print image data is performed by the EL element array 33 and the selfoc lens 34 shown in FIG. A combination of the EL element array 33 and the SELFOC lens 34 becomes a printer head 60. The potential of the exposed portion of the photosensitive drum 31 is increased to form an electrostatic latent image. Next, toner is adhered to the charged portion in the developing section 35 to form a toner image.
[0069]
The toner image formed on the surface of the photosensitive drum 31 is transferred to a sheet 37 at a transfer unit 36, and the transferred image is fixed to the sheet 37 at a fixing unit 38. Thereafter, the charge of the photosensitive drum 31 is removed by the charge removing unit 39, and the cleaning unit 40 further cleans the toner.
[0070]
FIG. 12 is a perspective view mainly showing the printer head 60 and the photosensitive drum 31. The EL element array 33 is configured as a linear light source, and the SELFOC lens 34 is configured as a microlens array. The light emitted from the EL element array 33 is condensed by a selfoc lens 34 and projected on the surface of the photosensitive drum 31.
[0071]
FIG. 13 shows an EL element array 33 constituted by using the EL elements 1 in the first embodiment. The glass substrate 51 is configured to double as the substrate of the EL element array 33. In addition, the first electrode 52 (the scanning electrode is a light source of the optical printer, and since the EL elements 1 may be arranged in a large number in a line, only one first electrode 52 is formed.
[0072]
The glass substrate 51 is electrically connected to a control circuit 42, a scanning driver IC (scan driver circuit) 43, a data driver IC (data driver circuit) 44, and a control circuit of the optical printer body. External connection terminals 45 are mounted. Then, the control circuit 42 causes the EL element 1 to emit light by the same driving method as the controller 4 of the first embodiment.
[0073]
FIG. 14 shows the relative intensity of the optical power of the EL element when the level of the voltage applied to the EL element and the number of pulses are changed. That is, the relative intensity of the optical power tends to increase as the number of applied voltage pulses increases.
[0074]
Here, since it is costly to increase the withstand voltage of both driver ICs 43 and 44, the withstand voltage of the scanning side driver IC 43, which is relatively easy to increase the withstand voltage, is about 230V, and the withstand voltage of the data side driver IC 44 is about 55V. About. Conventionally, for example, by setting the positive selection voltage to 216 V, the negative selection voltage to -166 V, and the data voltage to 0 V and 55 V, as described in the first embodiment, the combined voltage for causing the EL element to emit light is obtained. Was set to be symmetric at ± 216 V.
[0075]
On the other hand, in the present embodiment, the emission voltage of the EL element is improved while the withstand voltage of the driver ICs 43 and 44 is maintained as usual by performing the asymmetric emission driving with the selection voltage on the scanning side set to ± 216 V. Is possible.
[0076]
As shown in FIG. 14, the voltage at which the EL element substantially starts to emit light is at a level considerably lower than the selection voltage. However, when used as a printer head, contrast by light emission power (for example, when the luminance ratio is 10%) is clearly distinguished between the print ON state where a latent image is formed on the photosensitive drum 31 and the print OFF state where a latent image is not formed. : 1) can be obtained. Therefore, if the condition is satisfied, there is no problem even if the EL element emits light in the printing OFF state.
[0077]
As described above, according to the third embodiment, the printer head 60 including the driving device similar to the driving device 3 of the first embodiment and using the EL element 1 driven by the driving device as a light source is configured. An optical printer capable of high-speed printing can be configured.
[0078]
The present invention is not limited to the embodiment described above and shown in the drawings, and the following modifications or extensions are possible.
The selection voltage and the data voltage may be appropriately set according to the individual design, the allowable breakdown voltage of the driver IC, and the like.
The configuration is not limited to the one that performs the asymmetric driving, and the data voltage of the EL element 2 to be illuminated may be set to 0 V in the negative field to perform the symmetric driving at ± 216 V.
The configuration for driving the gate of the P-channel FET 15 is not limited to the capacitor coupling, but may be configured so that a driving switching element is separately arranged and driven.
In the third embodiment, the structure of the scanning electrodes may be divided and arranged along the arrangement direction of the EL elements as proposed in Japanese Patent Application No. 2002-259948.
[Brief description of the drawings]
FIG. 1 is a first embodiment when the present invention is applied to a dot matrix type EL display, and is a timing chart of each control signal.
FIG. 2 is a diagram showing a dot matrix type EL display formed using EL elements and a driving device thereof.
FIG. 3 is a diagram showing an electrical configuration of an output stage portion of a scanning driver IC for one scanning electrode;
FIG. 4 is a diagram showing an electrical configuration of a reference voltage switching circuit.
FIG. 5 is a diagram showing an electrical configuration of a data-side driver IC.
FIG. 6 is a diagram showing QV characteristics of an EL element.
FIG. 7 is an equivalent circuit diagram for explaining a calculation for obtaining a wiring resistance r;
8A is a plan view showing the structure of an inorganic EL device, and FIG. 8B is a diagram schematically showing a cross section taken along line AA of FIG.
FIG. 9 is a view corresponding to FIG. 5, showing a second embodiment of the present invention.
FIG. 10 is a diagram corresponding to FIG. 1;
FIG. 11 is a diagram showing a third embodiment in which the present invention is applied to a printer head of an optical printer, schematically showing a main structure of the optical printer;
FIG. 12 is a perspective view showing a photosensitive drum and a printer head.
FIG. 13 is a diagram showing an EL element array constituting a printer head.
FIG. 14 is a diagram showing the relative intensity of the optical power of the EL element when the voltage level applied to the EL element and the number of pulses are changed.
[Explanation of symbols]
1 is an EL element, 2 is an EL display, 3 is a driving device, 4 is a controller (control circuit) 4, 5 is a scanning side driver IC (scanning side driving circuit), 6 is a data side driver IC (data side driving circuit), 7 is a reference voltage switching circuit, 8 is a scan electrode, 9 is a data electrode, 10 is a diode, 11 is an inverting buffer (buffer), 12 is a pull-up resistor, 13 is a P-channel MOSFET, 14 is an N-channel MOSFET, and 15 is a P-channel MOSFET. A channel MOSFET, 16 is an N-channel MOSFET, 25 is a data driver IC (data driver), 33 is an EL element array, 43 is a scanning driver IC (scan driver), and 44 is a data driver IC (data driver). Driving circuit), 60 denotes a printer head.

Claims (8)

Driving an EL display having pixels as inorganic EL elements formed at intersections of scanning electrodes and data electrodes,
A scanning-side driving circuit configured to be able to apply a scanning voltage to the scanning electrode;
A reference voltage switching circuit that switches and outputs a voltage serving as a reference of the scan driving circuit;
A data drive circuit for applying a data voltage to the data electrode;
A control circuit that outputs a control signal to the scan-side and data-side drive circuits and the reference voltage switching circuit,
Applying to each pixel by a line sequential scanning method while alternately inverting the polarity of the composite voltage of the scanning voltage and the data voltage,
An EL display driving device that drives the EL element to emit light a plurality of times during one selection period on a scanning side,
An output stage of the scanning side driving circuit is configured by P-channel and N-channel MOSFETs connected by a totem pole between a high voltage power supply side and a reference voltage side,
The reference voltage switching circuit includes a P-channel MOSFET and an N-channel MOSFET each having one end connected to the ground and the other end connected to each of the reference voltage and the high-voltage power supply.
The control circuit includes:
When outputting a scanning voltage of a positive polarity from the scanning side drive circuit, switching on and off of a MOSFET arranged in the output stage,
An EL display driving apparatus characterized in that when a negative scanning voltage is output from the scanning side driving circuit, the MOSFET constituting the reference voltage switching circuit is turned on and off. The reference voltage switching circuit includes a drive power supply connected between a high voltage power supply and a reference voltage of the scan side drive circuit and having a power supply voltage equivalent to the scan voltage,
The control circuit includes:
With respect to the scanning-side drive circuit, only the P-channel MOSFET is turned on at the timing of outputting the positive-polarity scanning voltage, and in other cases, only the N-channel MOSFET is turned on.
2. The EL according to claim 1, wherein, in the reference voltage switching circuit, only the N-channel MOSFET is turned on at a timing of outputting a negative scanning voltage, and in other cases, only the P-channel MOSFET is turned on. Display drive. A buffer disposed between the scanning side drive circuit and the control circuit;
A diode reversely connected between the control circuit and the buffer;
3. The EL display driving device according to claim 1, further comprising: a pull-up resistor that pulls up an input terminal side of the buffer. The data-side drive circuit is configured to be able to hold a logic level for applying a data voltage to the data electrode, and is configured to be able to invert the logic level in response to an inversion signal input from outside. The EL display driving device according to claim 1, wherein: The scanning drive circuit is configured to output a bipolar scanning voltage having an equal absolute value,
The data-side drive circuit is configured to output 0 V when the scanning voltage is positive when the EL element emits light, and to output a data voltage when the scanning voltage is negative when the EL element emits light. The method according to any one of claims 1 to 4, wherein when the scanning voltage is not emitted, a data voltage is output when the scanning voltage has a positive polarity, and 0 V is output when the scanning voltage has a negative polarity. EL display driving device. 6. The EL according to claim 1, wherein a gate of a P-channel MOSFET constituting the reference voltage switching circuit is capacitor-coupled to a control signal output from the control circuit. Display drive. Assuming that the scanning voltage is V, the withstand voltage of the scanning drive circuit is V0, the capacitance of the EL element is C, and the discharge time of the EL element is t, the wiring resistance r of the scanning electrode is
V · exp (−t / (C · R)) + V ≦ V0
The EL display driving device according to any one of claims 1 to 6, wherein the setting is performed based on a value of a resistance value R that satisfies the following condition. A printer head for an optical printer, comprising: the driving device according to claim 1; and an EL element driven by the driving device as a light source.

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