JPH0998075A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To drive a P-channel LDMOS transistor TR without generating a reactive current. SOLUTION: Four blocks 1, 2, 3, and 4 are formed in insular silicon areas surrounded with silicon oxide films on a silicon substrate. The block 1 latches data DAT1 (the drive signal in a low voltage level) for driving a P-channel LDMOS transistor TR 12. In the block, resistors 7 and 8 for dividing a high voltage and a MOS TR 9 are connected in series, and the MOS TR 9 is turned on for a short time by the drive signal latched in the block 1 to output the voltage divided drive signal in a high voltage level (data DAT2) from between resistors 7 and 8. the block 3 receives supply of a reference potential from the outside to latch the drive signal from the block 2 and outputs it to the gate terminal of the P-channel LDMOS TR 12.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device having a high voltage output switching portion composed of MOS transistors.

[0002]

2. Description of the Related Art In a display LSI or the like, a high voltage output is required, so that the output section is composed of a high breakdown voltage transistor. The high breakdown voltage transistor used here is an LDMOS (Lateral Double Diffused MO).
S) transistors and high breakdown voltage MOS transistors. The LDMOS transistor has a structure as shown in FIG. That is, the N well region 36 is formed on the P-type silicon substrate 56, and the N well region 3 is formed.
An N ⁺ bulk contact region 37 and a P ⁺ source region 38 are formed in the region 6. Further, a P ⁺ drain region 39 is formed at a position separated from the N well region 36.
A LOCOS oxide film 40 is formed on the upper surface of the P-type silicon layer 32 between the N well region 36 and the P ⁺ drain region 39.
And a gate oxide film 41 are formed, and a gate electrode 42 is arranged on the oxide films 40 and 41. As described above, the structure is such that the electric field relaxation region (P ⁻ region) is provided on the drain side, and a breakdown voltage is provided between the drain and the source and between the gate and the drain. Normal M between gate and source
Since the structure is the same as that of the OS structure, the breakdown voltage is not as high as between the gate and the drain. Therefore, in circuit design, it is necessary not to apply a voltage higher than the allowable voltage between the gate and the source. Although a P-channel LDMOS transistor is shown in FIG. 11, an N-channel L whose conductivity type is reversed is shown.
The DMOS transistor has a similar structure.

An example of a drive circuit using such an LDMOS transistor is shown in FIG. In FIG. 12, P
Channel LDMOS transistor 44 and N channel LD
The MOS transistor 45 is connected in series to form a switching circuit. Logic unit (control circuit) 43
Operates at 5 volts. Further, the output unit operates at 100 volts, for example. That is, 100 volts is applied to the series circuit of the transistors 44 and 45. Then, the N-channel LDMOS transistor 45 is directly driven by the output from the logic section 43, or is driven through a booster circuit (for example, boosted to 8 volts). On the other hand, P
Since the channel LDMOS transistor 44 has a small gate-source breakdown voltage as described above,
You cannot directly enter the output from. That is, if the voltage is directly input, 95 V is applied between the gate and the source, which cannot be achieved in terms of withstand voltage.

Therefore, as shown in FIG.
A general method is to generate a drive voltage for the P-channel LDMOS transistor 44 in the output section by using 47 and the high voltage MOS transistor 48 for control. P by the boost circuit
A method of generating the drive voltage of the channel LDMOS transistor 44 may be considered, but the output (0 to 0 of the logic unit 43
In order to boost (5 volts) to 90 to 100 volts, the circuit scale becomes very large, which is not realistic.

Next, regarding a high voltage MOS transistor
Describe. The high voltage MOS transistor is shown in FIG.
It is structured like this. That is, the transaction shown in FIG.
Compared to the structure of the transistor, P on the silicon substrate 56^-Territory
Areas 49 and 50 are formed, P ^-N in area 49⁺Bulkco
Contact area 37 and P⁺A source region 38 is formed, P
^-P in area 50⁺A drain region 39 is formed.
In this way, electric field relaxation regions are provided on both the source and drain sides.
Area (P^-Since the areas 49, 50) are provided,
There is a breakdown voltage between the sources and between the gate and drain. still,
A P-channel MOS transistor is shown in FIG.
The same applies to N-channel MOS transistors whose conductivity types are reversed.
It has a similar structure.

In a switching circuit using such a high voltage MOS transistor, the configuration shown in FIG. 14 is well known. That is, the P-channel MOS transistor 5
1 and N channel MOS transistor 52 are connected in series, P channel MOS transistor 53 and N channel MOS transistor 54 are connected in series, and the gate of P channel MOS transistor 53 and transistor 5 are connected.
1, 52 are connected to each other, the gate of the P-channel MOS transistor 51 is connected to the drains of the transistors 53 and 54, and the N-channel MOS transistor 5 is connected.
An inverter 55 is interposed between the gates of 2, 54.

[0007]

As a conventional method, LD is used.
The configuration using the MOS transistor and the configuration using the high breakdown voltage MOS transistor have been described, but these have the following problems.

First, in the configuration shown in FIG. 12, a P-channel LD is used.
While the MOS transistor 44 is being driven, a current (reactive current) flows through the resistors 46 and 47 that generate a drive voltage, resulting in a large power consumption of the LSI. Further, since the gate voltage is generated by the resistance voltage division, when the power supply voltage V _HI (power supply voltage connected to the resistor 46) of the high breakdown voltage portion becomes smaller, the generated gate voltage also becomes smaller and the LDMOS is reduced.
There is also a problem that the transistor 44 cannot be driven.

On the other hand, in the structure shown in FIG. 14, the P-channel high breakdown voltage MOS without generating the reactive current as described above.
Although the transistor 51 can be driven, a high breakdown voltage MOS transistor must be used for this structure. As shown in FIG. 13, the high breakdown voltage MOS transistor has an electric field relaxation region (P
^- since the provided region 49 and 50), the resistance component between the source and the drain is larger than the LDMOS transistor. In order to ensure the same current capacity as the LDMOS transistor, the transistor size must be larger than that of the LDMOS transistor. As a result, the chip size of the LSI is increased, resulting in an increase in cost.

An object of the present invention is to solve these problems and provide a semiconductor integrated circuit device capable of driving a P-channel LDMOS transistor without generating a reactive current. In addition, a semiconductor integrated circuit device capable of reliably driving a P-channel LDMOS transistor even when the power supply voltage becomes low is provided.

[0011]

According to the first aspect of the present invention, in the level converter, the switching element is turned on for a short time by the drive signal of the low voltage level for driving the P-channel LDMOS transistor. It outputs a high-voltage level drive signal divided between both resistors. The latch part
The drive signal from the level conversion unit is latched and output to the gate terminal of the P-channel LDMOS transistor of the switching unit. Then, the P channel LDM of the switching unit
The OS transistor turns on. At this time, P channel M
A high voltage is applied to the gate terminal of the OS transistor,
A P-channel LD having a small potential difference between the source terminal and the gate terminal of the P-channel MOS transistor and a low breakdown voltage.
A MOS transistor can be used. Further, since the switching element is turned on for a short time in the level conversion unit, almost no reactive current flows in the series circuit of the first and second resistors and the switching element.

In this way, the P-channel LDMOS transistor can be driven without generating a reactive current. According to the second aspect of the present invention, the latch unit receives the reference potential from the outside and receives the P-channel LDM.
The voltage applied to the gate of the OS transistor is generated. Therefore, since the voltage is generated by resistance voltage division in the level conversion unit, the generated voltage also decreases as the power supply voltage decreases, but the latch unit receives the reference potential from the outside and changes the gate applied voltage. Since it is generated, it is possible to prevent the gate voltage from decreasing and it is possible to reliably drive the LDMOS transistor.

Further, although the latch portion receives a reference potential supplied from the outside, since the latch portion is formed in the island-shaped silicon region surrounded by the insulating film on the semiconductor substrate, the reference potential is applied to other regions. Can be different from the reference potential of.

According to the third aspect of the present invention, the driving signal of the low voltage level sends the driving contents of each switching section serially, and the front latch section drives the object to be driven from the serially sent signal. The signal for the switching unit of 1 is latched and sent to the level conversion unit. Therefore, it is possible to capture necessary signals. .

According to the fourth aspect of the present invention, since the switching section and the level converting section are formed in the island-shaped silicon region surrounded by the insulating film on the semiconductor substrate, they are insulated and separated from each other. Interference can be prevented in advance.

According to the fifth aspect of the present invention, the clock level conversion unit level-converts the clock supplied to the latch unit. Therefore, it is possible to configure the control signal to the semiconductor integrated circuit device only in the low voltage range (for example, in 0 to 5 volts).

According to the sixth aspect of the present invention, the reference potential supply means supplies a predetermined reference potential to the latch section. Therefore, the external system configuration can be downsized. According to the invention described in claim 7, the Zener diode is connected to the signal line between the output section of the level conversion section and the input section of the latch means. Then, the gate of the MOS transistor provided in the latch portion is protected. That is,
Since the level converter uses resistance voltage division, the amplitude of the output voltage from the level converter increases as the power supply voltage of the high-voltage operating unit increases, and if the amplitude of this output voltage exceeds the allowable voltage range, the latch Although it destroys the input transistor in some parts, the Zener diode protects the gate.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) A first embodiment of the present invention will be described below with reference to the drawings.

Here, a display LSI will be described as an example. FIG. 1 shows a basic configuration, and FIG. 2 shows a specific configuration. In FIG. 1, an LSI is composed of four blocks 1, 2, 3, and 4. The block 1 as the pre-latch unit is a latch circuit that latches the data DAT1 input from the outside of the LSI. The block 2 serving as a level conversion unit is a level shift circuit that level-converts the data latched in the block 1 to output the data DAT2. The block 3 as a latch unit is a latch circuit that latches the data DAT2 after the level conversion in the block 2. The block 4 as a switching unit is a switching circuit that outputs a high voltage. Each of the blocks (circuits) 1 to 4 is, as shown in FIGS. 3 and 4, island-shaped silicon which is surrounded by silicon oxide films (insulating films) 31 and 34 and isolated on a silicon substrate 30 (semiconductor substrate). It is formed in each area. That is, the P-type silicon layer 32 is formed on the silicon substrate 30 via the buried silicon oxide film 31, the trench 33 is formed in the silicon layer 32, and the silicon oxide film 34 and the poly silicon are formed in the trench 33. A silicon layer 35 is arranged. A region surrounded by the silicon oxide films 31 and 34 is an island-shaped silicon region (SOI region; Silicon).
On Insulator area). Further, FIG.
4 shows the case where a P channel LDMOS transistor is formed in the SOI region, and FIG. 4 shows the case where a P channel high breakdown voltage MOS transistor is formed in the SOI region. The structure of the transistor is the same as in FIGS. 11 and 13, and the same reference numerals are given.

The data DAT1 is a binary signal (driving signal) of low voltage level of 0 volt and 5 volt, which is an off command signal at 0 volt and an on command signal at 5 volt. The output block 4 at the final stage has 0 volt to high voltage V _HI.
(= 100V), block 1 is 0V ~
Operates at low voltage V _LOW (= 5 volts), block 2 is 0
Operates from Volts to high voltage V _HI (= 100 Volts). In addition, block 3 operates at 95-100 volts. That is, from the high voltage V _HI (= 100 V) to the low voltage V _LOW
95 volt minus (= 5 volt) and high voltage V _HI
Operates at voltages between (= 100 volts).

As described above, in this structure, the block 3 for latching the level-converted data DAT2 is provided, and this block 3 (latch circuit) is 95-1.
Operates at 00 volts. That is, the operating voltage range of block 3 is the same as that of block 1 (5 volt operation),
The reference potential is different. This reference potential (95 V) is supplied from the outside. This is possible because of the SOI structure in which the island-shaped silicon regions can be isolated. That is, a region having a bulk potential (reference potential) different from that of the other regions can be easily formed.

In this example, the operating voltage of the block 1 is set to 5
The operating voltage of the high voltage output section is 100 volts, but the operating voltage is not limited to this. 2, which shows a specific configuration of each block in FIG. 1, the latch block 1 includes a latch circuit 5 and an AND gate 6. The latch circuit 5 is provided with a data input terminal, a clock input terminal, and an output terminal Q1, and receives the data DAT1 and the clock CLK1. The output terminal Q1 of the latch circuit 5 is connected to the input terminal of the AND gate 6. The read enable signal RE1 is input to the other input terminal of the AND gate 6.

The level shift block 2 includes a resistor (first resistor) 7, a resistor (second resistor) 8 and an N-channel LDMO.
An S-transistor (switching element) 9 and voltage dividing resistors 7 and 8 for performing level conversion and an N-channel LD
The MOS transistor 9 is connected in series. Resistance 7
High voltage V _HI (= 100V) is applied to one end of
The source terminal of the N-channel LDMOS transistor 9 is grounded. N-channel LDMOS transistor 9
The gate terminal of is connected to the output terminal of AND gate 6,
Input the data DAT1. The connection point a between the resistor 7 and the resistor 8 serves as the output terminal of the block 2, and the level-converted data DAT2 is output from the output terminal.

The N-channel LDMOS transistor 9
Although the structure shown in FIG. 3 is used as, the N-channel high breakdown voltage MOS transistor having the structure shown in FIG. 4 may be used instead.

The latch block 3 includes a latch circuit 10 and an AND gate 11. The latch circuit 10 is provided with a data input terminal, a clock input terminal, and an output terminal Q2. The connection point a is connected to the data input terminal of the latch circuit 10, and the data DAT2 is input.
Further, the clock CLK2 is input to the latch circuit 10. The clock CLK2 is the data DAT after level conversion.
2 for latching, 95 volts and 100
It is a binary signal of Volt. Output terminal Q of the latch circuit 10
2 is connected to the input terminal of the AND gate 11. The read enable signal RE2 is input to the other input terminal of the AND gate 11. Further, the AND gate 11 is supplied with a high voltage V _HI (= 100 V) and a voltage (V _HI −V _LOW ) lower by 5 V than that as a drive voltage source (reference potential) from the outside.

The switching block 4 includes a P channel L
The DMOS transistor 12 and the N-channel LDMOS transistor 13 are connected in series, and the P-channel LDMO
The high voltage V _HI (= 1) is applied to the source terminal of the S-transistor 12.
00 volt) is applied, and the source terminal of the N-channel LDMOS transistor 13 is grounded. The gate terminal of the P-channel LDMOS transistor 12 is connected to the output terminal of the AND gate 11. The gate terminal of the N-channel LDMOS transistor 13 is connected to the output terminal of the AND gate 6 of the latch block 1 via the inverter 21 and the AND gate 22. P-channel LDMOS transistor 12 and N-channel LDMO
A connection point b with the S transistor 13 serves as an output terminal of the switching block 4. This output terminal is connected to a pixel such as electroluminescence (EL) of a display, and when the P-channel LDMOS transistor 12 is turned on, an H-level voltage is applied and the pixel is lit,
L by turning off the P-channel LDMOS transistor 12
It becomes a level and the same pixel goes out.

Although the drive circuit for one pixel is shown in FIGS. 1 and 2, the drive circuits shown in FIGS. 1 and 2 are provided for each pixel arranged in a matrix. And an external display control device (controller)
As shown in (a) of FIG. 5 as data DAT1, a binary signal indicating the display content of pixel number 1, pixel number 2
A binary signal indicating the display content of the pixel number n
A binary signal indicating the display content of (total number of pixels) is serially sent. The drive circuit shown in FIGS. 1 and 2 extracts a corresponding binary signal to display a pixel. The data DAT1
Is a frequency of about 15 to 20 MHz.

Next, the operation of the semiconductor integrated circuit device thus configured will be described. FIG. 5 is a time chart for explaining the operation. In FIG. 5, (a) is the data DAT1 input to the latch block 1 as described above,
(B) is the clock CLK input to the latch block 1
1, (c) is the output Q1 of the latch circuit 5, (d) is the read enable signal RE1 input to the latch block 1,
(E) is the gate voltage NG of the N-channel LDMOS transistor 9, (f) is the data DAT2 input to the latch block 3, (g) is the clock CLK2 input to the latch block 3, and (h) is the latch circuit 10. Output Q2,
(I) shows the read enable signal RE2 input to the latch block 3, (j) shows the gate voltage of the P-channel LDMOS transistor 12, and (k) shows the output OUT.

5 (a) to 5 (e) have binary values of 0 volt and 5 volt, respectively. (F) to (j) have binary values of 95 V and 100 V, respectively.
The output OUT of (k) has two values of 0 volt and 100 volt.

The operation for displaying the pixel number 1 will be described below with reference to FIG. Data DAT1 input from the outside of the LSI at the timing of t1 in FIG. 5 is latched by the latch circuit 5 of the block 1 by the clock CLK1. When the read enable signal (terminal) RE1 becomes H level at the timing of t2 in FIG. 5, the N channel LDMOS transistor 9 of the level shift block 2
Is turned on and the data DAT1 is 95 to 1 by the resistors 7 and 8.
The level is converted to the data DAT2 of 00 volt. That is, the 5-volt on-command signal is converted into a 95-volt on-command signal.

The voltage generated by the resistance voltage division (data D
AT2) is block 3 at the timing of t3 in FIG.
Is latched by the latch circuit 10 at the rising edge of the clock CLK2. When the read enable signal (terminal) RE1 becomes L level at the subsequent timing of t4, the N-channel LDMOS transistor 9 is turned off. The latched data DAT2 is read by the read enable signal (terminal) RE2 at the timing of t5 in FIG. 5, the data DAT2, that is, 95 V is applied to the gate of the P-channel LDMOS transistor 12 of the switching block 4, and the transistor 12 is turned on. Turn on.

As described above, the data DA read by the read enable signal RE1 at the timing of t1 in FIG.
By T1, 95 V is applied to the gate of the N-channel LDMOS transistor 12 to turn on the same. As a result, the switching blocks 4 to 10
0 volt is output and the pixel is lit.

Since the N-channel LDMOS transistor 9 in the level shift block 2 is turned on for the period of t2 to t4 (for example, 57 to 100 nsec) in FIG. 5, a reactive current generated in the level shift block 2, That is, the current flowing through the resistors 7 and 8 and the transistor 9 is also very small only during the period when the gate (NG) of the N-channel LDMOS transistor 9 is at H level.

On the other hand, when the input data DAT1 is an off command signal of 0 volt, the N channel LDMOS transistor 9 of the level shift block 2 is turned off and the data DAT is output.
1 is converted to 100 volt data DAT2 and output. This level-converted data DAT2 is block 3
It is latched by the clock CLK2 in the latch circuit 10 in FIG. The latched data DAT2 is read by the read enable signal (terminal) RE2, and the data DAT2 is read.
2 or 100 volts is block 4 P-channel LDM
Applied to the gate of the OS transistor 12, the transistor 12 is turned off.

The N-channel LDMOS transistor 1
3 is driven (turned on) by the output signal of the block 1 (5 volt signal). As a result, 0 is output from the switching block 4.
The volt is output and the pixel goes out.

As described above, in this embodiment, the blocks 1, 2, 3 and 4 are formed in the island-shaped silicon regions (SOI regions) surrounded by the insulating film on the silicon substrate, respectively.
In block 2, a high voltage level drive signal obtained by turning on the MOS transistor 9 for a short time by the data DAT1 (low voltage level drive signal) for driving the P-channel LDMOS transistor 12 and dividing the voltage from between the resistors 7 and 8. Is output, and in block 3, the drive signal from block 2 is latched to output the P-channel LDMOS of block 4.
The output is made to the gate terminal of the transistor 12.
Therefore, a high voltage is applied to the gate terminal of the P-channel MOS transistor 12, and a P-channel LDMOS transistor having a small potential difference between the source terminal and the gate terminal of the P-channel MOS transistor 12 and a low breakdown voltage can be used. Further, in the block 2, since the MOS transistor 9 is turned on for a short time, the resistors 7 and 8 are
Almost no reactive current flows in the series circuit of the MOS transistor 9 and the MOS transistor 9.

In this way, the P-channel LDMOS transistor 12 can be driven without generating a reactive current. Further, in the level shift block 2, since the voltage is generated by the resistance voltage division, the generated voltage becomes smaller as the power supply voltage of the high breakdown voltage portion becomes smaller, but the latch block 3 is supplied with the reference potential from the outside. Since the voltage applied to the gate of the P-channel LDMOS transistor 12 is received to prevent the gate voltage from decreasing, the LDMOS transistor 12 can be driven reliably.
Also, the block 3 is supplied with a reference potential from the outside,
Since the block 3 is formed in the island-shaped silicon region (SOI region) surrounded by the insulating film on the silicon substrate, it can be different from the reference potential in other regions.

Further, the block 1 can latch a necessary signal from the signals serially transmitted and take in the necessary signal. Furthermore, since the block 4 and the block 2 are formed in different SOI regions, they are isolated from each other and do not receive mutual interference. (Second Embodiment) Next, a second embodiment will be described focusing on differences from the first embodiment.

FIG. 6 shows a second embodiment. In this example, a block 14 (clock level conversion unit) for converting the level of the clock CLK2 supplied to the block 3 is provided. More specifically, as shown in FIG.
16 and MOS transistor 17 are connected in series, and resistor 1
High voltage V _HI (= 100V) is applied to one end of 5,
The drain terminal of the MOS transistor 17 is grounded.
Further, the resistor 15 and the resistor 16 are connected to the latch circuit 10 of the block 3. And the MOS transistor 1
A clock CLK3 (binary signal of 0 volt and 5 volt) is input to the gate terminal of 7 and level-converted by resistors 15 and 16 and output to the block 3 as clock CLK2 (binary signal of 95 volt and 100 volt). .

By providing the block 14 inside the LSI, the control signals from the external device to the LSI can be set to 0 to 0.
The system can be simplified because it can be configured with only 5 volts. (Third Embodiment) Next, a third embodiment will be described focusing on differences from the first embodiment.

FIG. 8 shows a third embodiment. In the first embodiment, the block 3 is externally _{supplied with a} high voltage V _HI (= 1).
00 volt) and a voltage 5 volts lower than that (V _HI −
V _LOW ), but in the present embodiment, the power supply circuit block 18 (reference potential supply means) is provided inside the LSI, and a high voltage V _HI (= 100 V) is supplied from the outside to supply the power supply circuit block. 18 generates the reference potential of the block 3 to generate the high voltage V _HI (= 100 volt) and the reference potential (95
Bolt) and is supplied to the block 3. As a result, the external system configuration can be reduced in size. (Fourth Embodiment) Next, the fourth embodiment will be described focusing on the differences from the first embodiment.

FIG. 9 shows a fourth embodiment. The line between the output section of the block 2 and the input section of the block 3 is provided with a protection circuit 19 composed of a Zener diode for gate protection of the input section of the block 3. More specifically, as shown in FIG. 10, a plurality of Zener diodes 20 are connected in series, one end of the Zener diode 20 is connected to the output terminal of the block 2, and a reference potential of 100 V is applied to the other end to output the output of the block 2 of 100. Be sure to clamp it on the bolt.

That is, since the level shift block 2 uses resistance voltage division, the amplitude of the output voltage from the block 2 increases as the power supply voltage of the high voltage operating section increases. When the amplitude of this output voltage exceeds the allowable voltage range of the logic circuit, the input transistor of the block 3 is destroyed. However, due to the Zener diode 20 of the protection circuit 19,
The gate of the MOS transistor in the input part of the block 3 is protected, and the dependency on the power supply voltage is eliminated.

[Brief description of drawings]

FIG. 1 is a basic configuration diagram according to a first embodiment.

FIG. 2 is a circuit configuration diagram according to the first embodiment.

FIG. 3 is a cross-sectional view of an SOI region and a P-channel LDMOS transistor formed in the SOI region.

FIG. 4 is a cross-sectional view of an SOI region and a P-channel high breakdown voltage MOS transistor formed in the SOI region.

FIG. 5 is a time chart for explaining the operation in the first embodiment.

FIG. 6 is a basic configuration diagram according to the second embodiment.

FIG. 7 is a circuit configuration diagram according to a second embodiment.

FIG. 8 is a configuration diagram according to a third embodiment.

FIG. 9 is a basic configuration diagram according to a fourth embodiment.

FIG. 10 is a circuit configuration diagram according to a fourth embodiment.

FIG. 11 is a sectional view of an LDMOS transistor.

FIG. 12 is a configuration diagram of a semiconductor integrated circuit device using an LDMOS transistor.

FIG. 13 is a cross-sectional view of a high voltage MOS transistor.

FIG. 14 is a configuration diagram of a semiconductor integrated circuit device using a high voltage MOS transistor.

[Explanation of symbols]

1 ... Block (pre-latch section), 2 ... Block (level conversion section), 3 ... Block (latch section), 4 ... Block (switching section), 7 ... Resistor, 8 ... Resistor, 9 ... N-channel LDMOS transistor ( Switching element), 1
2 ... P-channel LDMOS transistor, 13 ... N-channel LDMOS transistor, 14 ... Block (clock level section), 18 ... Power supply circuit block (reference potential supply means), 20 ... Zener diode, DAT1 ... Data (low voltage level drive signal) ), DAT2 ... Data (driving signal of high voltage level).

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Takayuki Matsuda 1-1, Showa-cho, Kariya city, Aichi prefecture Nihon Denso Co., Ltd.

Claims (7)

[Claims] 1. In a semiconductor integrated circuit device having a high voltage output switching section composed of a P-channel LDMOS transistor and an N-channel LDMOS transistor, a first resistor and a second resistor for switching a high voltage and switching. P-channel LDMOS device connected in series
A level conversion unit that outputs a high voltage level drive signal in which the switching element is turned on for a short time by a low voltage level drive signal for driving a transistor and is divided between the resistors; And a latch unit for latching the drive signal of the above and outputting it to the gate terminal of the P-channel LDMOS transistor of the switching unit. 2. The latch section is formed on an island-shaped silicon region surrounded by an insulating film on a semiconductor substrate, receives a reference potential from the outside, and generates a voltage applied to a gate of a P-channel LDMOS transistor. Claim 1
The semiconductor integrated circuit device according to 1. 3. A plurality of the switching units are provided, and the drive signal of the low voltage level is to serially output the drive content of each switching unit, and the switching target to be driven is output from the serially output signals. 2. The semiconductor integrated circuit device according to claim 1, further comprising a pre-latch unit for latching a signal to the unit, which is provided in a stage preceding the level conversion unit. 4. A switching part is formed on a semiconductor substrate in a first island-shaped silicon region surrounded by an insulating film, and the level converting part is surrounded by an insulating film on the semiconductor substrate. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is formed in the second island-shaped silicon region. 5. The semiconductor integrated circuit device according to claim 1, further comprising a clock level conversion unit that level-converts a clock supplied to the latch unit. 6. The reference potential supply means for supplying a predetermined reference potential to the latch section, according to claim 1.
The semiconductor integrated circuit device according to 1. 7. A zener diode for protecting a gate of a MOS transistor provided in the latch part is provided for a signal line between an output part of the level conversion part and an input part of the latch part. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is a semiconductor integrated circuit device.