JP5024316B2 - Voltage generation circuit and display device using the same - Google Patents

Description

  The present invention relates to a voltage generation circuit and a display device using the voltage generation circuit, and more particularly to a circuit when a load driving circuit and a voltage generation circuit are integrated on the same substrate as a display unit, and an arrangement thereof.

  A liquid crystal display device has advantages such as light weight, thinness, and low power consumption compared with a CRT (Cathode Ray Tube), and thus is used in various fields.

  Among the liquid crystal display devices, as shown in FIG. 9, the active matrix type liquid crystal display device has a matrix of pixels each having an amorphous silicon (a-Si) thin film transistor (TFT) as a switching element on a glass substrate. A liquid crystal display unit 11 is provided.

  This liquid crystal display device includes data driver ICs (integrated circuits) 21-1 to 21-5 for driving data lines, gate driver ICs 31-1 to 31-8 for controlling switching of pixels on each line, pixel electrodes, A common drive circuit IC 40 that drives a common electrode that is opposed to the liquid crystal layer and a power supply circuit IC 50 that supplies a voltage to the driver circuit and the drive circuit are provided.

  In the liquid crystal display device, when the voltage applied to the liquid crystal layer is always unipolar, a direct current component is applied to the liquid crystal layer for a long time, which causes problems such as deterioration of liquid crystal characteristics. For this reason, frame inversion driving for inverting the polarity of the voltage applied to the liquid crystal layer for each frame, line inversion driving for inverting for each line, and the like are performed (for example, see Patent Documents 1 and 2).

  In recent years, with the development of polysilicon (p-Si) TFT technology with higher current capability than a-Si, not only pixel switching elements but also various circuits can be formed on a glass substrate (for example, Non-patent documents 1 and 2).

  For example, for a liquid crystal display device for a mobile phone terminal of several inches class whose driving load is about several pF, as shown in FIG. 10, a data driver circuit 22 and gate drivers 32-1 and 32-2 are liquid crystal. It is mounted on the same substrate 10 as the pixels in the display device. As a result, it is possible to reduce the number of parts and connection parts required for the liquid crystal display device, and thus it is possible to reduce costs and achieve high reliability.

  On the other hand, the common drive circuit IC40 for performing line inversion drive drives the common electrode to the H level (VCOMH) and the L level (VCOML) every horizontal period. At this time, in order to drive the common electrodes of all the pixels of the liquid crystal display device at the same time, the common drive circuit IC 40 needs to drive a large load of several nF or more at a high speed of several μs.

  Therefore, conventionally, a bipolar transistor having high current capability or a single crystal Si MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor: metal oxide semiconductor field effect transistor) having a gate width of several millimeters is used at the output stage of the common drive circuit IC40. Is used.

  If the common drive circuit IC40 as described above is formed of p-Si TFTs and can be mounted on the same substrate 10 as the pixels in the liquid crystal display device, the same advantages as when data drivers and gate drivers are mounted can be obtained. It is done.

  However, in order to mount the common drive circuit IC40, since the current capability of the p-Si TFT is about 1/10 of that of the crystalline Si MOSFET, a TFT having a gate width of about several tens of millimeters is required at the output stage of the common drive circuit IC40. It becomes.

  In addition, the influence of wiring resistance on the driving speed must be taken into account. Therefore, in order to create the common drive circuit IC 40 on the same substrate 10 as the pixels in the liquid crystal display device, it is necessary to make a large area for arranging the common drive circuit IC 40 in a non-display area. It is difficult to frame.

  Further, as a design of the entire liquid crystal display device including the drive circuit, it is required to make the frame symmetrical. However, when the common drive circuit IC 40 is arranged, it is not easy to make the frame symmetrical.

Japanese Patent Laid-Open No. 11-194320 (page 3-5, FIG. 1) JP-A-11-194316 (page 3-7, FIG. 1)

“Low Temperature Poly-Si TFT-LCD with Integrated Analog Circuit” (T. Nakamura, et al., Asia Display / IDW'01 Proceedings, Oct. 16, 2001, pp. 1603-1606, F.g. “A 5-in, SVGA TFT-LCD with Integrated Multiple DAC Low-Temperature poly-Si TFTs” (Y. Mikami, et al., Asia Display / IDW'01 Procedings, 160. Op. 1610, FIG. 1)

  The conventional liquid crystal display device described above has a problem in that the circuit area of a common drive circuit using TFTs is increased because TFTs have lower current capability than bipolar transistors and single crystal Si MOSFETs.

  Further, in the conventional liquid crystal display device, since the circuit area of the common drive circuit is large and easily affected by the wiring resistance, the common drive circuit using TFT is arranged on the same substrate as the pixels in the liquid crystal display device. Has a problem that the frame is wide and not symmetrical.

  Accordingly, an object of the present invention is to solve the above-mentioned problems, and to provide a voltage generation circuit capable of realizing a symmetrical frame and a narrow frame without reducing the drive capability of the common drive circuit, and a display device using the voltage generation circuit. It is to provide.

The voltage generation circuit according to the present invention simultaneously drives a capacitive load in a display device in which a gate driver circuit for controlling switching of pixels of each line of the display unit is integrated on the same substrate as the substrate on which the display unit is mounted. A voltage generation circuit for generating a supply voltage to the display device drive circuit,
Arranged together with the display device drive circuit at a position facing the gate driver circuit across the display unit,
A first variable resistor for adjusting a voltage difference between a high level of the supply voltage and a low level of the supply voltage ;
A second variable resistor for adjusting a low level of the supply voltage ;
The variable portion of the first variable resistor is connected to the inverting input through the first resistor, one end of the second resistor is connected to the inverting input, and the other end of the second resistor is connected to the output, A first operational amplifier in which one end of a first capacitor is connected to the output, the other end is connected to a constant voltage, and a variable part of the second variable resistor is connected to a non-inverting input;
A constant voltage source is connected to the inverting input through a third resistor, one end of the fourth resistor is connected to the inverting input, the other end of the fourth resistor is connected to the output, and one end of the second capacitor Is connected to the output, the other end is connected to a constant voltage, and the variable part of the second variable resistor includes a second operational amplifier connected to a non-inverting input,
The first operational amplifier outputs a high level of the supply voltage, the second operational amplifier outputs a low level of the supply voltage;
The total resistance of the first variable resistor is 1/3 of the first resistor, and the total resistance of the second variable resistor and the first to fourth resistors on the same substrate It is the one of 1/3 or less.

The display device according to the present invention is a display device in which at least a gate driver circuit that controls switching of pixels of each line of the display unit is integrated on the same substrate as the substrate on which the display unit is mounted,
Positions facing the gate driver circuit across the display unit between a display device drive circuit that simultaneously drives a capacitive load in the display unit and a voltage generation circuit that generates a supply voltage to the display device drive circuit Placed in
A first variable resistor for adjusting a voltage difference between a high level of the supply voltage and a low level of the supply voltage ;
A second variable resistor for adjusting a low level of the supply voltage ;
The variable portion of the first variable resistor is connected to the inverting input through the first resistor, one end of the second resistor is connected to the inverting input, and the other end of the second resistor is connected to the output, A first operational amplifier in which one end of a first capacitor is connected to the output, the other end is connected to a constant voltage, and a variable part of the second variable resistor is connected to a non-inverting input;
A constant voltage source is connected to the inverting input through a third resistor, one end of the fourth resistor is connected to the inverting input, the other end of the fourth resistor is connected to the output, and one end of the second capacitor Is connected to the output, the other end is connected to a constant voltage, and the voltage generating circuit includes a second operational amplifier in which the variable portion of the second variable resistor is connected to a non-inverting input,
The first operational amplifier outputs a high level of the supply voltage, the second operational amplifier outputs a low level of the supply voltage;
The total resistance of the first variable resistor is 1/3 of the first resistor, and the total resistance of the second variable resistor and the first to fourth resistors on the same substrate It is the one of 1/3 or less.

  In the present invention, a common drive circuit is disposed on the display substrate at the end opposite to the end where the gate driver circuit is disposed, so that the drive capability of the common drive circuit is not reduced, and a symmetrical frame or narrowed frame is achieved. The effect that it is realizable is acquired.

It is a figure which shows the structure of the liquid crystal display substrate by the 1st Embodiment of this invention. It is a figure which shows the 1st structural example of the common drive circuit of FIG. 3 is a timing chart showing the operation of the common drive circuit of FIG. 2. FIG. 4 is a diagram illustrating a second configuration example of the common drive circuit in FIG. 1. FIG. 6 is a diagram illustrating a third configuration example of the common drive circuit in FIG. 1. It is a figure which shows the structure of the liquid crystal display substrate by the 2nd Embodiment of this invention. It is a figure which shows the structure of the common voltage generation circuit of FIG. FIG. 8 is a diagram illustrating an example in which the common drive circuit in FIG. 4 is combined with the common voltage generation circuit in FIG. 7. It is a figure which shows the structural example of the conventional liquid crystal display device. It is a figure which shows the structural example of the liquid crystal display device which integrated the conventional driver.

  Next, embodiments of the present invention will be described with reference to the drawings. First, an outline of the present invention will be described. That is, the display device drive circuit according to the present invention has a display unit in which a common drive circuit configured to supply a voltage to a common electrode from two common level power supply lines (VCOMH, VCOML) by a switch TFT is arranged in a matrix. Are integrated on the same substrate as the substrate on which is mounted.

  In the display device drive circuit of the present invention, the H level of the common inversion timing signal input to the gate of the switch TFT is set higher than the common voltage VCOMH, the L level is set lower than the common voltage VCOML, and the gate length of the TFT is increased. Two common level power supply amplitudes are set.

  When the gate driver is present on the same substrate as the pixels in the liquid crystal display device, the common drive circuit is disposed at the end opposite to the end where the gate driver is disposed and as close to the pad as possible. In addition, a pad in which a common drive circuit is disposed nearby is used as two common level pads. However, when the power supply circuit (common voltage generation circuit) is disposed on the same substrate, it is disposed near the common voltage generation circuit.

  A common voltage (VCOMH, VCOML) generation circuit suitable for the common drive circuit and easy to adjust the common voltage level is composed of a variable resistor (VR1) for adjusting a voltage difference between the common voltage VCOMH and the common voltage VCOML, and the common voltage VCOML. A variable resistor (VR2) for adjusting the level, four resistors (R11, R12, R21, R22), two operational amplifiers (A1, A2), and two capacitors (C1, C2) A constant voltage (Vref) is input. However, the total resistance value of the variable resistor VR1 is set to 1/3 or less than that of the resistor R11. Here, the capacitance values of the two capacitors C1 and C2 are made sufficiently larger (100 times or more) than the sum of the common electrode capacitances of the liquid crystal display device.

  A resistor R11 and a resistor R12 are connected in parallel to the inverting input terminal of the operational amplifier A1, the other end of the resistor R11 is connected to the variable portion of the variable resistor VR1, and the other end of the resistor R12 is connected to the output of the operational amplifier A1. Connected. The non-inverting input terminal of the operational amplifier A1 is connected to the variable part of the variable resistor VR2. Further, a capacitor C1 is connected to the output of the operational amplifier A1. This output outputs an H level common voltage VCOMH.

  A resistor R21 and a resistor R22 are connected in parallel to the inverting input terminal of the operational amplifier A2. The other end of the resistor R21 is connected to the constant voltage Vref, and the other end of the resistor R22 is connected to the output of the operational amplifier A2. Yes. The non-inverting input terminal of the operational amplifier A2 is connected to the variable part of the variable resistor VR2. Further, a capacitor C2 is connected to the output of the operational amplifier A2. This output outputs an L level common voltage VCOML. Both ends of the variable resistors VR1 and VR2 are connected to a constant voltage Vref and GND.

  Since the common drive circuit of the present invention has a simple switch configuration, the circuit area can be reduced. Further, the common drive circuit of the present invention applies the common voltages VCOMH and VCOML to the gate of the switch TFT in order to apply a voltage whose H level is higher than the common voltage VCOMH and whose L level is lower than the common voltage VCOML. As compared with the case, the ON resistance of the switch TFT can be lowered, and the gate width can be reduced.

  Furthermore, even if a high voltage is applied to the gate of the switch TFT, the voltage difference between the drain and source is the voltage difference between the common voltage VCOMH and the common voltage VCOML, so the gate length of the TFT is the common voltage VCOMH and the common voltage VCOML. It is possible to adjust to the voltage difference between. Therefore, the common drive circuit of the present invention can reduce the gate width of the switch TFT, and thus the circuit area can be reduced.

  When the gate driver is arranged on the same substrate as the liquid crystal display device, the common driving circuit of the present invention is arranged at the end opposite to the end where the gate driver is arranged, so that the width is about the same as the gate driver. The frame of the liquid crystal display panel can be made symmetrical. Further, when the common voltages VCOMH and VCOML are supplied from the input pad of the liquid crystal display device, the common driving circuit is arranged near the pad, and when the common voltage generating circuit is arranged on the same substrate, the common driving circuit is arranged. Is placed near the common voltage generation circuit, the wiring load can be suppressed, and the drive time of the common electrode by the common drive circuit can be shortened.

  In the common voltage generating circuit of the present invention, assuming that the resistance from the variable portion of the variable resistor to the constant voltage Vref is RA1, the resistor from the variable portion to GND is RB1, and the voltage of the variable resistor VR2 is V2, the variable resistor VR1 is variable. If the total resistance value (RA1 + RB1) of the variable resistor VR1 is equal to or less than 1/3 of the resistor R11, the voltage V1 of the section hardly depends on the resistors R11 and R12, and can be determined by the values of the resistors RA1 and RB1. .

  On the other hand, regarding the variable resistor VR2, the voltage V2 is not dependent on the resistors R21 and R22, but the resistor RA2 and RB2 depending on the values of the resistors RA2 and RB2, where RA2 is a resistor from the variable portion to the constant voltage Vref and RB2 is a resistor from the variable portion to GND. It becomes possible to decide. Here, since the common voltage VCOMH depends on the voltage V1 and the voltage V2, and the common voltage VCOML depends only on the voltage V2, in the common voltage generation circuit of the present invention, the common voltage difference Vsw (= VCOMH−VCOML) is a voltage. It is possible to adjust only by V1, that is, the variable resistor VR1, and the common voltage VCOML can be adjusted only by the variable resistor VR2.

  In general, in consideration of operating time, power consumption, and the like, the resistors R11, R12, R21, and R22 are about several MΩ, whereas the resistor (RA2 + RB2) is designed to be several MΩ to several tens MΩ, the same value or larger. Therefore, the resistance (RA1 + RB1) is at least 1/3 or less of the other resistances [resistance (RA2 + RB2) and resistances R11, R12, R21, R22]. 1/3 or less.

  Further, the common voltage generation circuit of the present invention includes capacitors C1 and C2 at the output, and since this capacitance value is sufficiently larger than all the common electrodes of the liquid crystal display device, it is considered that there is almost no influence of the voltage drop. .

  Furthermore, of the common voltage generation circuit, a capacitor and a resistor are provided outside the liquid crystal display device, and other parts of the common voltage generation circuit are integrated on the liquid crystal display device, and the common voltage generation circuit is located near the input pad of the liquid crystal display device. By arranging the common drive circuit near the common voltage generation circuit, there is almost no influence of wiring resistance, and the common electrode drive time by the common drive circuit is not affected.

  As described above, according to the present invention, the circuit is simple and the drive circuit is turned on by applying a voltage higher than the voltage applied between the drain and the source between the gate and the source of the switch TFT used in the drive circuit. Since the resistance is reduced and the gate length can be shortened, the gate area of the TFT can be reduced to reduce the circuit area, and the circuit area of the common drive circuit can be reduced.

  According to the present invention, a symmetrical frame can be realized by disposing a common drive circuit at an end opposite to an end where the gate driver is disposed on the liquid crystal display substrate. Further, the present invention is arranged near the pad when the common voltage is supplied from the pad, and close to the common voltage generation circuit when the common voltage is supplied from the common voltage generation circuit. It is possible to avoid a decrease in driving capability of the driving circuit. Furthermore, if the common drive circuit of the present invention is used, the circuit area can be reduced and the frame can be narrowed. Therefore, according to the present invention, when the common drive circuit is arranged on the liquid crystal display device substrate, it is possible to realize a symmetrical frame or narrow frame without reducing the drive capability of the common drive circuit.

  In the common voltage generation circuit of the present invention, the common voltage amplitude and the common voltage L level can be adjusted independently by a variable resistor, so that the common voltage level can be easily adjusted. In addition, since the output of the common voltage generation circuit of the present invention has a sufficiently large capacity compared to the capacitance value of the common electrode, voltage fluctuation hardly occurs even when the common drive circuit drives the common electrode. A voltage with high accuracy can be applied. Furthermore, when the common drive circuit and the common voltage generation circuit are arranged on the liquid crystal device substrate, the common drive circuit and the common voltage generation circuit are arranged close to each other, so that the common drive is not affected by the wiring load. Does not reduce the drive capability of the circuit.

  Therefore, according to the present invention, when the common drive circuit is arranged on the liquid crystal display device substrate, it is possible to realize a common voltage generation circuit in which the common voltage level can be easily adjusted without reducing the drive capability of the common drive circuit. . Note that the present invention can be applied not only to the liquid crystal display device described above but also to an active matrix display device having a large capacity load.

  Next, embodiments of the present invention will be described with reference to the drawings. Hereinafter, the present invention will be described using a liquid crystal display device, but the present invention can also be applied to a more general active matrix display device.

  FIG. 1 is a diagram showing a configuration of a liquid crystal display substrate according to a first embodiment of the present invention. In FIG. 1, a liquid crystal display unit 1 in which pixels are arranged in a matrix on a liquid crystal display substrate 10, a data driver circuit 2 that drives data lines of the liquid crystal display unit 1, and pixels in each line of the liquid crystal display unit 1. Driving the common electrode that is opposed to the gate driver circuit 3 that controls the switching of the pixel electrode and the liquid crystal layer of the liquid crystal display unit 1 (drives the common electrode of all the pixels of the liquid crystal display device at the same time). A drive circuit 4 is mounted, and a power supply circuit IC5 for supplying a voltage to the driver circuit and the drive circuit is provided outside.

  On the liquid crystal display substrate 10, a data driver circuit 2 and a gate driver circuit 3 for driving the liquid crystal display device are integrated together with the common drive circuit 4, and common voltages VCOMH and VCOML are applied from the outside through pads.

  The gate driver circuit 3 is disposed adjacent to one of the four ends of the liquid crystal display device. The common drive circuit 4 is disposed adjacent to the opposite end where the gate driver circuit 3 is disposed, and as close to the pad as possible so as to have the same width as the region of the gate driver circuit 3. Further, as a pad to which the common voltages VCOMH and VCOML are applied, a pad near the common drive circuit 4 is used.

  According to the present embodiment, the entire liquid crystal display device including the gate driver circuit 3 and the common drive circuit 4 can make the frame symmetric without creating a useless area. Furthermore, by arranging the common drive circuit 4 in the vicinity of the pad, the influence of the wiring resistance can be reduced, and the drive delay of the common electrode by the common drive circuit 4 can be suppressed.

  FIG. 2 is a diagram showing a first configuration example of the common drive circuit 4 of FIG. In FIG. 2, the common drive circuit 4 includes two common level power supply lines (VCOMH, VCOML), a common electrode in the liquid crystal display device, a common inversion timing signal line COMD, a Pch TFT (TFT: Thin Film Transistor) 41, and an Nch TFT 42. Yes.

  One end of the drain and source of the PchTFT 41 is connected to the H level common voltage VCOMH power line and the other end is connected to the common electrode. One end of the drain and source of the Nch TFT 42 is the L level common voltage VCOML power line and the other end is connected to the common electrode. Connected to the common electrode.

  The gates of the Pch TFT 41 and the Nch TFT 42 are connected to the common inversion timing signal line COMD, and the H level of COMD is made higher than VCOMH and the L level is made lower than VCOML.

  FIG. 3 is a timing chart showing the operation of the common drive circuit 4 of FIG. The operation of the common drive circuit 4 according to the first embodiment of the present invention will be described with reference to FIG. 2 and FIG.

  In this embodiment, the voltage difference between the gate and the source of the Pch TFT 41 and the Nch TFT 42 becomes larger than the VCOMH voltage and the VCOML voltage, and the ON resistance of the Pch TFT 41 and the Nch TFT 42 can be reduced.

  On the other hand, since only the VCOMH voltage and the VCOML voltage are applied between the drain and source of the Pch TFT 41 and the Nch TFT 42, the gate lengths of the Pch TFT 41 and the Nch TFT 42 can be shortened in accordance with two common level amplitudes.

  As described above, since the common drive circuit 4 according to the first embodiment of the present invention can reduce the gate widths of the Pch TFT 41 and the Nch TFT 42, the circuit area can be reduced.

  FIG. 4 is a diagram showing a second configuration example of the common drive circuit 4 of FIG. 4, the common drive circuit 4 has the same configuration as that of the first configuration example of the common drive circuit 4 shown in FIG. 2 except that a common inversion timing signal buffer 44 is provided.

  The input signal at the common inversion timing may have a driving capability comparable to that of a normal input signal. Also, by providing a level shift (LS) 43 before the common inversion timing signal buffer 44, the input signal at the common inversion timing can be set to a low voltage level.

  Furthermore, in the present embodiment, the common inversion signal applied to the gates of the Pch TFT 41 and the Nch TFT 42 can use the power source of the gate driver circuit 3 used in the liquid crystal display device. In this case, there is an advantage that it is not necessary to prepare a new voltage level for the common drive circuit.

  FIG. 5 is a diagram showing a third configuration example of the common drive circuit 4 of FIG. In FIG. 5, the common drive circuit 4 uses switches 45 and 46 of a CMOS (Complementary Metal Oxide Semiconductor) structure in which the Pch TFT and the Nch TFT are combined to form one switch instead of the Pch TFT 41 and the Nch TFT 42 in each of the above configuration examples. A common inversion timing signal buffer 47 is provided.

  In this case, since the switches 45 and 46 are controlled in timing by the common inversion timing signal and the inverted signal thereof, the common inversion timing signal and the inversion signal thereof are input from the outside, or the common inversion timing signal is input to the common through the inverter. An inverted signal of the inverted timing signal is generated.

  In the present embodiment, by adopting each of the above configuration examples as the common drive circuit 4, the circuit area can be suppressed and the frame can be narrowed. Further, the present embodiment is applicable to the case where the data driver circuit 2 is not integrated on the liquid crystal display substrate 10 or the case where other circuits are integrated.

  FIG. 6 is a diagram showing a configuration of a liquid crystal display substrate according to the second embodiment of the present invention. In FIG. 6, a display unit 1, a data driver circuit 2, a gate driver circuit 3, a common drive circuit 4, and a common voltage generation circuit 51 are mounted on a liquid crystal display substrate 10. A power supply circuit IC52 excluding a common voltage for supplying a voltage to the circuit is provided.

  On the liquid crystal display substrate 10, the data driver circuit 2 and the gate driver circuit 3 for driving the liquid crystal display device are integrated together with the common driving circuit 4 and the common voltage generating circuit 51, and common voltages VCOMH and VCOML are applied from the outside through the pads. Has been.

  The gate driver circuit 3 is arranged adjacent to one of the four ends of the liquid crystal display device. The common voltage generation circuit 51 is disposed adjacent to the pad at the opposite end where the gate driver circuit 3 is disposed, and is connected to the power supply, voltage, external resistance, and external capacitance used by the common voltage circuit 4. Uses a nearby pad on which the common voltage generation circuit 51 is disposed.

  The common drive circuit 4 is disposed adjacent to the opposite end where the gate driver circuit 3 is disposed, so as to have the same width as the region of the gate driver circuit 3 and adjacent to the common voltage generation circuit 51. .

  According to the present embodiment, the entire liquid crystal display device including the gate driver circuit 3, the common voltage generation circuit 51, and the common drive circuit 4 can make the frame symmetric without creating a useless area. In the present embodiment, the common voltage generation circuit 51 is arranged near the necessary pads, and the common drive circuit 4 is arranged near the common voltage generation circuit 51, thereby reducing the influence of the wiring resistance. Thus, the drive delay of the common electrode by the common drive circuit 4 can be suppressed.

  FIG. 7 is a diagram showing a configuration of the common voltage generation circuit 51 of FIG. In FIG. 7, the common drive circuit 4 and the common voltage generation circuit 51 are shown. As the configuration of the common drive circuit 4, each of the above configuration examples can be adopted.

  The common voltage generation circuit 51 is a circuit that generates a common voltage (VCOMH, VCOML), a variable resistor (VR1) that adjusts the voltage difference between the common voltage VCOMH and the common voltage VCOML, and a variable resistor that adjusts the level of VCOML ( VR2), four resistors (R11, R12, R21, R22), two operational amplifiers (A1, A2), and two capacitors (C1, C2), and an appropriate constant voltage (Vref) is input. And However, the total resistance value of the variable resistor VR1 is 1/3 or less than that of the resistor R11, and the capacitance values of the two capacitors C1 and C2 are made 100 times or more larger than the total common electrode capacitance value of the liquid crystal display device.

  Resistors R11 and R12 are connected in parallel to the inverting input terminal of the operational amplifier A1, the other end of the resistor R11 is connected to the variable part of the variable resistor VR1, and the other end of the resistor R12 is connected to the output of the operational amplifier A1. ing. The non-inverting input terminal of the operational amplifier A1 is connected to the variable part of the variable resistor VR2, and the capacitor C1 is connected to the output of the operational amplifier A1. This output outputs the common voltage VCOMH.

  Resistors R21 and R22 are connected in parallel to the inverting input terminal of the operational amplifier A2, the other end of the resistor R21 is connected to the constant voltage Vref, and the other end of the resistor R22 is connected to the output of the operational amplifier A2. The non-inverting input terminal of the operational amplifier A2 is connected to the variable part of the variable resistor VR2, and the capacitor C2 is connected to the output of the operational amplifier A2. This output outputs a common voltage VCOML. Both ends of the variable resistors VR1 and VR2 are connected to a constant voltage Vref and GND.

In the common voltage generating circuit 51 according to the present embodiment, the voltage V1 of the variable part of the variable resistor VR1 is RA1 as the resistance from the variable part of the variable resistor VR1 to the constant voltage Vref, and RB1 as the resistance from the variable part to GND. When the voltage of the variable part of VR2 is V2,
V1 = Vref × R11 × RB1
/ (R11 × RA1 + R11 × RB1 + RA1 × RB1)
+ V2 × RA1 × RB1
/ (R11 × RA1 + R11 × RB1 + RA1 × RB1)
... (1)
It is expressed as follows.

If the total resistance value (RA1 + RB1) of the variable resistor VR1 is 1/3 or less than the resistor R11, the second term on the right side of the equation (1) can be almost ignored as compared with the first term, and the equation (1) Because the third term in the denominator of the first term on the right side of can be ignored compared to the first and second terms,
V1≈Vref × RB1 / (RA1 + RB1) (2)
It is expressed as follows.

Also, regarding the variable resistor VR2, if the resistor from the variable portion to the constant voltage Vref is RA2, and the resistor from the variable portion to GND is RB2,
V2 = Vref × RB2 / (RA2 + RB2) (3)
It becomes.

On the other hand, the common voltages VCOMH and VCOML are
VCOMH = V2 × (R11 + R12)
/ R11−V1 × R12 / R11 (4)
VCOML = V2 × (R21 + R22)
/ R21−Vref × R22 / R21 (5)
It is expressed as follows.

Here, when the resistance values of the resistors R11 and R21 are equal and the resistance values of the resistors R12 and R22 are equal, the common voltage difference Vsw (= VCOMH−VCOML) is
Vsw = (Vref−V1) × R12 / R11 (6)
It is expressed.

  Therefore, the common voltage generation circuit 51 according to the present embodiment can adjust the common voltage difference Vsw only by the voltage V1, that is, the variable resistor VR1, and can adjust the common voltage VCOML only by the variable resistor VR2.

  Further, the common voltage generation circuit 51 according to the present embodiment includes capacitors C1 and C2 at the output. If these capacitance values are sufficiently larger than all the common electrodes of the liquid crystal display device, the output of the common voltage generation circuit 51 is provided. It is considered that there is almost no resistance and does not affect the drive time in the common drive circuit 4.

  FIG. 8 is a diagram showing an example in which the common drive circuit 4 of FIG. 4 is combined with the common voltage generation circuit 51 of FIG. Note that the example shown in FIG. 8 is merely an example, and it is possible to combine other common drive circuits. In the present embodiment, the voltages applied to both ends of the variable resistors VR1 and VR2 are the constant voltages Vref and GND. However, an appropriate constant voltage may be used as these voltages.

  As described above, in this embodiment, the circuit area is reduced by adopting each configuration example of the first embodiment of the present invention shown in FIGS. 2, 4, and 5 as the common drive circuit 4. And a narrow frame can be achieved.

  In this embodiment, the configuration example shown in FIG. 7 is adopted as the common voltage generation circuit 51, and the resistors and capacitors used in the configuration example are connected to the outside of the substrate of the liquid crystal display device through the input pads. A liquid crystal display device in which the gate driver circuit 3, the common drive circuit 4, and the common voltage generation circuit 51, in which there is no useless area, the frame is symmetrical, and the common voltage level can be easily adjusted, can be realized. . Furthermore, the present embodiment is applicable to the case where the data driver circuit 2 is not integrated on the liquid crystal display substrate 10 or other circuits are integrated, for example.

  As described above, in the present invention, the circuit is simple and the common driving is performed by applying a voltage higher than the voltage applied between the drain and the source between the gate and the source of the switch TFT used in the common driving circuit 4. The ON resistance of the circuit 4 is reduced, and the gate length can be shortened. Therefore, in the present invention, the gate width of the TFT can be reduced and the circuit area can be reduced, so that the circuit area of the common drive circuit 4 can be reduced.

  In the present invention, a symmetrical frame can be realized by disposing the common drive circuit 4 on the liquid crystal display substrate 10 at the end opposite to the end where the gate driver circuit 3 is disposed. In this case, according to the present invention, when the common voltage is supplied from the pad, it is arranged near the pad, and when the common voltage is supplied from the common voltage generation circuit 51, it is arranged near the common voltage generation circuit 51. It is possible to avoid a decrease in the driving capability of the common driving circuit 4 due to the above.

  Therefore, in the present invention, if the common drive circuit 4 having the above configuration is used, the circuit area can be reduced and the frame can be narrowed. Therefore, when the common drive circuit 4 is arranged on the liquid crystal display substrate 10, A symmetrical frame and narrow frame can be realized without reducing the drive capability of the common drive circuit 4.

  Furthermore, according to the present invention, the common voltage generation circuit 51 can independently adjust the common voltage amplitude and the common voltage L level with a variable resistor, so that the common voltage level can be easily adjusted. Since the output of the common voltage generation circuit 51 is connected with a capacitance sufficiently larger than the capacitance value of the common electrode, voltage fluctuation hardly occurs even when the common drive circuit 4 drives the common electrode, and the accuracy is improved. A high voltage can be applied.

  When the common drive circuit 4 and the common voltage generation circuit 51 are arranged on the liquid crystal display substrate 10, by arranging the common drive circuit 4 and the common voltage generation circuit 51 close to each other, the wiring load is not affected, The drive capability of the common drive circuit 4 is not reduced. Therefore, in the present invention, when the common drive circuit 4 is disposed on the liquid crystal display substrate 10, the common voltage generation circuit 51 that can easily adjust the common voltage level without reducing the drive capability of the common drive circuit 4 is realized. Can do. In the present invention, the same effects as those described above can be obtained with a more general active matrix display device having the same structure as described above.

1 Display section
2 Data driver circuit
3 Gate driver circuit
4 Common drive circuit
5 Power circuit IC
10 Liquid crystal display substrate 41 Pch TFT
42 Nch TFT
43 Level shift 44, 47 Common inversion timing signal buffer 45, 46 Switch 51 Common voltage generation circuit 52 Power supply circuit IC excluding common voltage

Claims (17)

A display device driving circuit that simultaneously drives a capacitive load in a display device in which a gate driver circuit that controls switching of pixels of each line of the display portion is integrated on the same substrate as the substrate on which the display portion is mounted. A voltage generation circuit for generating a supply voltage,
Arranged together with the display device drive circuit at a position facing the gate driver circuit across the display unit,
A first variable resistor for adjusting a voltage difference between a high level of the supply voltage and a low level of the supply voltage ;
A second variable resistor for adjusting a low level of the supply voltage ;
The variable portion of the first variable resistor is connected to the inverting input through the first resistor, one end of the second resistor is connected to the inverting input, and the other end of the second resistor is connected to the output, A first operational amplifier in which one end of a first capacitor is connected to the output, the other end is connected to a constant voltage, and a variable part of the second variable resistor is connected to a non-inverting input;
A constant voltage source is connected to the inverting input through a third resistor, one end of the fourth resistor is connected to the inverting input, the other end of the fourth resistor is connected to the output, and one end of the second capacitor Is connected to the output, the other end is connected to a constant voltage, and the variable part of the second variable resistor includes a second operational amplifier connected to a non-inverting input,
The first operational amplifier outputs a high level of the supply voltage, the second operational amplifier outputs a low level of the supply voltage;
The total resistance of the first variable resistor is 1/3 of the first resistor, and the total resistance of the second variable resistor and the first to fourth resistors on the same substrate voltage generating circuit, characterized in that the one of 1/3 or less. 2. The circuit according to claim 1 , wherein at least one of a resistor and a capacitor among circuit elements of the self circuit is disposed outside the substrate, and the resistor and the capacitor are connected through an input pad of the display unit. Voltage generator circuit. The display device drive circuit is a display device drive circuit that simultaneously drives a capacitive load in the display unit, and is disposed at a position facing the gate driver circuit across the display unit. The voltage generation circuit according to claim 1 or 2. The display device driving circuit includes a first voltage source, one or more first transistors connected to one of a drain and a source terminal, and a first voltage source that supplies a voltage lower than that of the first voltage source. Two voltage sources and one or more second transistors connected to either the drain or the source end,
One or more signal lines for transmitting signals having a high level equal to or higher than the voltage of the first voltage source and a low level equal to or lower than the voltage of the second voltage source to the gate ends of the first and second transistors. Connected to
4. The voltage according to claim 3, wherein both ends of the first and second transistors that are not connected to the first and second voltage sources are connected to a capacitive load in the display device. Generation circuit. In the display device driving circuit, the first transistor is a P-type transistor, the second transistor is an N-type transistor, and the gate ends of the first and second transistors are a common signal line. The voltage generation circuit according to claim 4, wherein the voltage generation circuit is connected to the voltage generation circuit. In the display device driving circuit, a P-type transistor and an N-type transistor are connected in parallel to form the first transistor, and an N-type transistor and a P-type transistor are connected in parallel to form the second transistor. A gate of each of the P-type transistor of the first transistor and the N-type transistor of the second transistor is connected to one signal line, and the N-type transistor of the first transistor and the second transistor 6. The voltage generation circuit according to claim 5, wherein the gate of each of the P-type transistors is connected to an inverted signal line of one signal line. In the display device driving circuit, the signal lines and the inverted signal lines of the signal lines have a high level power supply voltage of the gate driver and a low level power supply voltage of the gate driver. The voltage generation circuit according to claim 4, wherein: 8. The voltage generation circuit according to claim 4, wherein in the display device driving circuit, the transistors are all formed of thin film transistors. 9. A display device in which a gate driver circuit for controlling switching of pixels of each line of the display unit is integrated on the same substrate as the substrate on which the display unit is mounted,
Positions facing the gate driver circuit across the display unit between a display device drive circuit that simultaneously drives a capacitive load in the display unit and a voltage generation circuit that generates a supply voltage to the display device drive circuit Placed in
A first variable resistor for adjusting a voltage difference between a high level of the supply voltage and a low level of the supply voltage ;
A second variable resistor for adjusting a low level of the supply voltage ;
The variable portion of the first variable resistor is connected to the inverting input through the first resistor, one end of the second resistor is connected to the inverting input, and the other end of the second resistor is connected to the output, A first operational amplifier in which one end of a first capacitor is connected to the output, the other end is connected to a constant voltage, and a variable part of the second variable resistor is connected to a non-inverting input;
A constant voltage source is connected to the inverting input through a third resistor, one end of the fourth resistor is connected to the inverting input, the other end of the fourth resistor is connected to the output, and one end of the second capacitor Is connected to the output, the other end is connected to a constant voltage, and the voltage generating circuit includes a second operational amplifier in which the variable portion of the second variable resistor is connected to a non-inverting input,
The first operational amplifier outputs a high level of the supply voltage, the second operational amplifier outputs a low level of the supply voltage;
The total resistance of the first variable resistor is 1/3 of the first resistor, and the total resistance of the second variable resistor and the first to fourth resistors on the same substrate display device being characterized in that the one of 1/3 or less. The at least one of a resistor and a capacitor among circuit elements of the voltage generating circuit is disposed outside the substrate, and the resistor and the capacitor are connected through an input pad of the display unit. 9. The display device according to 9. The display device drive circuit is a display device drive circuit that simultaneously drives a capacitive load in the display unit, and is disposed at a position facing the gate driver circuit across the display unit. The display device according to claim 9 or 10. The display device driving circuit includes a first voltage source, one or more first transistors connected to one of a drain and a source terminal, and a first voltage source that supplies a voltage lower than that of the first voltage source. Two voltage sources and one or more second transistors connected to either the drain or the source end,
One or more signal lines for transmitting signals having a high level equal to or higher than the voltage of the first voltage source and a low level equal to or lower than the voltage of the second voltage source to the gate ends of the first and second transistors. Connected to
12. The display device according to claim 11, wherein both ends of the first and second transistors not connected to the first and second voltage sources are connected to a capacitive load in the display unit. . In the display device driving circuit, the first transistor is a P-type transistor, the second transistor is an N-type transistor, and the gate ends of the first and second transistors are a common signal line. The display device according to claim 12, wherein the display device is connected to the display device. In the display device driving circuit, a P-type transistor and an N-type transistor are connected in parallel to form the first transistor, and an N-type transistor and a P-type transistor are connected in parallel to form the second transistor. A gate of each of the P-type transistor of the first transistor and the N-type transistor of the second transistor is connected to one signal line, and the N-type transistor of the first transistor and the second transistor 13. The display device according to claim 12, wherein the gate of each of the P-type transistors is connected to an inverted signal line of one signal line. In the display device driving circuit, the signal lines and the inverted signal lines of the signal lines have a high level power supply voltage of the gate driver and a low level power supply voltage of the gate driver. The display device according to claim 12, wherein the display device is a display device. 16. The display device according to claim 12, wherein in the display device drive circuit, all of the transistors are formed of thin film transistors. The display device according to claim 9, wherein a transistor in the voltage generation circuit includes a thin film transistor.

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