JPH11288255A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the degradation of the picture quality due to distortion of a counter electrode voltage dependent upon display data. SOLUTION: The total of display data values in every line is detected to determine a correction quantity by an interface circuit 102, and a correction voltage value is added to or subtracted from the counter electrode voltage value applied to a counter electrode in accordance with the detected correction quantity by a power supply circuit 106. Thus, the degradation of the picture quality due to voltage distortion of the counter electrode voltage dependent upon display data and a compensation voltage is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display, and more particularly to a technique for displaying a high quality image using a low voltage driving circuit.

[0002]

2. Description of the Related Art FIG. 16 shows a configuration of a conventional liquid crystal display device.

In FIG. 1, reference numeral 201 denotes an interface signal including a display signal and a synchronization signal transferred from a system (not shown) using a liquid crystal display. 202
Is an interface circuit for generating display data and control signals for driving the liquid crystal display. 203
Is a signal drive circuit that generates a gray scale voltage corresponding to display data. A scan driving circuit 204 sequentially selects scan lines. Reference numeral 205 denotes a liquid crystal panel that performs display corresponding to input display data. 206 is a power supply circuit.

Hereinafter, signals generated by the interface circuit 202 will be described.

Reference numeral 207 denotes a control signal for the signal drive circuit 203, which includes display data and a synchronization signal. 208 is
This is a control signal for the scan drive circuit 204,
At 04, a timing signal for sequentially selecting a scanning line is included. Reference numeral 209 denotes an alternating signal “M” to be transferred to the power supply circuit 206.

Next, a signal generated by the power supply circuit 206 will be described.

Reference numeral 210 denotes a gray scale voltage reference signal to be transferred to the signal drive circuit 203. The signal serves as a reference for the gray scale voltage transferred to the liquid crystal panel 205 by the signal drive circuit 203. 211 is the scan driving circuit 204
Is a scanning voltage reference signal to be transferred to the scanning drive circuit 204. Based on this signal, the scanning driving circuit 204 transfers a voltage serving as a reference of a selection voltage to be output to the scanning line. Reference numeral 212 denotes a voltage signal supplied to a counter electrode connected to the liquid crystal of the liquid crystal panel 205.
Reference numeral 13 denotes a voltage signal supplied to a compensation electrode connected to the compensation capacitance of the liquid crystal panel 205.

Next, the signal 21 output from the signal driving circuit 203
Reference numeral 4 denotes a signal line group for transferring a gray scale voltage corresponding to the display data generated by the signal drive circuit 203. Reference numeral 215 output by the scan drive circuit 204 denotes a scan line for transferring a selection voltage for sequentially selecting display lines. Group.

Reference numeral 216 denotes a pixel portion which forms the liquid crystal panel 205. 217 of the pixel portion 216 is a thin film transistor (Thin Film) which is a switching element.
Transistor, hereafter called TFT. ), 218 is a liquid crystal, and 219 is a compensation capacitance.

The liquid crystal panel 205 has a matrix of pixel sections 216, and each pixel section 216 has a signal line group 214.
And the scanning line group 215. LCD panel 2
05 is the number of pixel units 2 in the horizontal and vertical directions corresponding to the resolution.
Sixteen. In general, in the case of a liquid crystal display of a color display, one pixel is composed of three primary colors of red, green, and blue. When each color pixel portion is arranged in the horizontal direction, the number of pixels in the horizontal direction is three times the resolution. Is the number of Further, the pixel units 216 arranged in the horizontal direction share one scanning line of the scanning line group 215, and the pixel units 217 arranged in the vertical direction.
In general, one of the signal line groups 214 shares one signal line.

Hereinafter, the operation of such a liquid crystal display will be described.

The display data and the synchronization signal transferred by the interface signal 201 are input to the interface circuit 202. In the interface circuit 202, a control signal 207 is sent to the signal drive circuit 203 and the scan drive circuit 20
4 to generate a control signal 208 and a power supply circuit 206 to generate and output a liquid crystal alternating signal 209.

In the signal driving circuit 203, the control signal 207
The display data for one horizontal line is sequentially fetched using the display data and the synchronization signal transferred in step 1, and when the display data for one horizontal line has been fetched, the gradation corresponding to the fetched display data for one horizontal line is obtained. Apply voltage to signal line group 2
14 are output simultaneously. The signal drive circuit 203 keeps outputting the grayscale voltage for one horizontal line during one horizontal period.
During this time, the signal drive circuit 203 performs the operation of sequentially taking in the display data of the next horizontal line in parallel. Therefore, the main voltage corresponding to the display data output from the interface circuit 202 is output to the liquid crystal panel 205 during the next horizontal period.

The above-described operation is repeatedly performed by the signal drive circuit 203 to output a gray scale voltage corresponding to display data for one frame, that is, one screen, to the liquid crystal panel 205.

Here, the gray scale voltage output from the signal drive circuit 203 is generated based on the gray scale voltage reference signal 210. Generally, in the grayscale voltage reference signal 210, a plurality of levels of voltages from a black display voltage to a white display voltage are transferred.

Next, the scanning drive circuit 204 applies a selection voltage to the scanning lines 215 sequentially from the first line in synchronization with the control signal 208. At this time, the TFT 2 of each pixel portion 216
17 is in a selected state when a selection voltage is applied, and applies a gradation voltage transferred from the signal line group 214 to the liquid crystal 218 and the compensation capacitor 219. Then, when the non-selection voltage is applied to the scanning line 215, the liquid crystal 218 and the compensation capacitor 219 hold the applied voltage until the scanning line 215 is brought into the next selection state.

As described above, in the liquid crystal display, gradation control is realized by controlling line-sequential scanning and controlling the amount of light transmitted at the voltage level of the effective voltage value applied to the liquid crystal 218.

Here, in FIG. 17, G1 is a driving waveform of a scanning line for driving the first line in the scanning line group 215, Vgon indicates a selection voltage level, and Vgof
f indicates a non-selection voltage level. Similarly, G2 is a driving waveform of a scanning line for driving the second line.

Vcom is a driving waveform of the counter electrode 213, VcomP is a positive voltage level, and
comN is a negative voltage level. Vd indicates a gradation voltage of one signal line of the signal line group 214. When the voltage is on the negative side with respect to the common electrode voltage Vcom, a negative voltage is applied to the pixel 217. When the pixel 217 is on the positive polarity side, a positive voltage is applied to the pixel 217. The liquid crystal 218 operates so that the luminance changes depending on the potential difference between the common electrode voltage Vcom and the gradation voltage Vd.

The compensation capacitor 219 shown in FIG. 16 is generally provided to prevent the voltage applied to the liquid crystal 218 from causing a current leak during the holding period, thereby making the holding voltage unstable. Specifically, the drive voltage of the compensation electrode 213 connected to the compensation capacitor 219 is similar to the drive voltage waveform of the common voltage Vcom of the liquid crystal 218. Therefore,
Hereinafter, description of the drive voltage of the compensation electrode 213 will be omitted.

In FIG. 17, when the selection voltage Vgon is applied to the scanning line G1, the TFT 217 is turned on.
In this state, the gray scale voltage Vd transferred through the signal line 214 is applied to the liquid crystal 218 of the pixel portion 216. When the non-selection voltage Vgoff is applied to the scanning line G1, the TFT 217 is turned off at this timing, and the liquid crystal 218 is turned off.
Holds that voltage.

In FIG. 17, the selection voltage Vgo is applied to the scanning line G1.
At the timing when n is applied, the voltage applied to the liquid crystal is a positive voltage because the voltage level of the counter electrode 212 is VcomN and negative. Similarly, at the timing when the selection voltage Vgon is applied to the scanning line G2, the counter electrode 2
Since the voltage level of No. 12 is VcomP and the polarity is positive, the voltage applied to the liquid crystal is a negative voltage.

Here, as described above, the voltage level of the counter electrode 212 is changed for each line between the positive VcomP and the negative VcomP.
com, and the alternating drive for each line, in which positive and negative gradation voltages are alternately applied for each line, is performed because of the polarity of the gradation voltage applied to the entire screen. This is to prevent the occurrence of a flicker phenomenon called flicker when one side is biased to one side.

The liquid crystal is one frame (about 60 Hz).
Since it is necessary to apply an AC voltage in a cycle, in a line corresponding to each scanning line group 215, a voltage having a polarity opposite to that of the voltage applied in the previous frame is applied at the timing of applying the voltage in the next frame. Alternating drive is also performed for each frame.

Here, when the voltage level of the counter electrode 212 is fixed, a signal drive circuit having a dynamic range twice as large as the gradation voltage Vd is required to perform AC driving. By converting the counter voltage Vcom of the counter electrode 212 into an alternating current as shown in FIG.
That is, the signal drive circuit can use a dynamic range in which a grayscale voltage of one polarity can be generated.

[0026]

According to the above-mentioned conventional liquid crystal display, the intermediate luminance is displayed on the entire screen as shown in FIG. This shows a phenomenon in which the middle luminance of the left and right display areas of the mold is higher than the middle luminance of the other areas.

Also, as shown in FIG. 18B, this is an example where the intermediate luminance is displayed on the entire screen and a white rectangular is displayed at the center. Shows a phenomenon that the luminance is reduced with respect to the intermediate luminance in the other areas.

The cause of this phenomenon will be described with reference to FIGS.

FIG. 19 shows a current path when the voltage applied to each pixel on the line selected by the scanning line G1 has a positive polarity, and includes a counter electrode 212 and a compensation electrode 213.
Indicates that the current from all the pixel portions is concentrated on the counter electrode 212 and the compensation electrode 213 because the pixels are common to all the pixels.

In FIG. 20, CL1 is a horizontal synchronizing signal, which is enabled once in one horizontal period, and is used to convert grayscale display data for one horizontal line into grayscale voltages and output them. Signal. M is a liquid crystal alternating signal. When the liquid crystal alternating signal M is at a “low” level, the power supply circuit 206 sets the counter electrode voltage Vcom to a negative polarity and outputs a “high”.
At the time of the level, control is performed such that the common electrode voltage Vcom has a positive polarity.

Vda is a simplified (reduced number of lines) description of the gradation voltage waveform on the signal line corresponding to Da in FIG. 3 (a), and Vdb is FIG.
7A is a simplified (shown with a reduced number of lines) grayscale voltage waveform on a signal line corresponding to Db in FIG.

Further, with respect to the counter voltage Vcom in FIG. 20, a solid line (VcomA) is a waveform diagram of the counter electrode line 212 at the output end of the power supply circuit 206 described above.
(mB) is a waveform diagram of the counter voltage Vcom inside the liquid crystal panel 205.

In FIG. 19, since the counter electrode 212 and the compensation electrode 213 are common to each pixel, current from all pixel portions concentrates on the counter electrode 212 and the compensation electrode 213. When this current is concentrated, the opposite electrode 2
Voltage distortion occurs in the counter voltage and the compensation voltage due to a load such as 12 and the resistance (not shown) of the compensation electrode 213.

This voltage distortion is as shown in FIG. That is, during the periods of tH1 and tH2 (the lines above the black rectangular region in FIG. * 3 (a)) and tH5 (the lines below the black rectangular region in FIG. * 3 (a)), the gradation voltage Is constant in the horizontal direction like Vda and Vdb (grayscale voltage of the intermediate voltage level), and the common electrode voltage is VcomB
However, during the period of tH3 and tH4 (both are lines including pixels in the black rectangular region in FIG. 3A), Vda
In order to perform black display, the amount of current concentrated on the common electrode 212 and the compensation electrode 213 increases, so that the common voltage VcomB inside the liquid crystal panel 205 does not reach the desired voltage level of the common voltage VcomA, and ΔV
com, the counter voltage Vcom decreases.

As a result, the effective voltage value applied to the liquid crystal obtained at tH3 and tH4 becomes Vdrms-ΔVcom with respect to the original Vdrms. Since the luminance displayed on the liquid crystal display is controlled by the effective voltage value applied to the liquid crystal 218, if the desired effective voltage value cannot be obtained, the display luminance changes and the left and right luminances of the black rectangular area are different. The result is a relatively increase with respect to the halftone luminance in the region of FIG.

On the other hand, as shown in FIG. 18B, when a white rectangular area is provided, the amount of current concentrated only on the lines including the pixels in the white rectangular area is reduced, so that the effective voltage value applied to the liquid crystal is reduced. However, since the luminance increases compared to the line not including the white rectangular area, a phenomenon occurs in which the luminance is relatively low on the left and right sides of the white rectangular area.

As described above, in the conventional liquid crystal display,
According to the display data, the counter electrode 212 and the compensation electrode 21
As the amount of current concentrated on No. 3 increases / decreases, and the amount of voltage distortion of the common electrode voltage and the compensation electrode voltage fluctuates, image quality has deteriorated.

Accordingly, an object of the present invention is to improve image quality deterioration due to voltage distortion of the common electrode voltage and the compensation electrode voltage depending on display data.

[0039]

In order to achieve the above object,
The present invention includes, for example, a plurality of liquid crystal cells arranged in a matrix, a scanning electrode provided for each horizontal line of the matrix, a driving electrode provided for each vertical line of the matrix, and a counter electrode. Each of the liquid crystal cells has a scanning electrode of a horizontal line to which the liquid crystal cell belongs, and a driving electrode of a vertical line to which the liquid crystal cell belongs,
Connected to the counter electrode, during the period when the voltage supplied to the connected scanning electrode was the selection voltage, the effective voltage with respect to the counter electrode voltage of the gray scale voltage supplied from the connected driving electrode,
A liquid crystal panel that holds when the voltage supplied to the connected scanning electrode changes from the selection voltage to the non-selection voltage and exhibits a concentration according to the held voltage, and a power supply circuit that generates the counter electrode voltage, A scan drive circuit for selecting each horizontal line, applying a selection voltage to scan electrodes of the selected horizontal line, and applying a non-selection voltage to scan electrodes of horizontal lines other than the selected scan electrode; The display data of each pixel of the display line corresponding to the horizontal line to which a voltage is applied is input, and the gray scale voltage corresponding to the input display data of each pixel is set to each vertical line to which the liquid crystal cell corresponding to each pixel belongs. And a driving circuit for applying the driving electrode to each of the driving electrodes, wherein, for each of the horizontal lines, the magnitude of the sum of the values of the display data of the pixels of the display line corresponding to the horizontal line is large. And a correction amount generation unit that calculates the correction amount of the horizontal line as the correction amount of the horizontal line. The power supply circuit selects the scan electrode of the horizontal line according to the correction amount of each horizontal line calculated by the correction amount generation unit. The voltage level of the common electrode voltage is set such that the effective voltage with respect to the common electrode voltage of the gradation voltage supplied from the driving electrode during the period in which the voltage is applied is a specified level according to the value of the display data. A liquid crystal display device characterized by correcting the following.

According to such a liquid crystal display device, the effect on the effective voltage due to the distortion of the common electrode voltage depending on the display data is canceled by correcting the common electrode voltage according to the display data, so that the image quality is improved. Display can be realized.

[0041]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the liquid crystal display according to the present invention will be described.

First, the first embodiment will be described.

FIG. 1 shows the configuration of the liquid crystal display according to the first embodiment.

In the figure, reference numeral 101 denotes an interface signal including a display data and a synchronization signal transferred from a system (not shown) using the present liquid crystal display. 10
An interface circuit 2 generates display data for driving the liquid crystal display and a control signal. 103
Is a signal drive circuit that generates a gray scale voltage corresponding to display data. A scanning drive circuit 104 sequentially selects scanning lines. Reference numeral 105 denotes a liquid crystal panel on which a display corresponding to the display data is performed. 1
06 is a power supply circuit.

Here, 107 of the control signals generated by the interface circuit 102 are control signals for the signal drive circuit 103, and include display data and control signals. 1
Reference numeral 08 denotes a control signal for the scan drive circuit 104, which transfers a timing signal to sequentially select scan lines.
Reference numeral 109 denotes an alternating signal “M” to be transferred to the power supply circuit 106.
And 110 is a control signal for transferring the voltage correction amount.

Next, among the voltage signals generated by the power supply circuit 106, reference numeral 111 is a gray scale voltage reference signal to be transferred to the signal drive circuit 103.
Transfers a reference voltage of a gray scale voltage corresponding to the display data to be transferred to the liquid crystal panel 105. Reference numeral 112 denotes a scan voltage reference signal to be transferred to the scan drive circuit 104, and this signal transfers a reference voltage of a selection signal output by the scan drive circuit 104 to sequentially select lines. 11
Reference numeral 3 denotes a voltage signal supplied to a counter electrode of the liquid crystal 105 connected to the liquid crystal, and reference numeral 114 denotes a voltage signal supplied to a compensation electrode connected to the additional capacitance of the liquid crystal panel 105.

Next, a signal 115 output from the signal driving circuit 103 is a group of signal lines for transferring a gray scale voltage corresponding to display data.
Reference numeral 6 denotes a group of scanning lines for transferring a scanning voltage for selecting or unselecting a scanning line.

Reference numeral 117 denotes a pixel portion constituting the liquid crystal panel 105; and 118, a thin film transistor (Thin Film Transistor) serving as a switching element.
ster, hereinafter referred to as TFT. ) And 119 is
Reference numeral 120 denotes a liquid crystal, and reference numeral 120 denotes a compensation capacitance.

Next, in this embodiment, the configuration of the correction amount data generating circuit provided in the interface circuit 102 is shown in FIG.

In the figure, reference numerals 701, 702, 703 denote counters with a load function, 704, 705, 706 denote data buses output from the counters 701, 702, 703, respectively, and 707, 708, 709 denote latch circuits. 710, 711, and 712 are latch circuits 707,
Data buses 708 and 709 are output, and 713 is an addition circuit. RD7: 0 is red display data, GD7: 0 is green display data, and BD7: 0
Is blue display data, DCLK is a clock synchronized with each of the above display data, HSYNC is a horizontal synchronization signal, VSYNC is a vertical synchronization signal, and both of these signals are shown in FIG. Interface signal 10
1 included.

Next, FIG. 3 shows a configuration of a common electrode voltage correction circuit provided in the power supply circuit 106 in this embodiment.

In the figure, 801 and 802 are digital / analog conversion circuits, and 803 and 804 are digital / analog converters, respectively.
The correction voltages output from the analog conversion circuits 801 and 802, 805, 806, and 807 are resistors for voltage division, 808 is a reference electrode reference voltage of positive polarity, and 8
09 is a negative reference electrode reference voltage, and 810 is
811 is an analog subtraction circuit; 812 is an output voltage of the analog addition circuit 810; 813 is an output voltage of the analog subtraction circuit 811; 814 is a voltage selection circuit; 815 is an output voltage of the voltage selection circuit 814, and 816 is a current amplification circuit.

Hereinafter, the operation of the liquid crystal display according to this embodiment will be described.

The display data and the synchronization signal transferred by the interface signal 101 are input to the interface circuit 102. The interface circuit 102 includes a control signal 107 for controlling the signal drive circuit 103, a scan drive circuit 104
, A liquid crystal alternating signal 109 for controlling the power supply circuit 106, and a control signal 110.

The signal drive circuit 103 sequentially takes in the display data for one horizontal line, and when it finishes taking in the display data for one horizontal line, outputs the gradation voltage corresponding to the taken-in display data for one horizontal line to the signal line. A group 114 outputs one horizontal line at a time. The signal drive circuit 103 keeps outputting the grayscale voltage for one horizontal line during one horizontal period. In addition, during this time, the signal driving circuit 103 performs an operation of sequentially acquiring display data of the next horizontal line in parallel.
That is, the gray scale voltage corresponding to the display data output by the interface circuit 102 is output to the liquid crystal panel 105 during the next horizontal period. The signal driving circuit 103 repeatedly performs such an operation, and outputs a gradation voltage corresponding to display data for one frame, that is, one screen, to the liquid crystal panel 105.
Output to Here, the gray scale voltage output from the signal drive circuit 103 is generated based on the voltage transferred by the gray scale voltage reference signal 111. Generally, the gradation voltage reference signal 1
In 11, a plurality of levels of voltages from a black display voltage to a white display voltage are transferred as the reference voltage of the gradation voltage.

Next, the scanning drive circuit 104 controls the control signal 1
A selection voltage is applied to the scanning lines 116 sequentially from the first line in synchronization with 08. At this time, the TFT 10 of each pixel unit 107
8 is in a selected state when a selection voltage is applied, and applies a gradation voltage transferred from the signal line group 115 to the liquid crystal 119 and the compensation capacitor 120. Then, when the non-selection voltage is applied to the scanning line 116, the liquid crystal 119 and the compensation capacitor 120 hold the applied voltage until the scanning line 116 becomes the next selected state. As described above, in the liquid crystal display, gradation control is performed by performing line-sequential scanning of the matrix of the pixel portion 117 and controlling the amount of light transmitted at the voltage level applied to the liquid crystal 119.

The basic operation up to this point is the same as that of the above-described conventional liquid crystal display. Here, in the liquid crystal display according to the present embodiment, the grayscale voltage applied to the liquid crystal panel and the driving waveform of the counter electrode are shown in FIG.

In the figure, CL1 is a horizontal synchronizing signal, which becomes effective once per horizontal period, and serves as a timing signal for converting gray scale display data for one horizontal line into a gray scale voltage and outputting it. . M is a liquid crystal alternating signal, and the power supply circuit 10
6 controls the counter electrode voltage Vcom to have a negative polarity when the liquid crystal alternating signal is at a "low" level, and to make the counter electrode voltage Vcom have a positive polarity when the liquid crystal alternating signal is at a "high" level. Vdc is t
A gray scale voltage for performing halftone display at H1, tH2, and tH5,
7 is a gray scale voltage waveform of a signal line that outputs a gray scale voltage corresponding to black display data in a period of tH3 and tH4. Vdd
Is a grayscale voltage waveform of a signal line that outputs a grayscale voltage for performing halftone display at tH1, tH2, tH3, tH4, and tH5. Regarding the counter voltage Vcom, the solid line (Vc
omC) is the counter electrode line 1 at the output end of the power supply circuit 106.
13 is a waveform diagram, and a dashed line (VcomD) is a waveform diagram inside the liquid crystal panel 105.

In the present embodiment, the correction data generation circuit provided in the interface circuit 102 calculates the voltage correction from the value of the display data output from the interface circuit 102.

Now, the present liquid crystal display is a display that performs color display, and the display data for one pixel output from the interface circuit 102 is composed of 8-bit red display data, 8-bit green display data, and 8-bit blue display data. The description will be made assuming that the data is composed of three color display data.

The correction amount data generating circuit shown in FIG. 2 includes red display data RD7: 0 and green display data GD, which are display data for one pixel output from the interface circuit 102.
7: 0 and blue display data BD7: 0 are sequentially and concurrently input to counters 701, 702, and 703, respectively.

When the most significant bit RD7 of the red display data RD7: 0, the most significant bit GD7 of the green display data GD7: 0, and the most significant bit BD7 of the blue display data BD7: 0 become valid values, The respective counters 701, 702, and 703 perform the dot clock D
Counts up in synchronization with CLK. As a result, each of the counters 701, 702, and 703 counts the number of pieces of display data in which the most significant bit of the color display data corresponding to the counter is a valid value, which is included in the display data output from the interface circuit 102.

On the other hand, when the horizontal synchronizing signal HSYNC becomes valid, the values counted by the respective counters 701, 702, 703 are taken into the respective latch circuits 707, 708, 709 and remain until the next horizontal synchronizing signal HSYNC becomes valid. Will be retained. At this time, each counter 701, 70
The count values of 2,703 are cleared by the horizontal synchronization signal HSYNC. Each counter 701, 702, 703
Are cleared and then restart the counting operation described above.

The red display data, green display data, and blue display data held in the latch circuits 707, 708, and 709 are added by an adder 713. As a result, the added value indicates the number of color display data included in one line and whose most significant bit is a valid value.

The added value is transferred as correction amount data to the common electrode voltage correction circuit of the power supply circuit 106 shown in FIG.

Next, in the counter electrode voltage correction circuit of the power supply circuit 106 shown in FIG. 3, the input correction amount data is converted into analog voltages by the digital / analog conversion circuits 801 and 802, and is used as a correction voltage. That is, the digital / analog conversion circuits 801 and 802 increase or decrease the level of the correction voltage to be output according to the increase or decrease of the correction amount data value.

Further, an analog voltage value substantially corresponding to the amount of attenuation of the common electrode voltage applied to the line for which the correction amount data has been generated is compared with the input correction amount data value by a digital / analog conversion circuit. Digital / analog conversion circuits 801,
A conversion characteristic 802 is set.

Here, the voltage dividing resistors 805 and 80
6 and 807, the common electrode reference voltage 808 of the positive polarity is VcomC in the tH1 period shown in FIG.
And the negative electrode reference voltage 809 is set to be the voltage level of the peak value of VcomD in the period tH2 shown in FIG.

The analog addition circuit 810 adds the correction voltage generated by the digital / analog conversion circuit 801 to the positive counter electrode reference voltage 808, and
1 subtracts the correction voltage generated by the digital / analog conversion circuit 802 from the negative counter electrode reference voltage 809. As a result, the voltage level output from the analog addition circuit 810 changes the peak value of the counter electrode reference voltage 808 of positive polarity to the number of color display data in which the most significant bit of the line scanned in the period is a valid value. The voltage level is increased by the corresponding voltage level. Similarly, the voltage level output from the analog addition circuit 811 is the peak value of the negative reference electrode reference voltage 809, and the color display data of which the most significant bit of the line scanned during the period is an effective value. The voltage level is increased by the voltage level corresponding to the number.

The voltage selection circuit 814 outputs the liquid crystal change signal 10
According to the polarity of 9'M ', the output of the analog addition circuit 810 is applied when a positive counter electrode voltage is applied to the counter electrode, and the analog addition circuit is applied when a negative counter electrode voltage is applied to the counter electrode. The output of the circuit 811 is selected and output to the counter electrode 113 via the current amplification circuit 816.

As a result, as in the periods tH3 and tH4 in FIG. 4, for a period in which a large number of pixels (for example, black display data) are applied with a large gradation voltage to the line scanned in the period, the positive electrode in the period tH3 is used. Like the peak value of the positive VcomC, the voltage level of the positive counter electrode voltage is increased by ΔVcom, or the negative VcomC during the tH4 period is increased.
, The voltage level of the negative electrode voltage can be reduced by ΔVcom.

Therefore, since there are many pixels (for example, black display data) to which a large gray scale voltage is applied to the line scanned during the period, the opposing voltage inside the liquid crystal panel 105 attenuates by ΔVcom like VcomD. Even so, the voltage effective value V actually applied to the liquid crystal 119 is
drms can be constant or almost constant.

For this reason, according to the present embodiment, it is possible to reduce the deterioration of the image quality and realize the high image quality display.

The first embodiment of the present invention has been described.

Here, during the scanning period of one line, the total of the gradation voltages applied to the pixels in the scanning line is:
FIG. 5 shows the relationship between the voltage distortion amounts of the common electrode voltage during the scanning period.

As shown in the figure, the amount of voltage distortion actually increases with an increase in the total gradation voltage applied to the pixels in the scanning line. The total of the gradation voltages applied to the pixels can be obtained by considering all the bit values of the color display data of all the pixels in the scan line.

However, considering all the bit values of the color display data leads to an increase in the required circuit scale. Therefore, in the above embodiment, the most significant bit RD7 of the red display data RD7: 0, The most significant bit GD7 of the green display data GD7: 0 is the blue display data BD7: 0.
Paying attention only to the most significant bit BD7,
The total of the gradation voltages applied to the pixels in the scanning line was obtained, and a correction voltage corresponding to the total was generated. However, in this case, the total of the gradation voltages applied to the pixels in the scanning line may be obtained in consideration of all the bit values of each color display data, and the correction voltage may be generated according to the total.

Alternatively, 2 bits indicated by 8 bits of each color display data
The same effect can be obtained by dividing the 56 gradations into three, four, etc., and determining the correction amount data by weighting each divided region.

That is, a correction amount data calculation circuit shown in FIG. 5 is provided in the interface circuit 102 instead of the correction amount data calculation circuit shown in FIG.

In FIG. 5, reference numeral 2001 denotes a decoder, 2002, 2003, and 2004 denote data amount detection circuits, and each data amount detection circuit 2002, 2003, 20
04 includes a counter 2005 and a latch 2006. 2007 is a 2/3 circuit, and 2008 is a 1/3 circuit.
Circuit. These are portions corresponding to red display data, and although not shown, similar circuits are provided for blue display data and green display data.

In FIG. 5, reference numeral 2009 denotes an adding circuit.

The decoder 2001 decodes the value of each color display data according to the weighting data associated with the value of the color display data. Here, the correspondence between the value of each color display data and the weighting data is as shown in FIG. Weighting data of 256 to 193 is “3”, gradation No. The weighting data of 192 to 129 is 2, the gradation No. Weighting data of 128 to 65 is “1”, gradation No. Weighting data from 64 to 1 is '0'.

More specifically, the decoder 2001 extracts the upper two bits RD7 and RD6 of the red display data RD7: 0 and, if the upper two bits are (1, 1), sends a pulse to the data amount detection circuit 2002. And outputs a pulse to the data amount detection circuit 2003 if the upper 2 bits are (1, 0), and outputs a pulse to the data amount detection circuit 2004 if the upper 2 bits are (0, 0). I do.

Each data amount detection circuit 2002, 2003,
The counter 2005 in 2004 counts the pulses sent from the decoder 2001 in synchronization with DCLK, and sends the count value to the latch 2006 in synchronization with HSYNC.

The output of the data amount detection circuit 2003 is 2 /
The data is converted into a value of 2/3 by the trimmer circuit 2007 and is added to the adder 201.
Sent to 0. Further, the output of the data detection circuit 2004 is converted into a value of ３ by the １ ／ circuit 2008 and sent to the addition circuit 2010.

The adder 2010 includes a 2/3 circuit 2007 and a 1/3 circuit 20 corresponding to the illustrated red display data.
08, the output of the data amount detection circuit 2002 and the 2/3 circuit 2007 corresponding to the blue display data (not shown)
The output of the 1/3 circuit 2008, the data amount detection circuit 2002, and 2/3 corresponding to the green display data (not shown)
The outputs of the conversion circuit 2007, the 1/3 conversion circuit 2008, and the data amount detection circuit 2002 are added to obtain correction amount data.

By doing so, the correction voltage can be generated with higher accuracy than in the embodiment described above, and a display screen with higher image quality can be obtained.

In the above-described embodiment in which only the most significant bit is considered, the display data and the weighting data are stored in FIG.
This is functionally equivalent to the case shown in FIG.

In the above description, the addition circuit 7 shown in FIG.
13 and the output of the adder 2010 in FIG. 6 are used as the correction amount data. However, this is based on the required image quality and the restrictions on the digital / analog side memorization to be used. Only the side bits may be used as the correction amount data. For example, only the upper 4 bits of the output of the adder 713 in FIG. 2 are used as the correction amount data, and the correction voltage is set to 16
You may make it only between steps.

Hereinafter, a second embodiment of the present invention will be described.

In the second embodiment, the correction of the gradation voltage is performed instead of the correction of the common electrode voltage in the first embodiment.

In the second embodiment, the power supply circuit 106 includes a gradation voltage correction circuit shown in FIG. 9 instead of the counter electrode voltage correction circuit of FIG. 3 used in the first embodiment. Other configurations are the same as in the first embodiment.

In the gradation voltage correction circuit shown in FIG. 9, reference numerals 1001 and 1002 denote digital / analog conversion circuits, and reference numerals 1003 and 1004 denote correction voltages output from the digital / analog conversion circuits 1001 and 1002, respectively. Is an analog addition circuit, and 1006
Is an analog subtraction circuit. Also, 1007, 100
8 is a voltage output from the analog addition circuit 1005 and the analog subtraction circuit 1006, respectively. And 1009,
Reference numeral 1010 denotes a resistor group for generating a gradation voltage.
Is a voltage line group for transferring the gray scale voltage divided by the resistor group 1009, and 1012 is a voltage line group for transferring the gray scale voltage divided by the resistor group 1010. Also, 1013
Is a voltage selection circuit group, and 1014 is a voltage line group that transfers the gray scale voltage selected by the voltage selection circuit group 1013 and converted to AC. Reference numeral 1015 denotes a current amplifier circuit group.

In FIG. 9, the correction amount data input from the correction data amount generation circuit described in the first embodiment is converted into analog voltages by digital / analog conversion circuits 1001 and 1002, and output as correction voltages. .

The correction voltage generated by the digital / analog conversion circuit 1001 is added to the reference voltage by the analog addition circuit 1005, and the digital / analog conversion circuit 1002
The correction voltage generated in is calculated by the analog subtraction circuit 1006.
It is subtracted from the reference voltage. Here, when the addition and the subtraction are not performed by the analog addition circuit 1005 and the analog subtraction circuit 1006, the negative gradation voltage reference signal similar to the conventional one is obtained from the resistor group 1009 and the conventional one from the resistance group 1010. This voltage is such that a similar positive polarity gradation voltage reference signal is output.

The voltage output from the analog adding circuit 1005 is divided by a voltage dividing resistor group 1009 to become a positive gradation voltage reference signal.
Are divided by a voltage dividing resistor group 1010 to become a negative gradation voltage reference signal.

The voltage selection circuit group 1013 determines whether the positive polarity grayscale voltage is used (the negative counter electrode voltage is used) in accordance with the polarity of the liquid crystal change signal 109'M '. Select the gray scale voltage reference signal and set the current amplification circuit group 1
The signal is output to the signal drive circuit 103 as the gray scale voltage reference signal 111 via 015. The voltage selection circuit group 10
Reference numeral 13 selects a negative gradation voltage reference signal during a period in which a negative gradation voltage is used (a period in which a positive counter electrode voltage is used) in accordance with the polarity of the liquid crystal change signal 109'M '. Then, the signal is output to the signal driving circuit 103 as the gradation voltage reference signal 111 via the current amplifier circuit group 1015.

As described above, the signal driving circuit 103
A gradation voltage corresponding to the display data is generated based on the supplied gradation voltage reference signal.

Here, FIG. 10 shows the counter electrode voltage and the gradation voltage applied to the liquid crystal according to the present embodiment.

In FIG. 10, CL1 is a line selection signal, and M is a liquid crystal alternating signal. Vde is tH
The halftone display is performed in the period of 1, tH2, tH5, and tH3,
7 is a gray scale voltage waveform of a signal line that outputs a gray scale voltage for performing black display in a period of tH4. Vdf is tH1, tH
This is a gradation voltage waveform of a signal line that outputs a gradation voltage for performing halftone display in any of the periods H2, tH3, tH4, and tH5.

Regarding the counter voltage Vcom, a solid line (VcomE) is a waveform diagram of the counter electrode line 113 at the output end of the power supply circuit 106, and a dashed line (VcomF) is a waveform diagram inside the liquid crystal panel 105.

Here, in the periods tH1, tH2, and tH25 where there are not many pixels (for example, black display data) to which a large gradation voltage is applied to the line scanned in the period, the gradation voltage Vde for performing the intermediate gradation display. In addition, Vdf has the same voltage level as that of the related art.

On the other hand, in the period of tH3 and tH4 where a large number of pixels (for example, black display data) are applied to the line scanned in the period, the correction voltage is added or subtracted from the peak value of the gradation voltage. As a result, the gray scale voltage of the intermediate gray scale becomes tH at which the gray scale voltage of the positive polarity is applied.
The voltage level decreases by ΔVdf like Vdf in the 3rd period, and Vd in the tH4 period when the negative gradation voltage is applied.
The voltage level is increased by ΔVdf as in f. Also,
Similarly, the voltage level of the black gradation voltage also decreases during the period tH3 in which the positive gradation voltage is applied, and increases in the period tH4 in which the negative gradation voltage is applied.

Therefore, since there are many pixels (for example, black display data) to which a large gray scale voltage is applied to the line scanned during the period, the opposing voltage inside the liquid crystal panel 105 is attenuated by ΔVcom like VcomD. Even so, the voltage effective value V actually applied to the liquid crystal 119 is
drms can be constant or almost constant.

Hereinafter, a third embodiment of the present invention will be described.

FIG. 11 shows the configuration of the liquid crystal display according to the present embodiment.

In the figure, reference numeral 1201 denotes an interface circuit; 1202, a control signal bus for transferring display data and control signals for controlling the signal driving circuit 103;
Reference numeral 1203 denotes a control signal bus for transferring a control signal for the scan drive circuit, and 1204 denotes a scan drive circuit.
Reference numeral 205 denotes a liquid crystal alternating signal, and reference numeral 1206 denotes a power supply circuit.

This embodiment is different from the above-described conventional liquid crystal display in the configuration and operation of the interface circuit 1201.

FIG. 12 shows the configuration of the interface circuit 1201 according to the present embodiment.

In the figure, 1301, 1302, 1303, 1
Reference numeral 304 denotes a line memory for storing one line of display data, 1305, 1306, 1307, and 1308.
Are the line memories 1301, 1302, 1303, 1
Reference numeral 1309 and 1310 denote display data selection circuits, and reference numerals 1311 and 1312 denote display data selection circuits 130.
Reference numeral 913 denotes a data bus for transferring display data output from the display data. Reference numeral 1313 denotes a display data selection circuit.
314 is a display data bus. Here, the display data bus 1314 is included in the control signal 1202 in FIG.

Next, reference numeral 1315 denotes each line memory 130.
1, 1302, 1303, and 1304, a control circuit 1316; a write control circuit 1316;
7, a read control circuit; 1318, a write control signal generated by the write control circuit 1316;
Reference numeral 1319 denotes a read control signal generated by the read control circuit 1317, 1320 denotes a selection signal of the display data selection circuits 1311 and 1312, and 1321 denotes a selection signal of the display data selection circuit 1313.

The reference numeral 1322 denotes a horizontal synchronizing signal “CL”.
1 ”, 1323 is a horizontal synchronizing signal“ CL3 ”, which is a control signal bus 1202 and a control signal bus 1203, respectively.
include. Data is an interface signal 1
01 is a data bus for transferring display data included in the data bus 01.

The operation of interface circuit 1201 will be described below with reference to FIG.

The line display data Lx in FIG. 13 represents display data for one line. A hatched portion indicates a period during which valid line display data is not transferred.

Now, when the line display data Ln is input, the write control signal generation circuit 1316 transfers the write control signal 1318 to the line memory 1301 and writes the line display data Ln to the line memory 1301.
Similarly, when the line display data Ln + 1 is input, it is written into the line memory 1302, and the line display data Ln + 2
Is input to the line memory 1303, and when the line display data Ln + 3 is input,
Write to 04.

When the line display data Ln + 4 is input, the write control signal 13
When the line display data Ln + 5 is input, the write control 1318 is transferred to the line memory 1302.
Line display data is written in 1, 1302, 1303, and 1304.

The read control circuit 1317 transfers and stores the read control signal 1319 to the line memories 1301 and 1302 while the line display data Ln + 2 and Ln + 3 are written in the line memories 1303 and 1304, respectively. Line display data Ln, Ln +
1 are sequentially read and supplied to the signal drive circuit 103. At this time, as shown in FIG. 13, the even-numbered line and the odd-numbered line are paired, and the alternating signal “M” is converted every two horizontal periods. Also, a period from the timing of the change of the AC signal “M” to the end of the period in which the line display data Ln supplied first after the change of the AC signal “M” is supplied to the liquid crystal panel is defined as the line display data. Each line display data and the horizontal synchronization signal CL1 are supplied to the signal drive circuit 103 so that Ln + 1 is longer than the period during which the liquid crystal panel is supplied. Immediately before the end of the supply of each line display data to the liquid crystal panel, a horizontal synchronizing signal CL3 for generating a scanning voltage at a timing at which the liquid crystal 109 takes in a gradation voltage is supplied to the scanning drive circuit 1204.

In the example of FIG. 14, when the line data is supplied to the interface circuit, the period in which there is no valid data before Ln + 1 is shifted to Ln when the line display data is supplied, whereby each line data is supplied to the liquid crystal panel. The period during which the line display data to be supplied first after the change of the AC signal "M" is supplied to the liquid crystal panel without changing the period to be applied and without changing the sum of the horizontal periods for two lines. The period until the end of the period is longer. However, at the time of reading, a period in which the line display data initially supplied after the change of the AC signal “M” is supplied to the liquid crystal panel may be extended without providing a period in which no valid data is provided.

Similarly to the above operation, during the period in which the line display data Ln + 4 and Ln + 5 are written in the line memories 1301 and 1302, the readout control circuit 1317 operates the line circuits 1303 and 1304, respectively. Read control signal 1319
Is transferred and the stored line display data Ln + 2, L
n + 3 are sequentially read out and supplied to the signal drive circuit 103. Hereinafter, similar processing is performed by the line memories 1301, 13
02 and the line memories 1303 and 1304.

The effect obtained as a result will be described with reference to FIG.

In FIG. 14, CL1 is a horizontal synchronizing signal, which becomes effective once in one horizontal period. In the present embodiment, the cycle changes for each line. M is a liquid crystal alternating signal, and the power supply circuit 1206 performs control such that the counter electrode voltage Vcom has a negative polarity when the signal is at a “low” level, and has a positive polarity when the signal is at a “high” level. The liquid crystal alternating signal is converted every two lines. Vdg
Is a grayscale voltage waveform of a signal line that outputs a grayscale voltage corresponding to halftone display during the periods tH1, tH2, and tH5.
7 is a gray scale voltage waveform of a signal line that outputs a gray scale voltage corresponding to black display data in a period of H3 and tH4. Vdh is
Each of tH1, tH2, tH3, tH4, and tH5 is a gradation voltage waveform of a signal line that outputs a gradation voltage for performing halftone display. Regarding the counter voltage Vcom, a solid line (Vcom
G) is a waveform diagram of the counter electrode line 113 at the output end of the power supply circuit 1206 shown in FIG. 1, and a dashed line (VcomH) is a waveform diagram inside the liquid crystal panel 105.

As shown in FIG. 14, by converting the AC signal "M" into AC every two lines as described above, tH12 and tH12, which are the periods for applying the gradation voltage of the odd-numbered lines, are used.
During the period of H14, the common electrode voltage Vcom is not converted into an alternating current, so that the voltage fluctuation of the common electrode voltage depending on the display data is suppressed. The counter electrode voltage Vcom is converted into AC during the periods tH11, tH13, and tH15 during which the gradation voltage of the even-numbered line is applied. By taking a relatively long time until the power supply circuit 1206 takes in the voltage, the power supply circuit 1206 eliminates the voltage distortion caused by the AC.
Since the time required for the common electrode voltage VcomH inside the liquid crystal panel 105 to reach the common electrode voltage VcomG at the end can be secured, it is possible to suppress voltage fluctuation depending on display data.

Therefore, when the liquid crystal takes in the gradation voltage, the effective voltage value Vdrm actually applied to the liquid crystal 119 is obtained.
s can be constant regardless of the display data,
Image quality deterioration can be reduced, and high image quality display can be realized.

In the third embodiment, the line for displaying the line display data which is supplied first after the change of the liquid crystal alternating signal includes a period in which no valid data exists before the line. Period (tH11,
During the time tH13, etc., the selection voltage can be applied. However, for the other lines displaying the line display data, the selection voltage is applied to the line because there is no period without valid data before that. Possible period (t
H12, tH14, etc.) are relatively short.

For this reason, if the selection voltage is supplied to the scanning lines only during the horizontal period, a sufficient selection voltage may not be applied due to the time constant from the non-selection state to the selection state.

Therefore, in the present embodiment, the scanning drive circuit 1
While synchronizing with the horizontal synchronizing signal CL3, FIG.
As shown in (2), for a line whose horizontal period is relatively short, the selection voltage is applied in advance from one horizontal period before the horizontal period of the line, and a sufficient selection voltage is applied to all the lines. To be done.

The third embodiment of the present invention has been described.

In the third embodiment described above, the AC conversion is performed every two lines, but the AC conversion may be performed on three or more lines.

The embodiments of the present invention have been described.

In each of the above embodiments, it has been described that the larger the value of the display data is, the larger the corresponding gradation voltage is. However, in the present embodiment, the smaller the value of the display data is, The present invention can be similarly applied to a liquid crystal display in which the gray scale voltage corresponding to is small.
However, in this case, in the first and second embodiments,
When the correction amount data generation circuit of FIG. 2 is used, the display data whose most significant bit is 0 is counted when calculating the correction amount data, and when the correction amount data generation circuit of FIG. The weighting data is set to increase as the value of.

Further, in each of the above embodiments, the case where the liquid crystal panel is driven by the alternating voltage in which the counter electrode voltage is converted by using the low voltage driving circuit is described. The configuration for correcting the counter electrode and the gradation voltage can be applied even when the counter electrode voltage is not changed to an alternating current.

[0132]

As described above, according to the present invention, it is possible to improve the image quality deterioration due to the voltage distortion of the counter voltage and the compensation voltage depending on the display data.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a liquid crystal display according to a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a correction amount data generation circuit according to the first embodiment of the present invention.

FIG. 3 is a block diagram illustrating a configuration of a common electrode voltage correction circuit according to the first embodiment of the present invention.

FIG. 4 is a diagram showing driving waveforms in the liquid crystal display according to the first embodiment of the present invention.

FIG. 5 is a diagram showing the relationship between the total gradation voltage applied to the pixels in one line and the amount of voltage distortion.

FIG. 6 is a diagram illustrating another configuration example of the correction data amount calculation circuit according to the first embodiment of the present invention.

FIG. 7 is a diagram illustrating an example of a relationship between a color display data value and weighting data in a correction data amount calculation circuit according to another configuration example according to the first embodiment of the present invention.

FIG. 8 is a diagram illustrating an example of a relationship between a color display data value and weighting data in a correction data amount calculation circuit according to another configuration example according to the first embodiment of the present invention.

FIG. 9 is a block diagram illustrating a configuration of a gradation voltage correction circuit according to a second embodiment of the present invention.

FIG. 10 is a diagram showing driving waveforms in a liquid crystal display according to a second embodiment of the present invention.

FIG. 11 is a block diagram illustrating a configuration of a liquid crystal display according to a third embodiment of the present invention.

FIG. 12 is a block diagram illustrating a configuration of an interface circuit according to a third embodiment of the present invention.

FIG. 13 is a timing chart showing the operation of the interface circuit according to the third embodiment of the present invention.

FIG. 14 is a diagram showing driving waveforms in a liquid crystal display according to a third embodiment of the present invention.

FIG. 15 is a diagram showing a timing of applying a selection voltage in a liquid crystal display according to a third embodiment of the present invention.

FIG. 16 is a block diagram showing a configuration of a conventional liquid crystal display.

FIG. 17 is a timing chart showing a driving mechanism in a conventional liquid crystal display.

FIG. 18 is a diagram showing how image quality deteriorates due to distortion of a common electrode voltage depending on display data in a conventional liquid crystal display.

FIG. 19 is a diagram showing a current flow by a gray scale voltage in a conventional liquid crystal display.

FIG. 20 is a diagram showing driving waveforms in a conventional liquid crystal display.

[Explanation of symbols]

101: interface signal, 102: interface circuit, 103: signal drive circuit, 104: scan drive circuit,
105: liquid crystal panel, 106: power supply circuit, 107: control signal, 108: control signal, 109: AC signal, 11
0: control signal, 111: gradation voltage signal, 112: scanning voltage signal, 113: counter electrode, 114: counter electrode, 11
5: signal line group, 116: scanning line group, 117: pixel portion, 1
18: thin film transistor, 119: liquid crystal, 120: compensation capacitance, 201: interface signal, 202: interface circuit, 203: signal drive circuit, 204: scan drive circuit, 205: liquid crystal panel, 206: power supply circuit, 20
7: control signal, 208: control signal, 209: alternating signal, 210: gradation voltage signal, 211: scanning voltage signal, 2
12: compensation electrode, 213: counter electrode, 214: signal line group, 215: scanning line group, 216: pixel portion, 217: thin film transistor, 218: liquid crystal, 219: compensation capacitance, 70
1: Counter with load function, 702: Counter with load function, 703: Counter with load function, 7
04: data bus, 705: data bus, 706: data bus, 707: latch circuit, 708: latch circuit, 7
09: latch circuit, 710: data bus, 711: data bus, 712: data bus, 713: adder circuit, 80
1: digital / analog conversion circuit, 802: digital / analog
Analog conversion circuit, 803: correction voltage line, 804: correction voltage line, 805: resistance, 806: resistance, 807: resistance,
808: reference electrode reference voltage line of positive polarity, 809: reference voltage line of negative electrode, 810: analog addition circuit, 8
11: analog subtraction circuit, 812: output voltage line, 81
3: output voltage line, 814: voltage selection circuit, 815: output voltage line, 816: current amplifier circuit, 1001: digital /
Analog conversion circuit, 1002: digital / analog conversion circuit, 1003: correction voltage line, 1004: correction voltage line,
1005: analog addition circuit, 1006: analog subtraction circuit, 1007: output voltage line, 1008: output voltage line,
1009: resistor group, 1010: resistor group, 1011: voltage line group, 1012: voltage line group, 1013: voltage selection circuit group, 1014: voltage line group, 1015: current amplification circuit group,
1201: interface circuit, 1202: control signal,
1203: control signal, 1204: scan drive circuit, 120
5: liquid crystal alternating signal, 1206: power supply circuit, 1301:
Line memory, 1302: line memory, 1303: line memory, 1304: data bus, 1305: data bus, 1307: data bus, 1308: data bus, 1309: display data selection circuit, 1310: display data selection Circuit, 1311: data bus, 1312: data bus, 1313: display data selection circuit, 1314: display data bus, 1315: control circuit, 1316: write control circuit, 1317: read control circuit, 1318: write control signal line, 131
9: read control signal line, 1320: selection signal, 132
1: selection signal, 1314: horizontal synchronization signal “CL1”, 1
314: Horizontal synchronization signal “CL3”

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification symbol FI H04N 5/66 102 H04N 5/66 102B (72) Inventor Hiroshi Kurihara 3300 Hayano Mobara-shi, Chiba Pref. Hitachi, Ltd. Electronic Device Division

Claims (10)

[Claims] A plurality of liquid crystal cells arranged in a matrix, a scanning electrode provided for each horizontal line of the matrix, a driving electrode provided for each vertical line of the matrix, and a counter electrode. And each of the liquid crystal cells has
The scanning electrode connected to the horizontal line to which the liquid crystal cell belongs, the driving electrode to the vertical line to which the liquid crystal cell belongs, and the counter electrode are connected to each other while the voltage supplied to the connected scanning electrode is a selection voltage. The effective voltage with respect to the counter electrode voltage of the gradation voltage supplied from the driving electrode is held when the voltage supplied to the connected scanning electrode changes from the selection voltage to the non-selection voltage, and the density according to the held voltage is held. A liquid crystal panel, a power supply circuit for generating the common electrode voltage, and sequentially selecting each horizontal line, applying a selection voltage to the scanning electrodes of the selected horizontal line, and applying a selection voltage to horizontal lines other than the selected scanning electrode. A scan drive circuit for applying a non-selection voltage to the scan electrode; A driving circuit for applying a driving electrode for each vertical line to which a liquid crystal cell corresponding to each pixel belongs, and for each of the horizontal lines, a display line corresponding to the horizontal line. The power supply circuit includes a correction amount generation unit that calculates a total magnitude of display data values of the pixels as a correction amount of the horizontal line, wherein the power supply circuit calculates a correction amount of each horizontal line calculated by the correction amount generation unit. Accordingly, the effective voltage with respect to the counter electrode voltage of the gradation voltage supplied from each drive electrode during the period when the selection voltage is applied to the scan electrode of the horizontal line depends on the value of the corresponding display data. A liquid crystal display device, wherein the voltage level of the common electrode voltage is corrected to a prescribed level. 2. A liquid crystal display device comprising: a plurality of liquid crystal cells arranged in a matrix; scanning electrodes provided for each horizontal line of the matrix; driving electrodes provided for each vertical line of the matrix; And each of the liquid crystal cells has
The scanning electrode connected to the horizontal line to which the liquid crystal cell belongs, the driving electrode to the vertical line to which the liquid crystal cell belongs, and the counter electrode are connected to each other while the voltage supplied to the connected scanning electrode is a selection voltage. The effective voltage with respect to the counter electrode voltage of the gradation voltage supplied from the driving electrode is held when the voltage supplied to the connected scanning electrode changes from the selection voltage to the non-selection voltage, and the density according to the held voltage is held. A power supply circuit for generating the counter electrode voltage and a gradation reference voltage, sequentially selecting each horizontal line, applying a selection voltage to a scan electrode of the selected horizontal line, and performing a selected scan. A scan drive circuit for applying a non-selection voltage to the scan electrodes of the horizontal lines other than the electrodes; and a display data of each pixel of a display line corresponding to the horizontal line to which the scan drive circuit is applying the selection voltage. And a drive circuit for generating a gray scale voltage corresponding to the gray scale reference voltage at a voltage level corresponding to the voltage level of the gray scale reference voltage, and applying the generated gray scale voltage to a drive electrode of each vertical line to which a liquid crystal cell corresponding to each pixel belongs. A liquid crystal display device, wherein, for each of the horizontal lines, a correction amount generating unit that calculates, as a correction amount of the horizontal line, a total magnitude of display data values of pixels of a display line corresponding to the horizontal line. The power supply circuit is supplied from each driving electrode during a period in which the selection voltage is applied to the scanning electrode of the horizontal line according to the correction amount of each horizontal line calculated by the correction amount generation unit. Correcting the voltage level of the gray scale reference voltage serving as a reference of the gray scale voltage so that the effective voltage of the gray scale voltage with respect to the common electrode voltage becomes a prescribed level corresponding to the value of the corresponding display data. To Characteristic liquid crystal display device. 3. The liquid crystal display device according to claim 1, wherein said power supply circuit converts said counter electrode voltage into an alternating current at a predetermined alternating period, and said driving circuit operates said floor at said alternating period. A liquid crystal display device, wherein the adjustment voltage is converted into an alternating current with a polarity opposite to the polarity of the common electrode voltage. 4. The liquid crystal display device according to claim 1, wherein the display data of each pixel is data composed of a plurality of bits, and wherein the correction amount generating means includes a plurality of display data. Of the bits, only the value of the bit having a large influence on the magnitude of the gradation voltage corresponding to the display data is considered, and the total magnitude of the display data values of the pixels on the display line is approximately determined. A liquid crystal display device characterized by the above-mentioned. 5. A liquid crystal display device comprising: a plurality of liquid crystal cells arranged in a matrix; a scan electrode provided for each horizontal line of the matrix; a driving electrode provided for each vertical line of the matrix; and a counter electrode. And each of the liquid crystal cells has
The scanning electrode connected to the horizontal line to which the liquid crystal cell belongs, the driving electrode to the vertical line to which the liquid crystal cell belongs, and the counter electrode are connected to each other while the voltage supplied to the connected scanning electrode is a selection voltage. The effective voltage with respect to the counter electrode voltage of the gradation voltage supplied from the driving electrode is held when the voltage supplied to the connected scanning electrode changes from the selection voltage to the non-selection voltage, and the density according to the held voltage is held. A liquid crystal display device including a liquid crystal panel, wherein: a plurality of horizontal line periods are unequally divided; and timing generation means for generating a timing of a modified horizontal line period corresponding to each horizontal line; A power supply circuit for generating an alternating counter electrode voltage whose polarity changes for each period, and for each horizontal line period, a display line corresponding to the horizontal line period And it holds the input display data of each pixel,
During each corrected horizontal line period indicated by the timing generated by the timing generation means, the display data of each pixel of the display line corresponding to the horizontal line period is read until the corrected horizontal line period ends, and the read data corresponding to the read display data is read. Means for applying a gradation voltage having a polarity opposite to that of the counter electrode voltage to the driving electrode of each vertical line to which the liquid crystal cell corresponding to each pixel belongs, sequentially in synchronization with the end of each corrected horizontal line period. A scan driving circuit that changes a voltage applied to a scan electrode of a horizontal line corresponding to the corrected horizontal line period from a selection voltage to a non-selection voltage. The timing is adjusted so that the first corrected horizontal line period among the equally divided corrected horizontal line periods is temporally longer than the horizontal line period. The liquid crystal display device which is characterized in that formed. 6. The liquid crystal display device according to claim 5, wherein the scanning drive circuit precedes the start of the first horizontal line period in the plurality of horizontal line periods in which the polarity of the common electrode voltage is the same. Wherein the voltage applied to the scanning electrodes of the horizontal lines corresponding to the first horizontal line period is changed to a selection voltage. 7. A liquid crystal display device comprising: a plurality of liquid crystal cells arranged in a matrix; a scan electrode provided for each horizontal line of the matrix; a drive electrode provided for each vertical line of the matrix; and a counter electrode. And each of the liquid crystal cells has
The scanning electrode connected to the horizontal line to which the liquid crystal cell belongs, the driving electrode to the vertical line to which the liquid crystal cell belongs, and the counter electrode are connected to each other while the voltage supplied to the connected scanning electrode is a selection voltage. The effective voltage with respect to the counter electrode voltage of the gradation voltage supplied from the driving electrode is held when the voltage supplied to the connected scanning electrode changes from the selection voltage to the non-selection voltage, and the density according to the held voltage is held. And a power supply circuit for generating the counter electrode voltage, sequentially selecting each horizontal line, applying a selection voltage to the scanning electrode of the selected horizontal line, and selecting A scan drive circuit for applying a non-selection voltage to the scan electrodes of the horizontal lines other than the scan electrodes; and Enter the display data,
A driving circuit for applying a gradation voltage corresponding to the input display data of each pixel to a driving electrode of each vertical line to which a liquid crystal cell corresponding to each pixel belongs; and a driving circuit corresponding to each of the horizontal lines. Correction amount generation means for calculating the total magnitude of the display data values of the respective pixels of the display line to be corrected as the correction amount of the horizontal line. In accordance with the correction amount of the line, the effective voltage with respect to the counter electrode voltage of the gradation voltage supplied from each driving electrode during the period when the selection voltage is applied to the scanning electrode of the horizontal line is the corresponding display data. A driving apparatus for a liquid crystal panel, wherein a voltage level of the common electrode voltage is corrected so as to have a prescribed level according to a value. 8. A plurality of liquid crystal cells arranged in a matrix, a scanning electrode provided for each horizontal line of the matrix, a driving electrode provided for each vertical line of the matrix, and a counter electrode. And each of the liquid crystal cells has
The scanning electrode connected to the horizontal line to which the liquid crystal cell belongs, the driving electrode to the vertical line to which the liquid crystal cell belongs, and the counter electrode are connected to each other while the voltage supplied to the connected scanning electrode is a selection voltage. The effective voltage with respect to the counter electrode voltage of the gradation voltage supplied from the driving electrode is held when the voltage supplied to the connected scanning electrode changes from the selection voltage to the non-selection voltage, and the density according to the held voltage is held. A driving circuit for driving a liquid crystal panel exhibiting the following, wherein the counter electrode voltage, a power supply circuit for generating a gradation reference voltage, and sequentially selecting each horizontal line, and selecting voltage to a scanning electrode of the selected horizontal line. And a scan drive circuit for applying a non-selection voltage to scan electrodes on horizontal lines other than the selected scan electrode, and a display corresponding to the horizontal line to which the scan drive circuit is applying the select voltage. Enter the display data of each pixel of the Inn,
A gray scale voltage corresponding to the input display data of each pixel is generated at a voltage level corresponding to the voltage level of the gray scale reference voltage, and applied to a driving electrode of each vertical line to which a liquid crystal cell corresponding to each pixel belongs. And a correction amount generating means for calculating, for each horizontal line, a total magnitude of display data values of pixels of a display line corresponding to the horizontal line as a correction amount of the horizontal line. The power supply circuit, according to the correction amount of each horizontal line calculated by the correction amount generation unit, a floor supplied from each driving electrode during a period in which the selection voltage is applied to the scanning electrode of the horizontal line. Correcting the voltage level of the gray scale reference voltage serving as a reference of the gray scale voltage so that the effective voltage of the adjustment voltage with respect to the common electrode voltage becomes a specified level corresponding to the value of the corresponding display data. Driving device for a liquid crystal panel characterized. 9. A liquid crystal cell comprising: a plurality of liquid crystal cells arranged in a matrix; scanning electrodes provided for each horizontal line of the matrix; driving electrodes provided for each vertical line of the matrix; and a counter electrode. And each of the liquid crystal cells has
The scanning electrode connected to the horizontal line to which the liquid crystal cell belongs, the driving electrode to the vertical line to which the liquid crystal cell belongs, and the counter electrode are connected to each other while the voltage supplied to the connected scanning electrode is a selection voltage. The effective voltage with respect to the counter electrode voltage of the gradation voltage supplied from the driving electrode is held when the voltage supplied to the connected scanning electrode changes from the selection voltage to the non-selection voltage, and the density according to the held voltage is held. A timing generating means for generating a timing of a modified horizontal line period corresponding to each horizontal line by unequally dividing a plurality of horizontal line periods, and for each of the plurality of horizontal line periods. A power supply circuit for generating an alternating counter electrode voltage whose polarity changes, and for each horizontal line period, a power supply circuit for each pixel of a display line corresponding to the horizontal line period. Held by entering the display data,
During each corrected horizontal line period indicated by the timing generated by the timing generation means, the display data of each pixel of the display line corresponding to the horizontal line period is read until the corrected horizontal line period ends, and the read data corresponding to the read display data is read. Means for applying a gradation voltage having a polarity opposite to that of the counter electrode voltage to the driving electrode of each vertical line to which the liquid crystal cell corresponding to each pixel belongs, sequentially in synchronization with the end of each corrected horizontal line period. A scan driving circuit that changes a voltage applied to a scan electrode of a horizontal line corresponding to the corrected horizontal line period from a selection voltage to a non-selection voltage. The timing is adjusted so that the first corrected horizontal line period among the equally divided corrected horizontal line periods is temporally longer than the horizontal line period. Driving device for a liquid crystal panel, characterized by forming. 10. The driving device according to claim 9, wherein the scanning drive circuit precedes the start of the first horizontal line period in the plurality of horizontal line periods in which the polarity of the common electrode voltage is the same. A driving apparatus for driving a liquid crystal panel, wherein a voltage applied to a scanning electrode of a horizontal line corresponding to the first horizontal line period is changed to a selection voltage.