JP2000305534A - Liquid crystal drive circuit and liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce degrading of an image quality caused by a parasitic capacity with a drain line by providing a liquid crystal driver with an output circuit to switchingly output a gradation voltage and an inverted voltage which is obtained by inverting the gradation voltage with respect to a common electrode voltage of a liquid crystal panel, and outputting the switched voltage during a horizontal period therefrom. SOLUTION: A liquid crystal driver is provided with an output amplifier circuit 133 to switchingly output a normal output of a specified gradation voltage and an inverted output with respect to a common electrode voltage, and thereby a liquid crystal panel is driven with the inverted output for a specified period of horizontal period while with the normal output for the other period. The output amplifier circuit 133 operates as an inverted output driven amplifier circuit by switching switches SW1-SW3 with a reverse signal 121 while as a normal output amplifier circuit by switching the switches SW1-SW3 with an inverted signal 121. With the inverted signal 121 made effective for the start time of the horizontal period, an inverted output with respect to the common electrode standard voltage 113 is outputted for the inverted output period an inverted output period.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display for displaying input data. In addition, the present invention relates to a liquid crystal drive circuit that performs display on a liquid crystal display, and particularly to a liquid crystal driver circuit that applies a drive voltage to a liquid crystal panel.

[0002]

2. Description of the Related Art A conventional liquid crystal display device is disclosed in JP-A-8-87.
251, the liquid crystal driver performs dot inversion driving in which the polarity of the AC liquid crystal driving voltage is inverted and output for each output terminal, thereby preventing current concentration on the common electrode of the liquid crystal panel and reducing image quality deterioration. Had been reduced.

However, in the conventional driving method, no consideration has been given to the point that the image quality is deteriorated due to the change in the liquid crystal pixel effective value voltage due to the change in the drain line voltage of the liquid crystal panel depending on the display pattern.

[0004]

In such a conventional dot inversion drive, a typical TFT shown in FIGS. 2 and 3 is used.
Image quality degradation due to the additional capacitance of the pixels of the liquid crystal panel has not been considered. FIG. 2 shows an equivalent circuit of one pixel, where TFT is a thin film transistor for performing a switching operation of a pixel electrode, Clcd is a liquid crystal capacitor, and a common electrode V
com and a capacitor. Cadd is the storage capacitor formed in the previous gate line, and Cgs is the thin film transistor T
This is the parasitic capacitance between the gate and source terminals of the FT. Further, in the liquid crystal pixel electrode, Cg1 and Cg2 are additional capacitances with the vertically adjacent gate lines Gn-1 and Gn, Cd1 and Cd.
2 has an additional capacitance with the left and right adjacent data lines Dn and Dn + 1. In the pixel configuration of FIG.
It is the same as FIG. 2 except that str is formed on the independent electrode Vstr.

[0005] In any of the above pixel structures, FIG.
In the display patterns shown in FIGS. 6 and 8, the data lines Dn and D
n + 1 and the gate line Gn have the driving waveforms shown in FIG. 5, FIG. 7, and FIG. Hereinafter, it is assumed that the voltage and luminance characteristics of the liquid crystal panel are normally white, that is, the transmittance increases when no applied voltage is applied to the pixel electrode (white), and decreases when the applied voltage is applied (black). In the horizontal display pattern shown in FIG. 4, when the white display line is selected by the gate line Gn and the on-level voltage is reached, the thin film transistor TFT is turned on. In the m-th frame, the AC polarity of the white display is changed from the data line Dn to the positive polarity. Is applied to the pixel electrode. At the same time, since the right pixel also performs white display, an applied voltage Vd1- having a negative AC polarity for white display is applied to the pixel electrode from the data line Dn + 1. In the next horizontal period, the gate line Gn is turned off, and the thin film transistor TFT of the pixel electrode is turned off, and the operation of applying the voltage to the pixel electrode is completed.

At this time, since the pixels on the next line perform black display, the data line Dn is applied with an applied voltage Vd2- having a negative polarity of black display, and the data line Dn + 1 is applied with an AC polarity of black display. Is applied with a positive applied voltage Vd2 +. In the subsequent horizontal period, a similar applied voltage is applied to the data line D.
n, Dn + 1. Then, in the next (m + 1) -th frame, an applied voltage having the opposite AC polarity is applied to the same pixel electrode, and the same operation is repeated in the subsequent frames.
Display is performed by dot inversion driving. Therefore, in this case, the parasitic capacitance Cd1 affects the voltage change of the drain line Dn on the pixel electrode, but the parasitic capacitance Cd2 affects the pixel electrode due to the voltage change of the drain line Dn + 1 substantially symmetrically with respect to the common electrode Vcom. In addition, the effect of the voltage change of the drain line on the pixel electrode is canceled.

In the case of the vertical line display shown in FIG.
As in FIG. 5, in the m-th frame and the next (m + 1) -th frame, the same voltage is applied to the same pixel electrode, and the same operation is repeated in the subsequent frames, and the display is performed by dot inversion driving. Done. In this case, the parasitic capacitance C
Due to d1, the influence on the pixel electrode due to the voltage change of the drain line Dn is canceled out because it becomes substantially symmetric with respect to the common electrode Vcom every horizontal period. In addition, the influence on the pixel electrode due to the voltage change of the drain line Dn + 1 due to the parasitic capacitance Cd2 is canceled because it becomes substantially symmetric with respect to the common electrode Vcom every horizontal period.

However, in the display pattern shown in FIG. 8, the effect of the voltage change of the drain line on the pixel electrode is not canceled. FIG. 9 shows the voltage change of the drain line at this time.
A white display is provided for each of the drain lines Dn and Dn + 1 every horizontal period,
Since the black display is repeated, the polarity is biased to the negative side in the m-th frame, and the polarity is biased to the positive side in the (m + 1) -th frame. I will.

According to the present invention, the deterioration of image quality due to the parasitic capacitance with the drain line is reduced.

[0010]

In order to solve the above-mentioned problem, an output amplifier circuit for switching between a non-inverted output of a predetermined gradation voltage and an inverted output with respect to a common electrode voltage and outputting the same to an output amplifier circuit of a liquid crystal driver. The liquid crystal panel is driven by the inverted output during a certain period of the horizontal period and the non-inverted output during the other periods. Further, an inversion control circuit for determining an inversion condition based on the display data is provided.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a configuration diagram of a liquid crystal panel driving circuit field to which the present invention is applied. 101 is a group of display signals transferred from a system device, and 102 is a circuit for converting a display signal group 101 into a synchronization signal of a liquid crystal driver and display data. A liquid crystal controller; 103, a liquid crystal driver for applying a driving voltage corresponding to display data to the liquid crystal panel; 104, a power supply circuit for generating a gradation voltage and a reference voltage of the liquid crystal panel; 105, a scanning circuit for line-sequential selection of the liquid crystal panel And 106, an active matrix liquid crystal panel, 107, display data converted for the liquid crystal driver, 108, a data transmission clock synchronized with the display data 107, 109, a horizontal synchronization signal indicating a horizontal period,
Reference numeral 110 denotes an AC signal indicating an AC timing for driving the liquid crystal, 1
Reference numeral 11 denotes a positive gradation reference voltage having a liquid crystal drive voltage having a positive AC polarity, 112 denotes a negative gradation reference voltage having a negative AC polarity of a liquid crystal drive voltage, and 113 denotes a reference voltage of a common electrode of a liquid crystal panel. The common electrode voltages Vcom and 114 are a scanning reference voltage of a scanning drive voltage output from the scanning circuit, 115 is a frame synchronization signal indicating a frame cycle, and 116 is a scanning horizontal synchronization signal indicating the timing of a scanning horizontal cycle.

Reference numeral 117 denotes a shift register circuit for sequentially taking in display data inside the liquid crystal driver 103;
Denotes a display data bus output from the shift register;
9 is a control circuit for generating a timing signal inside the liquid crystal driver from the horizontal synchronization signal 109, and 120 is a latch circuit 12.
2, a horizontal latch signal for simultaneously latching display data on the display data bus 118 into the latch circuit 1507; 121, an inversion timing signal indicating the output inversion timing of the output amplifier circuit 133; 123, output data of the latch circuit 122;
124 is a control circuit for generating a selection signal 125 from the AC signal 110, 126 is a selection circuit for selecting display data of an output terminal corresponding to an adjacent pixel, 127 is selection data,
128 is a DAC circuit for generating a positive gradation voltage corresponding to the selection data 128, 129 is a DAC circuit for generating a negative gradation voltage corresponding to the selection data 128, and 130 is D
The gray scale voltages generated by the AC circuits 128 and 129, 131 is a selection circuit for selecting a gray scale voltage corresponding to an adjacent output terminal, 132 is a selected gray scale voltage, and 133 is a liquid crystal panel 106 which amplifies the selected gray scale voltage. Output amplifier circuit.

FIGS. 10 and 11 show the circuit operation of the output amplifier circuit 133. The three switches SW1, SW2,
By switching SW3, the functions of the inverting amplifier and the forward amplifier are switched. FIG. 12 is a block diagram of an output amplifier circuit, FIG. 13 is a timing chart showing a liquid crystal driving voltage for one horizontal period, and FIG. 14 is a timing chart showing a liquid crystal driving voltage for two frame periods.

Next, the liquid crystal panel driving operation of the present invention will be described. In FIG. 1, a display signal group 101 sent from a system device such as a personal computer (not shown) generates a timing signal and a control signal for a liquid crystal driving circuit by a liquid crystal controller 102. The display data 107 is sent to the liquid crystal driver 103 in RG in synchronization with the data transmission clock 108.
It is transmitted serially in B2 pixel units. LCD driver 1
Assuming that the number of output gradations is 17, that is, 256 gradations, display data of a total of 48 bits is sequentially transmitted by 8 bits × 2 pixels for each of RGB. The liquid crystal driver 103 sequentially takes in the display data 107 at the data transmission clock 108 and takes in the display data for one line. When the data of one line is fetched, the latch circuit 1 is output in a horizontal cycle by the horizontal latch signal 130.
The display data is latched simultaneously in one line at 22.

The selection circuit 126 selects the display data of each two pixels corresponding to the adjacent output in accordance with the AC timing. The DAC circuit 128 has a positive gradation voltage, D
The AC circuit 129 generates a gray scale voltage of a negative polarity, so that the selection circuit 126 determines whether an adjacent output is a positive polarity or a negative polarity.
The selection circuit 131 selects the corresponding display data, and the selection circuit 131 selects the gradation voltage 130 so as to correspond to the output terminal. For example, when selling a positive polarity gradation voltage to the X1 terminal and a negative gradation voltage to the X2 terminal, the selection circuit 126 converts the display data corresponding to the X1 terminal into the DAC circuit 128 and the display data corresponding to the X2 terminal into the DAC circuit. The selection is made to correspond to the circuit 129. Then, in the DAC circuits 128 and 129,
A gradation voltage corresponding to the display data is generated, and the selection circuit 13
In step 1, a positive gradation voltage is selected for the X1 terminal and a negative gradation voltage is selected for the X2 terminal, and the data is amplified by the output amplifier circuit 133 and the data line of the liquid crystal panel 106 is driven.

On the other hand, when selling the negative gradation voltage to the X1 terminal and the positive gradation voltage to the X2 terminal, the selection circuit 126 outputs the display data corresponding to the X1 terminal to the DAC circuit 12.
9. The display data corresponding to the X2 terminal is
Select to correspond to Then, the DAC circuit 12
8 and 129, a gradation voltage corresponding to the display data is generated, and the selection circuit 131 supplies a negative gradation voltage to the X1 terminal.
A gray-scale voltage of positive polarity is selected for the X2 terminal, amplified by the output amplifier circuit 133, and drives the data line of the liquid crystal panel 106. The same operation is performed on and after the X3 terminal, thereby realizing dot inversion driving in which the polarity of the adjacent terminal is inverted.

Further, in this embodiment, as shown in FIG. 10, SW1, SW2, and SW3 are switched by the inversion signal 121, thereby inverting an amplifier circuit. As shown in FIG.
By switching W2 and SW3 with the inversion signal 121, it operates as a non-inverting amplifier circuit. As shown in FIG. 13, by making the inversion signal 121 valid during the beginning of the horizontal period, the output amplifier circuit 133 outputs a voltage inverted with respect to the common electrode reference voltage 113 during the inversion output period.
In other words, as shown in FIG.
In the case of outputting d1 +, during the inversion output period, a Vd1− voltage that is inverted with respect to the common electrode reference voltage 113 (Vcom) of the Vd1 + voltage is output, and then a predetermined gradation voltage Vd1 + corresponding to display data and AC polarity is output. Output. The drive waveform shown in FIG. 14 is obtained by performing this inversion output operation at every output terminal every horizontal period and every frame period.
The inversion output period is set according to the characteristics of the liquid crystal panel.

In this embodiment, FIG. 14 shows a driving waveform of the display pattern shown in FIG. 8, and a common electrode reference voltage 11 of a predetermined applied voltage is applied during the first inversion output period of the horizontal period.
By outputting the inverted output voltage based on the reference voltage 3, the bipolar voltage is always applied to the common electrode reference voltage 113 for each data line in one horizontal period. Therefore, the parasitic capacitance Cd1 shown in FIGS. , Cd2, the voltage fluctuation of the pixel electrode is reduced, and the image quality deterioration is improved.

Next, a second embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIGS. The second embodiment differs from the first embodiment in the inverted output operation. FIG. 15 is a configuration diagram of a liquid crystal panel driving circuit field to which the present invention is applied.
02, a shift register circuit for sequentially taking in display data inside the liquid crystal driver 1501; 1503, a display data bus output from the shift register; 1504, a control circuit for generating a timing signal inside the liquid crystal driver from the horizontal synchronization signal 109; Is a horizontal latch signal for simultaneously latching display data on the display data bus 1503 in the latch circuit 1507, 1509 is an inversion control circuit for generating an inversion signal from display data of each output, and 1518 is an output amplifier circuit 1
An inversion timing signal 516 indicates an output inversion timing, 1508 denotes output data of the latch circuit 1507, 15
Reference numeral 10 denotes a control circuit for generating a selection signal 1511 from the AC signal 110, reference numeral 1512 denotes a selection circuit for selecting display data of an output terminal corresponding to an adjacent pixel, reference numeral 1519 denotes selection data, and reference numeral 1513 denotes a positive polarity floor corresponding to the selection data 1519. DAC circuit 1514 for generating the adjustment voltage;
A DAC circuit for generating a negative polarity gradation voltage corresponding to 519, 1520 is a gradation voltage generated by the DAC circuits 1513 and 1514, 1515 is a selection circuit for selecting a gradation voltage corresponding to an adjacent output terminal, and 1521 is a selection circuit. Gradation voltage, 1
An output amplifier circuit 516 amplifies the selected gradation voltage and outputs the amplified voltage to the liquid crystal panel 106.

FIG. 16 is a block diagram of the output amplifier circuit 1516. By switching three switches SW1, SW2, and SW3, the functions of the inverting amplifier and the non-inverting amplifier are switched. FIG. 17 is a timing chart showing the liquid crystal driving voltage for one horizontal period, and FIG. 18 is a timing chart showing the liquid crystal driving voltage for two frame periods.

Next, the liquid crystal panel driving operation of the present invention will be described. In FIG. 15, a display signal group 101 sent from a system device (not shown) such as a personal computer generates a timing signal and a control signal for a liquid crystal driving circuit by a liquid crystal controller 102. The display data 107 is sent to the liquid crystal driver 103 in RG in synchronization with the data transmission clock 108.
It is transmitted serially in B2 pixel units. LCD driver 1
Assuming that the number of output gradations of 501 is 256 gradations, display data of a total of 48 bits is sequentially transmitted by 8 bits × 2 pixels for each of RGB.

In the liquid crystal driver 1501, the display data 1
07 is sequentially captured by the data transmission clock 108, and display data for one line is captured. Then, when data for one line is fetched, the display data is latched simultaneously in one line to the latch circuit 1507 in the horizontal cycle by the horizontal latch signal 1505. 1509 generates an inversion control signal 1518 from the display data 1508, and the selection circuit 1512 selects the display data of each two pixels corresponding to the adjacent output according to the AC timing. Since the DAC circuit 1513 generates a gray scale voltage of a positive polarity and the DAC circuit 1514 generates a gray scale voltage of a negative polarity, depending on whether an adjacent output is positive or negative,
The selection circuit 1512 selects the corresponding display data, and the selection circuit 1515 selects the gradation voltage 15 corresponding to the output terminal.
Select 20. For example, when selling a positive polarity gradation voltage to the X1 terminal and a negative polarity gradation voltage to the X2 terminal, the selection circuit 15
12, the display data corresponding to the X1 terminal is converted to the DAC circuit 1513, and the display data corresponding to the X2 terminal is converted to the DAC circuit.
The selection is made to correspond to the circuit 1514. And DA
The C circuits 1513 and 1514 generate gradation voltages corresponding to the display data. The selection circuit 1515 selects a positive gradation voltage for the X1 terminal and a negative gradation voltage for the X2 terminal. The liquid crystal panel 10 is amplified by 1516.
6 are driven. Conversely, the X1 terminal has a negative polarity,
In the case of selling the positive gradation voltage to the X2 terminal, the selection circuit 1512 selects the display data corresponding to the X1 terminal so as to correspond to the DAC circuit 1514 and the display data corresponding to the X2 terminal so as to correspond to the DAC circuit 1513. I do. Then, the DAC circuits 1513 and 1514 generate a gray scale voltage corresponding to the display data.
A negative gradation voltage is selected for the terminal and a positive gradation voltage is selected for the X2 terminal, and the data is amplified by the output amplifier circuit 1516 and the data line of the liquid crystal panel 106 is driven. The same operation is performed on and after the X3 terminal, thereby realizing dot inversion driving in which the polarity of the adjacent terminal is inverted.

Further, in this embodiment, SW1, SW2, and SW3 are switched by an inversion signal 1518 as shown in FIG. 16 to thereby obtain an inversion amplifier circuit as shown in FIGS.
Operates as a non-inverting amplifier circuit. In the present embodiment, FIG.
As shown in (5), a condition for inverting or not inverting according to the display data, that is, the value of the gradation voltage is set, and an inversion signal 1518 is generated from the display data by the inversion control circuit 1509 for each output. As shown in FIG. 17, in the data line Dn + 1, by inverting the signal 1518 during the beginning of the horizontal period, the output amplifier circuit 1516 outputs a voltage inverted with respect to the common electrode reference voltage 113 during the inverted output period. However, the data line Dn outputs a predetermined gradation voltage without being inverted.

That is, as shown in FIG. 18, when the grayscale voltage Vd1 is output to the data line, it is output without being inverted, and when the grayscale voltage Vd2- is output to the data line, Vd2 is output during the inverted output period. -Voltage common electrode reference voltage 113
(Vcom) and outputs an inverted Vd2 + voltage,
Thereafter, display data and a predetermined gradation voltage Vd2- corresponding to the AC polarity are output. By performing this inversion output operation in every horizontal period and every frame period in accordance with display data at all output terminals, a driving waveform shown in FIG. 17 is obtained. The inversion output period and the inversion gradation condition are set according to the characteristics of the liquid crystal panel.

In this embodiment, FIG. 17 shows a driving waveform of the display pattern shown in FIG. 8, and a common electrode reference voltage 11 of a predetermined applied voltage is applied during the first inversion output period of the horizontal period.
By outputting the inverted output voltage based on the reference voltage 3, the bipolar voltage is always applied to the common electrode reference voltage 113 for each data line in one horizontal period. Therefore, the parasitic capacitance Cd1 shown in FIGS. , Cd2, the voltage fluctuation of the pixel electrode is reduced, and the image quality deterioration is improved.

Next, a third embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIGS. 9 to 21. The third embodiment differs from the second embodiment in the output voltage operation and the circuit operation of the output amplifier circuit 1916 shown in FIG. 19 is different, but the other operations are the same. Therefore, this embodiment describes the operation of the output amplifier circuit. As shown in FIG.
1, the power supply voltage VCC during the inverted output period by SW2
Alternatively, it is configured to be connected to GND which is a ground voltage.

As shown in FIG. 21, the power supply voltage VCC is output from the output amplifier circuit 1916 during the inversion output period by making the inversion signal 1918 effective during the beginning of the horizontal period on the data line Dn + 1. Outputs a predetermined gradation voltage without inversion. When the grayscale voltage Vd1 is output to the data line, it is output without being inverted. When the grayscale voltage Vd2- is output to the data line, the power supply voltage VCC is output during the inverted output period.
A predetermined gradation voltage Vd2- corresponding to the AC polarity is output. The inversion output operation is performed in every horizontal period and every frame period in accordance with the display data at all the output terminals, so that the driving waveform shown in FIG. 21 is obtained. The inversion output period and the inversion gradation condition are set according to the characteristics of the liquid crystal panel.

In this embodiment, FIG. 21 shows a driving waveform of the display pattern shown in FIG. 8, and a common electrode reference voltage 11 of a predetermined applied voltage is applied during the first inversion output period of the horizontal period.
By outputting the inverted output voltage based on the reference voltage 3, the bipolar voltage is always applied to the common electrode reference voltage 113 for each data line in one horizontal period. Therefore, the parasitic capacitance Cd1 shown in FIGS. , Cd2, the voltage fluctuation of the pixel electrode is reduced, and the image quality deterioration is improved.

[0029]

According to the present invention, vertical smear and flicker can be reduced irrespective of the display pattern of the liquid crystal panel, and high image quality display by dot inversion driving can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of a liquid crystal display device to which the present invention is applied.

FIG. 2 is an equivalent circuit diagram of a pixel electrode.

FIG. 3 is an equivalent circuit diagram of a pixel electrode.

FIG. 4 is a diagram showing a display pattern.

FIG. 5 is a diagram showing a driving waveform.

FIG. 6 is a diagram showing a display pattern.

FIG. 7 is a diagram showing a driving waveform.

FIG. 8 is a diagram showing a display pattern.

FIG. 9 is a diagram showing a driving waveform.

FIG. 10 is a block diagram of an amplifier circuit.

FIG. 11 is a block diagram of an amplifier circuit.

FIG. 12 is a configuration diagram of an amplifier circuit.

FIG. 13 is a diagram showing a driving waveform.

FIG. 14 is a diagram showing a driving waveform.

FIG. 15 is a block diagram of one embodiment of a liquid crystal display device.

FIG. 16 is a configuration diagram of an amplifier circuit.

FIG. 17 is a diagram showing a driving waveform.

FIG. 18 is a diagram showing a driving waveform.

FIG. 19 is a block diagram of one embodiment of a liquid crystal display device.

FIG. 20 is a configuration diagram of an amplifier circuit.

FIG. 21 is a diagram showing a driving waveform.

FIG. 22 is a diagram showing an inversion condition.

[Explanation of symbols]

101: display signal, 102: liquid crystal controller, 103
.. Liquid crystal driver, 104 power supply circuit, 105 scanning circuit, 106 liquid crystal panel, 133 output amplifier circuit

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Tsutomu Furuhashi 1099 Ozenji Temple, Aso-ku, Kawasaki City, Kanagawa Prefecture Inside System Development Laboratory, Hitachi, Ltd. No. 1 In the Hitachi, Ltd. Semiconductor Group (72) Inventor Hirofumi Koshi 3300 Hayano, Mobara-shi, Chiba F-term in the Hitachi Display Group (reference) 2H093 NA31 NA43 NA51 NB07 NC22 NC26 NC35 NC59 ND03 ND10 5C006 AC26 BB16 BC11 BF25 FA22 FA23 FA25 FA37 5C080 AA10 BB05 DD05 DD06 DD10 EE29 FF11 JJ01 JJ02 JJ03 JJ04

Claims (7)

[Claims] 1. A liquid crystal display comprising a liquid crystal panel having a pixel portion arranged in a matrix, a scanning circuit for selecting a scanning line to which a voltage is applied, and a liquid crystal driver for outputting a liquid crystal application voltage corresponding to display data. The liquid crystal driver is provided with an output circuit for switching and outputting a gray scale voltage corresponding to display data and an AC polarity in a horizontal period and a voltage obtained by inverting the gray scale voltage with respect to a common electrode voltage of a liquid crystal panel. A liquid crystal display device characterized in that a voltage is switched and output during a period. 2. The liquid crystal display device according to claim 1, wherein the inverted output is switched according to display data conditions. 3. A liquid crystal display comprising a liquid crystal panel having pixel portions arranged in a matrix, a scanning circuit for selecting a scanning line to which a voltage is applied, and a liquid crystal driver for outputting a liquid crystal application voltage corresponding to display data. The liquid crystal driver is provided with an output circuit for switching and outputting a display voltage and a gray scale voltage corresponding to an AC polarity in a horizontal period, and a power supply voltage or a ground voltage in accordance with the AC polarity. A liquid crystal display device characterized in that the liquid crystal display device outputs the data. 4. A liquid crystal display device according to claim 3, wherein said output is switched according to display data conditions. 5. A liquid crystal display comprising a liquid crystal panel having pixel portions arranged in a matrix, a scanning circuit for selecting a scanning line to which a voltage is applied, and a liquid crystal driver for outputting a liquid crystal application voltage corresponding to display data. The liquid crystal driver is provided with an output circuit for switching and outputting a voltage level higher and lower than the common electrode voltage of the liquid crystal panel in the same horizontal period, and switching and outputting the voltage in the horizontal period. apparatus. 6. An output circuit for switching and outputting a gray scale voltage corresponding to display data and an AC polarity and a power supply voltage or a ground voltage corresponding to the AC polarity in the horizontal period, and switching the voltage in the horizontal period. A liquid crystal driver characterized by outputting to a liquid crystal panel. 7. An output circuit for switching and outputting a gray scale voltage corresponding to display data and an AC polarity and a voltage obtained by inverting the gray scale voltage with respect to a common electrode voltage of a liquid crystal panel during a horizontal period. A liquid crystal driver characterized in that the voltage is switched to output to a liquid crystal panel.